Log - b09cfb51ca2bc0ed4a019cc46dd20223b966a577 - toolchain/llvm-project

b09cfb5 Use inbounds GEPs for memcpy and memset lowering by Eli Bendersky · 10 years ago
a5740e0 AArch64: add comment missed out from earlier patch. by Tim Northover · 10 years ago
2d8315f ARM: Enable MachineScheduler and disable PostRAScheduler for swift. by Matthias Braun · 10 years ago
494a381 Use small encodings for constants when possible. by Rafael Espindola · 10 years ago
da3d0d7 Arm: Don't define a label twice with two setjmps in a function. by Matthias Braun · 10 years ago
3cd00c1 Fix __builtin_setjmp in combination with sjlj exception handling. by Matthias Braun · 10 years ago
9152528 Fix spelling. NFCI. by Simon Pilgrim · 10 years ago
ca0ffc3 AArch64: make inexact signalling on round Darwin-specific by Tim Northover · 10 years ago
54cced5 [PowerPC] v4i32 is a VSRCRegClass by Bill Schmidt · 10 years ago
f871e09 Streamline the coding style in NVPTXLowerAggrCopies by Eli Bendersky · 10 years ago
e7981ce [NVPTX] enable SpeculativeExecution in NVPTX by Jingyue Wu · 10 years ago
af7d770 AArch64: Implement conditional compare sequence matching. by Matthias Braun · 10 years ago
78655fc AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand by Tom Stellard · 10 years ago
c98ee20 AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsets by Tom Stellard · 10 years ago
f4ce569 Revert "Add missing load/store flags to thumb2 instructions." by Pete Cooper · 10 years ago
5dfd8b6 [NVPTX] Don't leak dead instructions after unlinking them from the BasicBlock by Benjamin Kramer · 10 years ago
f14af16 Correct lowering of memmove in NVPTX by Eli Bendersky · 10 years ago
ff5efb8 AMDGPU/R600: Remove unused variable by Tom Stellard · 10 years ago
1d46fb2 AMDPGU/R600: Replace llvm_unreachable() call with LLVMContext::emitError() by Tom Stellard · 10 years ago
dadb847 [X86] Reapply r240257 : "Allow more call sequences to use push instructions for argument passing" by Michael Kuperstein · 10 years ago
e1ea4e7d [X86] Fix emitPrologue() to make less assumptions about pushes by Michael Kuperstein · 10 years ago
7d54fab [Mips] Make helper function static, NFC. by Benjamin Kramer · 10 years ago
e029eae Add missing break in switch case in R600ISelLowering by Mehdi Amini · 10 years ago
bd7287e Move most user of TargetMachine::getDataLayout to the Module one by Mehdi Amini · 10 years ago
5c0fa58 Remove DataLayout from TargetLoweringObjectFile, redirect to Module by Mehdi Amini · 10 years ago
938bd6f Revert "[X86] Allow more call sequences to use push instructions for argument passing" by Reid Kleckner · 10 years ago
024d91a [ARM] Define a subtarget feature that is used to avoid using movt/movw by Akira Hatanaka · 10 years ago
e3c8161 Clear kill flags in ARMLoadStoreOptimizer. by Pete Cooper · 10 years ago
5d1f12d TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() by Matthias Braun · 10 years ago
ad61f34 Revert "Look through PHIs to find additional register sources" by Bruno Cardoso Lopes · 10 years ago
21ca199 Add missing load/store flags to thumb2 instructions. by Pete Cooper · 10 years ago
1e77bb1 [PPC64LE] Fix vec_sld semantics for little endian by Bill Schmidt · 10 years ago
fadd4fe Look through PHIs to find additional register sources by Bruno Cardoso Lopes · 10 years ago
c11fd3e [PPC] Disassemble little endian ppc instructions in the right byte order by Benjamin Kramer · 10 years ago
5d36b23 [PowerPC] Use the MachineCombiner to reassociate fadd/fmul by Hal Finkel · 10 years ago
673b493 [PowerPC] Extend physical register live range in PPCVSXFMAMutate by Hal Finkel · 10 years ago
097adfb [AArch64] Fix problems in decoding generic MSR instructions by Petr Pavlu · 10 years ago
096e8b0 AVX : Fix ISA disabling in case AVX512VL , some instructions should be disabled only if AVX512BW present. by Igor Breger · 10 years ago
e46f7ef Change conditional to assert. NFC. by Pete Cooper · 10 years ago
7e64ef0 Use more foreach loops in SelectionDAG. NFC by Pete Cooper · 10 years ago
c8f48c1 WebAssembly: fix build breakage. by JF Bastien · 10 years ago
4012024 [PowerPC] Support symbolic targets in patchpoints by Hal Finkel · 10 years ago
9bbad03 [PowerPC] Use the ABI indirect-call protocol for patchpoints by Hal Finkel · 10 years ago
65c6940 Add allnodes() iterator range to SelectionDAG. NFC. by Pete Cooper · 10 years ago
d9767a3 WebAssembly: add basic int/fp instruction codegen. by JF Bastien · 10 years ago
fdfaae4 Fix NDEBUG build warning by Krzysztof Parzyszek · 10 years ago
2e82883 Fix Windows build: replace __func__ with LLVM_FUNCTION_NAME by Krzysztof Parzyszek · 10 years ago
9e6dea1 [MMX] Use the appropriate instructions for GR64 <-> VR64 copies. by Bruno Cardoso Lopes · 10 years ago
8acae52 [PowerPC] Fix the PPCInstrInfo::getInstrLatency implementation by Hal Finkel · 10 years ago
7587447 [Hexagon] Generate instructions for operations on predicate registers by Krzysztof Parzyszek · 10 years ago
2469211 AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32) by Matt Arsenault · 10 years ago
84db5d9 AMDGPU/SI: Fix read2 merging into a super register. by Matt Arsenault · 10 years ago
9912bb8 MachineRegisterInfo: Remove UsedPhysReg infrastructure by Matthias Braun · 10 years ago
984a361 Add missing builtins to the PPC back end for ABI compliance (vol. 4) by Nemanja Ivanovic · 10 years ago
0256486 PrologEpilogInserter: Rewrite API to determine callee save regsiters. by Matthias Braun · 10 years ago
c962d4f AArch64: add rev64 alias for 64-bit rev instruction. by Tim Northover · 10 years ago
a0ecf07 [Hexagon] Generate "extract" instructions more aggressively by Krzysztof Parzyszek · 10 years ago
61f9efe ARMAsmParser: Take MCInst param by const-ref by Hans Wennborg · 10 years ago
e48fe2a AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions by Tom Stellard · 10 years ago
a927a86 Silencing two MSVC warnings; 'argument' : truncation from 'unsigned int' to 'int16_t' and truncation of constant value. NFC intended. by Aaron Ballman · 10 years ago
03f9c01 [mips] Fix li/la differences between IAS and GAS. by Daniel Sanders · 10 years ago
d1ba2d9 Generate correct asm info for mingw and cygwin ARM targets. by Yaron Keren · 10 years ago
0b305db Prune trailing whitespaces and CRs. by NAKAMURA Takumi · 10 years ago
15deb80 [PPC64LE] More improvements to VSX swap optimization by Bill Schmidt · 10 years ago
d886151 [Hexagon] Move BitTracker into the llvm namespace and remove redundant qualifications by Benjamin Kramer · 10 years ago
ca95d44 AMDGPU: Minor cleanups to always inline pass by Matt Arsenault · 10 years ago
4c8ca53 Enable partial and runtime loop unrolling for NVPTX. by Mark Heffernan · 10 years ago
5f4dd92 [WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name by Reid Kleckner · 10 years ago
db5a11f AMDGPU/SI: Select mad patterns to v_mac_f32 by Tom Stellard · 10 years ago
0a43abc ARM: Fix cttz expansion on vector types. by Logan Chien · 10 years ago
69bf1ce [ARM] Handle commutativity when converting to tADDhirr in Thumb2 by Scott Douglass · 10 years ago
d9d8d26 [ARM] Add Thumb2 ADD with SP narrowing from 3 operand to 2 by Scott Douglass · 10 years ago
039f768 [ARM] Small refactor of tryConvertingToTwoOperandForm (nfc) by Scott Douglass · 10 years ago
6d8f785 Removing several -Wunused-but-set-variable warnings; NFC intended. by Aaron Ballman · 10 years ago
0f37093 AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types. by Elena Demikhovsky · 10 years ago
1ef7a0f [ARM] Add support for nest attribute using r12 by Renato Golin · 10 years ago
4f50052 [X86][SSE] (V)PMINSB is commutable. by Simon Pilgrim · 10 years ago
ae5cd27 Trim trailing whitespaces. NFC. by Simon Pilgrim · 10 years ago
64cc4ad [X86][SSE] Vectorized v4i32 non-uniform shifts. by Simon Pilgrim · 10 years ago
cbf0892 [PowerPC] Make use of the TargetRecip system by Hal Finkel · 10 years ago
965cea5 [PowerPC] Support the nest parameter attribute by Hal Finkel · 10 years ago
e463e47 MC: Only allow changing feature bits in MCSubtargetInfo by Duncan P. N. Exon Smith · 10 years ago
cf13d18 AMDGPU: Fix chains for memory ops dependent on argument loads by Matt Arsenault · 10 years ago
754e21f MC: Remove MCSubtargetInfo() default constructor by Duncan P. N. Exon Smith · 10 years ago
bb57d73 MC: Remove MCSubtargetInfo::InitCPUSched() by Duncan P. N. Exon Smith · 10 years ago
0d51973 AMDGPU: Use requested chain when lowering arguments by Matt Arsenault · 10 years ago
e5a112f ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920 by Matthias Braun · 10 years ago
00b3020 Fix AArch64 prologue for empty frame with dynamic allocas. by Evgeniy Stepanov · 10 years ago
a277561 [TTI] BasicTTIImpl assumes no vector registers by Jingyue Wu · 10 years ago
d9bd22b ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code by Matthias Braun · 10 years ago
e4ba6b8 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 by Matthias Braun · 10 years ago
5ca0bac WebAssembly: basic instructions todo, and basic register info. by JF Bastien · 10 years ago
b73a2ed Target RegisterInfo: devirtualize TargetFrameLowering by JF Bastien · 10 years ago
a4a3182d ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic. by Matthias Braun · 10 years ago
5c0039a Actually support volatile memcpys in NVPTX lowering by Eli Bendersky · 10 years ago
d9e4b4f NFC. Added a blank line for consistency. by Nemanja Ivanovic · 10 years ago
5655fb3 Add missing builtins to the PPC back end for ABI compliance (vol. 3) by Nemanja Ivanovic · 10 years ago
ad85c8c [NVPTX] declare no vector registers by Jingyue Wu · 10 years ago
85a2450 [WinEH] Make sure LSDA tables are 4 byte aligned by Reid Kleckner · 10 years ago
d880520 Replace index-loops by range-based loops by Eli Bendersky · 10 years ago