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gerrit-public.fairphone.software / toolchain / llvm-project / b13c91f159fa9b631cb15dc02ea0b72b2802ac4d / llvm / lib / CodeGen / TargetSchedule.cpp
  1. 4a9a4e1 [MISched] Explanatory error message when machine model is not complete. NFC by MinSeong Kim · 10 years ago
  2. 244a677 Use llvm_unreachable() instead of report_fatal_error() if the machine model is incomplete by Matthias Braun · 10 years ago
  3. 7a247f7 Turn effective assert(0) into llvm_unreachable by Matthias Braun · 10 years ago
  4. 42e1e66 TargetSchedule: factor out common code; NFC by Matthias Braun · 10 years ago
  5. 307c2cb Remove unnecessary TargetMachine.h includes. by Eric Christopher · 11 years ago
  6. 1175945 Change MCSchedModel to be a struct of statically initialized data. by Pete Cooper · 11 years ago
  7. fc6de42 Have MachineFunction cache a pointer to the subtarget to make lookups by Eric Christopher · 11 years ago
  8. d913448 Remove the TargetMachine forwards for TargetSubtargetInfo based by Eric Christopher · 11 years ago
  9. 5e1207e MachineCombiner Pass for selecting faster instruction by Gerolf Hoflehner · 11 years ago
  10. e69170a Revert "Introduce a string_ostream string builder facilty" by Alp Toker · 11 years ago
  11. 6147173 Introduce a string_ostream string builder facilty by Alp Toker · 11 years ago
  12. d2f96b9 IfConverter: Use TargetSchedule for instruction latencies by Arnold Schwaighofer · 12 years ago
  13. b6854d8 Mark the x86 machine model as incomplete. PR17367. by Andrew Trick · 12 years ago
  14. 5d486186 MI-Sched: handle ReadAdvance latencies as used by Swift. by Andrew Trick · 12 years ago
  15. de2109e Machine Model: Add MicroOpBufferSize and resource BufferSize. by Andrew Trick · 12 years ago
  16. be2bccb MI-Sched cleanup. If an instruction has no valid sched class, do not attempt to check for a variant. by Andrew Trick · 13 years ago
  17. 6057017 Change the default latency for implicit defs. by Andrew Trick · 13 years ago
  18. ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  19. e96390e misched: TargetSchedule interface for machine resources. by Andrew Trick · 13 years ago
  20. 0b1d8d0 misched: Better handling of invalid latencies in the machine model by Andrew Trick · 13 years ago
  21. 5f35afb misched: Handle "transient" non-instructions. by Andrew Trick · 13 years ago
  22. c334bd4 misched: fall-back to a target hook for instr bundles. by Andrew Trick · 13 years ago
  23. dd79f0f misched: Use the TargetSchedModel interface wherever possible. by Andrew Trick · 13 years ago
  24. 780fae8 misched: Add computeInstrLatency to TargetSchedModel. by Andrew Trick · 13 years ago
  25. cfcf520 misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule. by Andrew Trick · 13 years ago
  26. 8abcf4d Enable -schedmodel, but prefer itineraries until we have more benchmark data. by Andrew Trick · 13 years ago
  27. f2b70d9 TargetSchedule: cleanup computeOperandLatency logic & diagnostics. by Andrew Trick · 13 years ago
  28. 6e6d597 TargetSchedModel API. Implement latency lookup, disabled. by Andrew Trick · 13 years ago
  29. 8e7f202 Revert r164061-r164067. Most of the new subtarget emitter. by Andrew Trick · 13 years ago
  30. f403ee7 TargetSchedModel API. Implement latency lookup, disabled. by Andrew Trick · 13 years ago
  31. d2a19da TargetSchedModel interface. To be implemented... by Andrew Trick · 13 years ago