Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / b13ef17a149973087d8b11c716b3574e820deeed / llvm / lib / CodeGen / MachineScheduler.cpp
  1. b13ef17 MI Sched: Update the way resources are tracked so the current heuristics make more sense. by Andrew Trick · 12 years ago
  2. b55db58 MI-Sched: cleanup DEBUG output. by Andrew Trick · 12 years ago
  3. 736dd9a MI-Sched: Adjust regpressure limits for reserved regs. by Andrew Trick · 12 years ago
  4. 71f08a3 Give RegMax higher priority. by Andrew Trick · 12 years ago
  5. 3c3a40e Remove compareRPDelta. by Andrew Trick · 12 years ago
  6. 7e63046 MI-Sched: Remove another heuristic that is sensitive to queue order. by Andrew Trick · 12 years ago
  7. d40d0f2 MI-Sched: Track multiple candidates with the same priority level. by Andrew Trick · 12 years ago
  8. 8e8415f Missing NDEBUGs. by Andrew Trick · 12 years ago
  9. f78e7fa MI-Sched: heuristics using the new latency and machine model. by Andrew Trick · 12 years ago
  10. de2109e Machine Model: Add MicroOpBufferSize and resource BufferSize. by Andrew Trick · 12 years ago
  11. e2ff575 MI-Sched: Rename IssueCount to CurrMOps. by Andrew Trick · 12 years ago
  12. 0cd8afc MI-Sched: Remove the temporary EnableCopyConstrain flag. by Andrew Trick · 12 years ago
  13. f5b8ef2 MI-Sched: added tracking of dependent latency for better heuristics. by Andrew Trick · 12 years ago
  14. 5580e5c MI-Sched: DEBUG: print critical resource. by Andrew Trick · 12 years ago
  15. 80df8b8 Move #include from .h to .cpp file. by Jakub Staszak · 12 years ago
  16. dd77014 MI Sched: revert a minor heuristic that snuck in with -misched-vcopy. by Andrew Trick · 13 years ago
  17. 2e87517 Fix for r180193 - MI Sched: eliminate local vreg. by Andrew Trick · 13 years ago
  18. 85a1d4c MI Sched: eliminate local vreg copies. by Andrew Trick · 13 years ago
  19. 7c791a3 MI Sched: regpressure tracing. by Andrew Trick · 13 years ago
  20. 1f0bb69 MI-Sched: DEBUG formatting. by Andrew Trick · 13 years ago
  21. e833e1c MI-Sched: schedule physreg copies. by Andrew Trick · 13 years ago
  22. 80e66ce RegisterPressure heuristics currently require signed comparisons. by Andrew Trick · 13 years ago
  23. 96ce384 Disable DFSResult for ConvergingScheduler. by Andrew Trick · 13 years ago
  24. 419d491 MachineScheduler: format DEBUG output. by Andrew Trick · 13 years ago
  25. 4ab769f Fix missing std::. Not sure how this compiles for anyone else. by Matt Arsenault · 13 years ago
  26. df17ddd Cleanup #includes. by Jakub Staszak · 13 years ago
  27. 48f2a72 Add -verify-misched option. by Andrew Trick · 13 years ago
  28. 87609f5 Use const reference instead of vector object when passing an argument to by Jakub Staszak · 13 years ago
  29. 553e0fe MIsched: HazardRecognizers are created for each DAG. Free them. by Andrew Trick · 13 years ago
  30. 399c9bf MIsched: cleanup code. Use isBoundaryNode(). by Andrew Trick · 13 years ago
  31. c641ada Use const reference instead of vector copying. by Jakub Staszak · 13 years ago
  32. 54b2ce3 MIsched: Print block name. No functionality. by Andrew Trick · 13 years ago
  33. ea9fd95 MachineScheduler support for viewGraph. by Andrew Trick · 13 years ago
  34. e2c3f5c MIsched: Improve the interface to SchedDFS analysis (subtrees). by Andrew Trick · 13 years ago
  35. 44f750a MISched: Add SchedDFSResult to ScheduleDAGMI to formalize the by Andrew Trick · 13 years ago
  36. 92da424 MachineScheduler: enable biasCriticalPath for all DAGs. by Andrew Trick · 13 years ago
  37. 5907292 Follow-up typo correction from building the wrong branch. by Andrew Trick · 13 years ago
  38. ae182ce Fix typo from r170452. Affects -enable-misched heuristics. by Andrew Trick · 13 years ago
  39. 9f0b95f MIsched: add an ILP window property to machine model. by Andrew Trick · 13 years ago
  40. ef23569 MISched: Cleanup, redundant statement. by Andrew Trick · 13 years ago
  41. d6d5ad3 MISched: Heuristics, compare latency more precisely. It matters more for some targets. by Andrew Trick · 13 years ago
  42. 44f54d9 MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to compute it. by Andrew Trick · 13 years ago
  43. 493b867 MISched: cleanup, use the proper iterator type. by Andrew Trick · 13 years ago
  44. ffb6168 MISched: minor improvement, initialize remaining resources before the first scheduling decision. by Andrew Trick · 13 years ago
  45. ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  46. b767d1e misched: Fix RegisterPressureTracker handling of DebugVals. by Andrew Trick · 13 years ago
  47. e7ea8aa misched: fix RegionBegin when DebugValues get shuffled to the top. by Andrew Trick · 13 years ago
  48. aa598b3 misched: Recompute priority queue when DFSResults are updated. by Benjamin Kramer · 13 years ago
  49. 48d392e misched: Analysis that partitions the DAG into subtrees. by Andrew Trick · 13 years ago
  50. cd1c2f9 misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics. by Andrew Trick · 13 years ago
  51. cf7e697 misched: Debug output fix. Use an always valid iterator. by Andrew Trick · 13 years ago
  52. 108c88c misched: Allow subtargets to enable misched and dependent options. by Andrew Trick · 13 years ago
  53. ec369d5 misched: rename interfaceto avoid gcc warnings by Andrew Trick · 13 years ago
  54. 26328024 misched: Target-independent support for MacroFusion. by Andrew Trick · 13 years ago
  55. a7714a0 misched: Target-independent support for load/store clustering. by Andrew Trick · 13 years ago
  56. f1ff84c misched: Infrastructure for weak DAG edges. by Andrew Trick · 13 years ago
  57. c280f41 Silence GCC warning about falling off the end of a non-void function. by Benjamin Kramer · 13 years ago
  58. 3ca33ac misched: Heuristics based on the machine model. by Andrew Trick · 13 years ago
  59. 4d1fa71 misched: Rename RemainingCount to avoid confusion with remaining resources. by Andrew Trick · 13 years ago
  60. d9d4be0 misched: Added handleMove support for updating all kill flags, not just for allocatable regs. by Andrew Trick · 13 years ago
  61. 90f711d misched: ILP scheduler for experimental heuristics. by Andrew Trick · 13 years ago
  62. dd79f0f misched: Use the TargetSchedModel interface wherever possible. by Andrew Trick · 13 years ago
  63. 984d98b misched: avoid scheduling an instruction twice. by Andrew Trick · 13 years ago
  64. a2733e9 misched: add a hook for custom DAG postprocessing. by Andrew Trick · 13 years ago
  65. 19f49ac Release build: guard dump functions with by Manman Ren · 13 years ago
  66. 7a8e100 Reorganize MachineScheduler interfaces and publish them in the header. by Andrew Trick · 13 years ago
  67. 742534c Release build: guard dump functions with "ifndef NDEBUG" by Manman Ren · 13 years ago
  68. ae53561 Simplify the computeOperandLatency API. by Andrew Trick · 13 years ago
  69. a538d83 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. by Craig Topper · 13 years ago
  70. 35521e2 Fix a typo (the the => the) by Sylvestre Ledru · 13 years ago
  71. 87255e3 I'm introducing a new machine model to simultaneously allow simple by Andrew Trick · 13 years ago
  72. 2f26b34 misched: allow NULL InstrItineraries. by Andrew Trick · 13 years ago
  73. 8c9e672 misched: avoid scheduling instructions that can't be dispatched. by Andrew Trick · 13 years ago
  74. ce27bb9 misched: count micro-ops toward the issue limit. by Andrew Trick · 13 years ago
  75. b9f84bb Guard private fields that are unused in Release builds with #ifndef NDEBUG. by Benjamin Kramer · 13 years ago
  76. 05ff466 Move RegisterClassInfo.h. by Andrew Trick · 13 years ago
  77. 88517f6 Move RegisterPressure.h. by Andrew Trick · 13 years ago
  78. 4544606 misched: API for minimum vs. expected latency. by Andrew Trick · 13 years ago
  79. d36adec misched: comments from code review. by Andrew Trick · 13 years ago
  80. 4e7f6a7 misched: trace formatting by Andrew Trick · 13 years ago
  81. 85d8f0c Silence unused variable warnings from when assertions are disabled. by Kaelyn Uhrain · 13 years ago
  82. a306a8a misched: Use the same scheduling heuristics with -misched-topdown/bottomup. by Andrew Trick · 13 years ago
  83. 79d3eec misched: Trace regpressure. by Andrew Trick · 13 years ago
  84. a8ad5f7 misched: Give each ReadyQ a unique ID by Andrew Trick · 13 years ago
  85. 61f1a27 misched: Added ScoreboardHazardRecognizer. by Andrew Trick · 13 years ago
  86. ca47335 misched: Release bottom roots in reverse order. by Andrew Trick · 13 years ago
  87. dd375dd misched: rename ReadyQ class by Andrew Trick · 13 years ago
  88. f378617 misched: copy comments so compareRPDelta is readable by itself. by Andrew Trick · 13 years ago
  89. 6a50baa comments by Andrew Trick · 13 years ago
  90. 276a3e8 misched: trace ReadyQ. by Andrew Trick · 13 years ago
  91. 2202577 misched: Added 3-level regpressure back-off. by Andrew Trick · 13 years ago
  92. 47a1fea comment by Andrew Trick · 13 years ago
  93. 463b2f1 misched: fix liveness iterators by Andrew Trick · 13 years ago
  94. c5d7008 misched: Print machineinstrs with -debug-only=misched by Andrew Trick · 13 years ago
  95. 419eae2 misched: tracing register pressure heuristics. by Andrew Trick · 13 years ago
  96. 7ee9de5 misched: Add register pressure backoff to ConvergingScheduler. by Andrew Trick · 13 years ago
  97. 795c112 misched: Release only unscheduled nodes into ReadyQ. by Andrew Trick · 13 years ago
  98. 95dafd8 misched: Added ReadyQ container wrapper for Top and Bottom Queues. by Andrew Trick · 13 years ago
  99. 4add42f misched: Introducing Top and Bottom register pressure trackers during scheduling. by Andrew Trick · 13 years ago
  100. 4d4b546 Fix a naughty header include that breaks "installed" builds. by Andrew Trick · 14 years ago