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gerrit-public.fairphone.software / toolchain / llvm-project / b26592e04d59666b54c3221528f299fc9b10768c / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
  1. b26592e [AArch64] Create a TargetInfo header. NFC by Richard Trieu · 6 years ago
  2. ff6875a AArch64: support binutils-like things on arm64_32. by Tim Northover · 6 years ago
  3. aa49be4 Avoid cppcheck operator precedence warnings. NFCI. by Simon Pilgrim · 6 years ago
  4. 9142b8e [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions by David Spickett · 7 years ago
  5. 474f5d9 AArch64: enforce even/odd register pairs for CASP instructions. by Tim Northover · 7 years ago
  6. 2946cd7 Update the file headers across all of the LLVM projects in the monorepo by Chandler Carruth · 7 years ago
  7. c419028 [AArch64][v8.5A] Add Memory Tagging instructions by Oliver Stannard · 7 years ago
  8. 8459d34 [AArch64][v8.5A] Add speculation restriction system registers by Oliver Stannard · 7 years ago
  9. 31af178 [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag by Oliver Stannard · 7 years ago
  10. 27c769d [Target] Untangle disassemblers by Benjamin Kramer · 7 years ago
  11. ceabd50 [AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions (cont'd) by Sjoerd Meijer · 7 years ago
  12. 83a2a62 [AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions by Sjoerd Meijer · 7 years ago
  13. bc5c7f2 [AArch64] Make function parameter names in declarations match those of definitions by Fangrui Song · 7 years ago
  14. 8cd1f53 [AArch64][SVE] Asm: Support for FMUL (indexed) by Sander de Smalen · 7 years ago
  15. 18ac8f9 [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions. by Sander de Smalen · 7 years ago
  16. 97ca6b9 [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction. by Sander de Smalen · 7 years ago
  17. 6277079 [AArch64][SVE] Asm: Support for DUP (immediate) instructions. by Sander de Smalen · 7 years ago
  18. 30f9f11 [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions. by Sander de Smalen · 8 years ago
  19. 367694b [AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes. by Sander de Smalen · 8 years ago
  20. 7a210db [AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions. by Sander de Smalen · 8 years ago
  21. d239eb3 [AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions. by Sander de Smalen · 8 years ago
  22. f836af8 [AArch64][SVE] Asm: Support for structured LD2 (scalar+imm) load instructions. by Sander de Smalen · 8 years ago
  23. 81fcf86 [AArch64][SVE] Asm: Add AND_ZI instructions and aliases by Sander de Smalen · 8 years ago
  24. 906a5de Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions by Sander de Smalen · 8 years ago
  25. 6595603 Reverted r322073 because of AddressSanitizer failure on by Sander de Smalen · 8 years ago
  26. 1f97363 [AArch64][SVE] Asm: Add predicated ADD/SUB instructions by Sander de Smalen · 8 years ago
  27. dc5e081 [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors. by Sander de Smalen · 8 years ago
  28. cd6be96 [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2 by Sander de Smalen · 8 years ago
  29. 37517a2 Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo by Reid Kleckner · 8 years ago
  30. ce1e097 [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support by Sander de Smalen · 8 years ago
  31. 6a3bf1f Reverted r319315 because of unused functions (due to PPR not yet being by Sander de Smalen · 8 years ago
  32. 2b6338b [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support by Sander de Smalen · 8 years ago
  33. 91f11e5 [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support by Florian Hahn · 8 years ago
  34. 25efe76 [AArch64] Fix for buildbots, unused function by Sam Parker · 8 years ago
  35. 96f8959 [AArch64] Remove DecodeAuthLoadWriteback by Sam Parker · 8 years ago
  36. 6d42de7 [AArch64] Enable ARMv8.3-A pointer authentication by Sam Parker · 8 years ago
  37. 96d933d [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
  38. cb07d67 Fix some more -Wimplicit-fallthrough warnings. NFCI. by Simon Pilgrim · 8 years ago
  39. f42454b Move the global variables representing each Target behind accessor function by Mehdi Amini · 9 years ago
  40. b03fd12 Replace "fallthrough" comments with LLVM_FALLTHROUGH by Justin Bogner · 9 years ago
  41. 45513a8 Minor code cleanups. NFC. by Junmo Park · 9 years ago
  42. e6ae676 AArch64: TableGenerate system instruction operands. by Tim Northover · 9 years ago
  43. 911ea20 [AArch64] Add ARMv8.2-A UAO PSTATE bit by Oliver Stannard · 10 years ago
  44. 1bab191 [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for by Alexandros Lamprineas · 10 years ago
  45. 50f1723 Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC. by Daniel Sanders · 10 years ago
  46. 153010c Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC. by Daniel Sanders · 10 years ago
  47. c40de48 Revert r247684 - Replace Triple with a new TargetTuple ... by Daniel Sanders · 10 years ago
  48. 18d4b0d Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC. by Daniel Sanders · 10 years ago
  49. f423f56 Change the last few internal StringRef triples into Triple objects. by Daniel Sanders · 10 years ago
  50. 5f6f60d [AArch64] Add v8.1a atomic instructions by Vladimir Sukharev · 10 years ago
  51. e9119e4 MC: Modernize MCOperand API naming. NFC. by Jim Grosbach · 10 years ago
  52. d49cb8f [AArch64] Add v8.1a "Limited Ordering Regions" extension by Vladimir Sukharev · 11 years ago
  53. a98f689 [AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget features. by Vladimir Sukharev · 11 years ago
  54. 186db43 unique_ptrify the RelInfo parameter to TargetRegistry::createMCSymbolizer by David Blaikie · 11 years ago
  55. 7fc5b87 Pass an ArrayRef to MCDisassembler::getInstruction. by Rafael Espindola · 11 years ago
  56. 4aa6bea Misc style fixes. NFC. by Rafael Espindola · 11 years ago
  57. e493f17 [AArch64] Allow access to all system registers with MRS/MSR instructions. by Tom Coxon · 11 years ago
  58. 2c13e71 [AArch64] Remove unnecessary whitespace. (Test commit) by Tom Coxon · 11 years ago
  59. 729b12e Fix left shifts of negative integers in AArch64 InstPrinter/Disassembler by Alexey Samsonov · 11 years ago
  60. 1f8930e Run sort_includes.py on the AArch64 backend. by Benjamin Kramer · 11 years ago
  61. 35910d7 AArch64: remove "arm64_be" support in favour of "aarch64_be". by Tim Northover · 11 years ago
  62. 3b0846e AArch64/ARM64: move ARM64 into AArch64's place by Tim Northover · 11 years ago[Renamed (69%) from llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp]
  63. cc08e1f AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. by Tim Northover · 11 years ago
  64. 4a3ab28 ARM64: model pre/post-indexed operations properly. by Tim Northover · 11 years ago
  65. c350acf ARM64: separate load/store operands to simplify assembler by Tim Northover · 11 years ago
  66. c3b931d [ARM64] Split tbz/tbnz into W/X register variant by Bradley Smith · 11 years ago
  67. e0483f9c [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted by Bradley Smith · 11 years ago
  68. 618850b AArch64/ARM64: implement diagnosis of unpredictable loads & stores by Tim Northover · 11 years ago
  69. 523b5a4 ARM64: refactor NEON post-indexed loads & stores (MC). by Tim Northover · 11 years ago
  70. f57d5ca [ARM64] Conditionalize CPU specific system registers on subtarget features by Bradley Smith · 11 years ago
  71. d53a671 AArch64/ARM64: expunge CPSR from the sources by Tim Northover · 11 years ago
  72. 79ec019 AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands by Tim Northover · 12 years ago
  73. 650cb57 [ARM64] Add a big endian version of the ARM64 target machine, and update all users. by James Molloy · 12 years ago
  74. 84e68b2 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 12 years ago
  75. d174b72 [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some by Chandler Carruth · 12 years ago
  76. 9d205d4 ARM64: Extended addressing mode source reg is 64-bit. by Jim Grosbach · 12 years ago
  77. a1bc0f5 [MC] Require an MCContext when constructing an MCDisassembler. by Lang Hames · 12 years ago
  78. 30120c0 Make helper static and place random global into the llvm namespace. by Benjamin Kramer · 12 years ago
  79. 95400e2 Remove redundant symbolization support from MCDisassembler interface. by Lang Hames · 12 years ago
  80. a2308f4 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. by Bradley Smith · 12 years ago
  81. a19b7e8 [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. by Bradley Smith · 12 years ago
  82. af2710c [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. by Bradley Smith · 12 years ago
  83. eb4ca04 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. by Bradley Smith · 12 years ago
  84. 4925be9 [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. by Bradley Smith · 12 years ago
  85. 08c391c [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. by Bradley Smith · 12 years ago
  86. 2ba17a4 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. by Bradley Smith · 12 years ago
  87. 8c0b88c [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. by Bradley Smith · 12 years ago
  88. 35cadc5 [ARM64] STRHro and STRBro were not being decoded at all. by Bradley Smith · 12 years ago
  89. 87c60e0 [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4. by Bradley Smith · 12 years ago
  90. cd91e5c [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined. by Bradley Smith · 12 years ago
  91. d1726ee Fixing warnings in the MSVC build. No functional changes intended. by Aaron Ballman · 12 years ago
  92. 23aaf2a Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() always initialize Size argument. by Alexey Samsonov · 12 years ago
  93. 7b7a67c [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is by Chandler Carruth · 12 years ago
  94. 00ed996 ARM64: initial backend import by Tim Northover · 12 years ago