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gerrit-public.fairphone.software / toolchain / llvm-project / bc041b82d44b51a3b7da79c38e4052e28ff8011c / llvm / lib / Target / AMDGPU / SILoadStoreOptimizer.cpp
  1. 7de74af Add optimization bisect opt-in calls for AMDGPU passes by Andrew Kaylor · 9 years ago
  2. ecc7cbf Test commit access by Konstantin Zhuravlyov · 10 years ago
  3. 3ac9cc6 CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC by Duncan P. N. Exon Smith · 10 years ago
  4. 84db5d9 AMDGPU/SI: Fix read2 merging into a super register. by Matt Arsenault · 10 years ago
  5. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/SILoadStoreOptimizer.cpp]
  6. 381a94a R600/SI: Remove explicit m0 operand from DS instructions by Tom Stellard · 10 years ago
  7. 799003b Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. by Benjamin Kramer · 11 years ago
  8. 065e3d4 R600/SI: Move gds operand to the end of operand list by Tom Stellard · 11 years ago
  9. 7792e32 Reuse a bunch of cached subtargets and remove getSubtarget calls by Eric Christopher · 11 years ago
  10. 0d2832a R600/SI: Fix live range error hidden by SIFoldOperands by Matt Arsenault · 11 years ago
  11. a99ada5 R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction by Tom Stellard · 11 years ago
  12. da00cf5 Work around bugs in MSVC "14" CTP 3's conversion logic by Reid Kleckner · 11 years ago
  13. fe0a2e6 R600/SI: Match read2/write2 stride 64 versions by Matt Arsenault · 11 years ago
  14. 4103328 R600/SI: Add load / store machine optimizer pass. by Matt Arsenault · 11 years ago