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gerrit-public.fairphone.software / toolchain / llvm-project / bf60f68c2c6dcbf0983b0b51ca688e11a5f9ecda / llvm / utils / TableGen / X86RecognizableInstr.cpp
  1. d968f6f [tablegen] Avoid creating temporary strings by Alexander Shaposhnikov · 8 years ago
  2. 2344b76 fix trivial typos in comments; NFC by Hiroshi Inoue · 8 years ago
  3. 3c18f19 [X86] Moving X86Local namespace from .cpp to .h file to use it in memory folding TableGen backend. by Ayman Musa · 8 years ago
  4. 684372d Fixed assert message to correctly refer to MRMSrcReg4VOp3Frm/MRMSrcMeg4VOp3Frm. by Simon Pilgrim · 9 years ago
  5. 51ffeab [X86][AVX] Extend hasVEX_WPrefix bit to accept WIG value (W Ignore) + update all AVX instructions with the new value. by Ayman Musa · 9 years ago
  6. fba613e [X86] Merge the disassemblers handling of the different TYPE_RELs by getting the size information from the ENCODING field. NFCI by Craig Topper · 9 years ago
  7. ad944a1 [X86] Reduce the number of operand 'types' the disassembler needs to deal with. NFCI by Craig Topper · 9 years ago
  8. 33ac064 [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a different encoding than regular addressing modes. by Craig Topper · 9 years ago
  9. 7dfd583 [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQD by Craig Topper · 9 years ago
  10. 5f8419d [X86] Create a new instruction format to handle 4VOp3 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. by Craig Topper · 9 years ago
  11. 9b20fec [X86] Create a new instruction format to handle MemOp4 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. by Craig Topper · 9 years ago
  12. 61b62e5 [X86] Space out the encodings of X86 instruction formats. I plan to add some new encodings in future commits and this will reduce the size of those commits. NFC by Craig Topper · 9 years ago
  13. 1867c6a [X86] Merge small helper function into the switch that calls it since they both operate on the same variable. NFC by Craig Topper · 9 years ago
  14. 313226f [X86] Explicitly list all X86 instruction forms in switch statement so its easier to detect when one is missing. NFC by Craig Topper · 9 years ago
  15. 45ef10f AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling. by Igor Breger · 10 years ago
  16. f5ef3f9 [X86] Remove some unused encoding checks from the disassembler table building. by Craig Topper · 10 years ago
  17. 802e2e7 [TableGen,X86] Add NDEBUG check to a variable initialization that's only used by asserts. NFC by Craig Topper · 10 years ago
  18. 8a01c41 [TableGen,X86] Remove extra optional operand from RawFrm. RawFrm with 2 immediates is handled by RawFrmImm8/RawFrmImm16. by Craig Topper · 10 years ago
  19. 6615654 [TableGen] Fix inconsistent spacing. NFC by Craig Topper · 10 years ago
  20. 983be94 [TableGen] Stop passing by reference an integer that doesn't get modified. NFC by Craig Topper · 10 years ago
  21. b89d189 [TableGen] Remove unused member variable. NFC by Craig Topper · 10 years ago
  22. 9a5a83a [X86][PKU] Add {RD,WR}PKRU encoding by Asaf Badouh · 10 years ago
  23. 7993e18 [X86] Part 2 to fix x86-64 fp128 calling convention. by Chih-Hung Hsieh · 10 years ago
  24. 6a1a357 AVX-512: Added all SKX forms of GATHER instructions. by Elena Demikhovsky · 10 years ago
  25. 6b62b65 X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. by Elena Demikhovsky · 10 years ago
  26. 0e6d6d5 AVX-512: Added VPMOVx2M instructions for SKX, fixed encoding of VPMOVM2x. by Elena Demikhovsky · 11 years ago
  27. a3776de [X86] Add the remaining 11 possible exact ModRM formats. This makes their encodings linear which can then be used to simplify some other code. by Craig Topper · 11 years ago
  28. 916708f [X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions. by Craig Topper · 11 years ago
  29. 7d3c6d3 [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions. by Craig Topper · 11 years ago
  30. 53a8467 [X86] Replace i32i8imm on SSE/AVX instructions with i32u8imm which will make the assembler bounds check them. It will also make them print as unsigned. by Craig Topper · 11 years ago
  31. 620b50c [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm. by Craig Topper · 11 years ago
  32. 8c0809c Replace size method call of containers to empty method where appropriate by Alexander Kornienko · 11 years ago
  33. 7c10252 [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized. by Craig Topper · 11 years ago
  34. 23fa478 [X86] Remove some unused TYPE enums from the disassembler. by Craig Topper · 11 years ago
  35. 6394454 [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16. by Craig Topper · 11 years ago
  36. 62c0525 [X86] Remove unused operand type from disassembler handling. NFC by Craig Topper · 11 years ago
  37. ae8e1b3 [X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. by Craig Topper · 11 years ago
  38. 055845f [X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates. by Craig Topper · 11 years ago
  39. 99bcab7 [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit modes with all 4 combinations of OpSize and AdSize prefixes being present or not. by Craig Topper · 11 years ago
  40. b86338f [X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags. by Craig Topper · 11 years ago
  41. 5068d0f [AVX512] Support mask register in MRMDestReg format by Adam Nemet · 11 years ago
  42. fd6a73d [X86 disasm tblegen backend] Clean up numPhysicalOperands asserts by Adam Nemet · 11 years ago
  43. 373b2b1 [x86] Fix a pretty horrible bug and inconsistency in the x86 asm by Chandler Carruth · 11 years ago
  44. 2ea081d [SKX] avx512_icmp_packed multiclass extension by Robert Khasanov · 11 years ago
  45. 0d928a1 Add support for the X86 secure guard extensions instructions in assembler (SGX). by Kevin Enderby · 11 years ago
  46. 595683d [SKX] Enabling mask logic instructions: encoding, lowering by Robert Khasanov · 11 years ago
  47. 74acbb7 [SKX] Enabling mask instructions: encoding, lowering by Robert Khasanov · 11 years ago
  48. bfa0131 [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features. by Robert Khasanov · 11 years ago
  49. 5933c2f [X86] AVX512: Add disassembler support for compressed displacement by Adam Nemet · 11 years ago
  50. 2406477 [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. by Craig Topper · 12 years ago
  51. e413b62 [x86] Simplify disassembler code slightly. by Craig Topper · 12 years ago
  52. e2347df [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. by Craig Topper · 12 years ago
  53. 56f0ed81 Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. by Craig Topper · 12 years ago
  54. 2fb696b Put some of the X86 formats in a more logical order. by Craig Topper · 12 years ago
  55. 0d1fd55 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. by Craig Topper · 12 years ago
  56. 5ccb617 Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. by Craig Topper · 12 years ago
  57. 69e245c Remove filtering concept from X86 disassembler table generation. It's no longer necessary. by Craig Topper · 12 years ago
  58. 5b3a6bd Remove special case filtering for instructions with lock prefix as they are all marked with isCodeGenOnly already. by Craig Topper · 12 years ago
  59. ea91f02 Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear from the disassembler table build without custom filtering code. by Craig Topper · 12 years ago
  60. a0869dc Recommit r201059 and r201060 with hopefully a fix for its original failure. by Craig Topper · 12 years ago
  61. ebdae7c Revert r201059 and r201060. by Bob Wilson · 12 years ago
  62. 0a43c2c Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. by Craig Topper · 12 years ago
  63. 0d88de8 Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. by Craig Topper · 12 years ago
  64. fa6298a Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. by Craig Topper · 12 years ago
  65. 8e92e85 Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix. by Craig Topper · 12 years ago
  66. d402df3 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. by Craig Topper · 12 years ago
  67. 10243c8 Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. by Craig Topper · 12 years ago
  68. ec68866 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch. by Craig Topper · 12 years ago
  69. 9bbf7ca ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385) by David Woodhouse · 12 years ago
  70. b33c2ef [x86] Allow address-size overrides for STOS[BWLQ] (PR9385) by David Woodhouse · 12 years ago
  71. 2ef8d9c [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) by David Woodhouse · 12 years ago
  72. caaa285 [x86] Fix disassembly of MOV16ao16 et al. by David Woodhouse · 12 years ago
  73. 35da3d1 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. by Craig Topper · 12 years ago
  74. b7c7f38 Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. by Craig Topper · 12 years ago
  75. ad60708 Remove stray comma in enum to satisfy -Wpedantic. by Craig Topper · 12 years ago
  76. ae11aed Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. by Craig Topper · 12 years ago
  77. 32da3c8 [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand by David Woodhouse · 12 years ago
  78. 2ea87da The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used. by Craig Topper · 12 years ago
  79. d9e1669 Use patterns to remove some duplicate instructions. by Craig Topper · 12 years ago
  80. 34db652 Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. by Craig Topper · 12 years ago
  81. c010797 Remove no longer needed x86 disassembler hack. by Craig Topper · 12 years ago
  82. 0550ce7 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. by Craig Topper · 12 years ago
  83. 5165cf7 Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. by Craig Topper · 12 years ago
  84. 3484fc2 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. by Craig Topper · 12 years ago
  85. 5999d47 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. by Craig Topper · 12 years ago
  86. bc281ad8 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. by Craig Topper · 12 years ago
  87. 1da8582 Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. by Craig Topper · 12 years ago
  88. 66c20f3 Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. by Craig Topper · 12 years ago
  89. fae226c Remove unused HasFROperands field from disassembler. by Craig Topper · 12 years ago
  90. eabdbcb Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. by Craig Topper · 12 years ago
  91. a941d2b Remove unnecessary stirng comparison from disassembler. by Craig Topper · 12 years ago
  92. 9dd48c8 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. by Craig Topper · 12 years ago
  93. 83b7e24 Remove unused function argument. by Craig Topper · 12 years ago
  94. 3321c99 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. by Craig Topper · 12 years ago
  95. 9155118 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. by Craig Topper · 12 years ago
  96. de3f751 AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp by Elena Demikhovsky · 12 years ago
  97. 623b0d6 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. by Craig Topper · 12 years ago
  98. e98c8cb Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. by Craig Topper · 12 years ago
  99. 0e21bca Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. by Craig Topper · 12 years ago
  100. 6d776e2 Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change. by Craig Topper · 12 years ago