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gerrit-public.fairphone.software / toolchain / llvm-project / c1be9c16bcb43f4e5fb7ac3efe9dbcc39074aad6 / llvm / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. c1be9c1 [ARM] NEON instructions were erroneously decoded from certain invalid encodings by Artyom Skrobov · 12 years ago
  2. 08a8660 ARM: provide diagnostics on more writeback LDM/STM instructions by Tim Northover · 12 years ago
  3. 510de64 [ARM] Remove an unused function from the disassembler. by Joey Gouly · 12 years ago
  4. 3308909 [ARMv8] Add support for the v8 cryptography extensions. by Amara Emerson · 12 years ago
  5. c34bf73 This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci, by Mihai Popa · 12 years ago
  6. df68600 [ARMv8] Add support for the NEON instructions vmaxnm/vminnm. by Joey Gouly · 12 years ago
  7. 18ce7e4 Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury. by Joey Gouly · 12 years ago
  8. cc4ff9e Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions. by Joey Gouly · 12 years ago
  9. 8449c0d ARM: check predicate bits for thumb instructions by Amaury de la Vieuville · 12 years ago
  10. 8175bda ARM: rGPR is meant to be unpredictable, not undefined by Amaury de la Vieuville · 12 years ago
  11. 2f0ac8d ARM: fix IT decoding by Amaury de la Vieuville · 12 years ago
  12. 4b6c076 ARM: enable decoding of pc-relative PLD/PLI by Amaury de la Vieuville · 12 years ago
  13. 4d3e3f2 ARM: fix thumb literal loads decoding by Amaury de la Vieuville · 12 years ago
  14. e2bb1d1 ARM: thumb stores cannot use PC as dest register by Amaury de la Vieuville · 12 years ago
  15. bd2b610 ARM: fix B decoding by Amaury de la Vieuville · 12 years ago
  16. 064546c ARM: Enforce decoding rules for VLDn instructions by Amaury de la Vieuville · 12 years ago
  17. 53ff029 ARM: Fix STREX/LDREX reecoding by Amaury de la Vieuville · 12 years ago
  18. 43cb13a ARM: ISB cannot be passed the same options as DMB by Amaury de la Vieuville · 12 years ago
  19. f4ec0c85 ARM: fix VMOVvnf32 decoding when ambiguous with VCVT by Amaury de la Vieuville · 12 years ago
  20. 68bcd02 ARM: enforce SRS decoding constraints by Amaury de la Vieuville · 12 years ago
  21. 631df63 ARM: fix CPS decoding when ambiguous with QADD by Amaury de la Vieuville · 12 years ago
  22. ea7bb57 ARM: fix VCVT decoding by Amaury de la Vieuville · 12 years ago
  23. 4173e29 ARM: add fstmx and fldmx instructions for assembly by Tim Northover · 12 years ago
  24. df1ecbd7 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. by Michael J. Spencer · 12 years ago
  25. 534d3a4 Remove the Copied parameter from MemoryObject::readBytes. by Benjamin Kramer · 12 years ago
  26. ad1084d Add MCSymbolizer for symbolic/annotated disassembly. by Ahmed Bougacha · 12 years ago
  27. f41e3f5 VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). by Mihai Popa · 12 years ago
  28. dcf0922 Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). by Mihai Popa · 12 years ago
  29. 8bad66e Replace some bit operations with simpler ones. No functionality change. by Benjamin Kramer · 12 years ago
  30. dc1764c5 The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. by Mihai Popa · 12 years ago
  31. a83d5e9 ARM: Fix encoding of hint instruction for Thumb. by Quentin Colombet · 12 years ago
  32. 27ff504 ARM: Permit "sp" in ARM variant of STREXD instructions by Tim Northover · 12 years ago
  33. a155ab2 ARM: permit "sp" in ARM variants of MOVW/MOVT instructions by Tim Northover · 12 years ago
  34. 6f03f62 Fix treatment of ARM unallocated hint instructions. by Quentin Colombet · 12 years ago
  35. 772cf46 Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set. by Gordon Keiser · 13 years ago
  36. f686be4 Patch by Gordon Keiser! by Joe Abbey · 13 years ago
  37. e3d3230 Remove edis - the enhanced disassembler. Fixes PR14654. by Roman Divacky · 13 years ago
  38. ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  39. 136d674 Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst by Kevin Enderby · 13 years ago
  40. 6fd9624 Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target by Kevin Enderby · 13 years ago
  41. b23926d Fix a bug where a 32-bit address with the high bit does not get symbolicated by Kevin Enderby · 13 years ago
  42. 0c97e76 Fix the handling of edge cases in ARM shifted operands. by Tim Northover · 13 years ago
  43. 00e071a Diagnose invalid alignments on duplicating VLDn instructions. by Tim Northover · 13 years ago
  44. fb3cdd8 Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions. by Tim Northover · 13 years ago
  45. 228e6d4 Fix integer undefined behavior due to signed left shift overflow in LLVM. by Richard Smith · 13 years ago
  46. f6add7e Remove unnecessary include of ARMGenInstrInfo.inc. by Craig Topper · 13 years ago
  47. ecaef49 Switch the fixed-length disassembler to be table-driven. by Jim Grosbach · 13 years ago
  48. 6a43bf7 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. by Jiangning Liu · 13 years ago
  49. 288e1af Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. by Jiangning Liu · 13 years ago
  50. 35521e2 Fix a typo (the the => the) by Sylvestre Ledru · 13 years ago
  51. 1dc44dc Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! by Richard Barton · 13 years ago
  52. aeed158 Revert r159938 (and r159945) to appease the buildbots. by Chad Rosier · 13 years ago
  53. 5beef2d Oops - correct broken disassembly for VMOV by Richard Barton · 13 years ago
  54. c9e1c94f Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) by Richard Barton · 13 years ago
  55. f1ef87d Correct decoder for T1 conditional B encoding by Richard Barton · 13 years ago
  56. 70c1aa0 ARMDisassembler.cpp: Fix utf8 char in comments. by NAKAMURA Takumi · 13 years ago
  57. cabbae6 Tweak to the fix in r156212, as with the change in removing the shift the by Kevin Enderby · 13 years ago
  58. 8ce1ada Fix a bug in the ARM disassembler for wide branch conditional instructions by Kevin Enderby · 13 years ago
  59. 9142230 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits by Kevin Enderby · 13 years ago
  60. 9560af8 Fixed disassembler for vstm/vldm ARM VFP instructions. by Silviu Baranga · 13 years ago
  61. 9d8f6f3 ARM: Tweak tADDrSP definition for consistent operand order. by Jim Grosbach · 13 years ago
  62. f435b09 Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. by Richard Barton · 13 years ago
  63. e960000 Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector by Richard Barton · 13 years ago
  64. ca45af9 Added support for disassembling unpredictable swp/swpb ARM instructions. by Silviu Baranga · 13 years ago
  65. 41f1fcd Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. by Silviu Baranga · 13 years ago
  66. 29ae538 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) by Kevin Enderby · 13 years ago
  67. 40d4e47 Fix a few more places in the ARM disassembler so that branches get by Kevin Enderby · 14 years ago
  68. 72f18bb Fixed a case of ARM disassembly getting an assert on a bad encoding by Kevin Enderby · 14 years ago
  69. d2980cd Fix ARM disassembly of VLD instructions with writebacks.  And add test a case by Kevin Enderby · 14 years ago
  70. 7a3973d ARMDisassembler: drop bogus dependency on ARMCodeGen by Dylan Noblesmith · 14 years ago
  71. f6e7e12 Remove unnecessary llvm:: qualifications by Craig Topper · 14 years ago
  72. 4afd7d2 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. by Silviu Baranga · 14 years ago
  73. d213f21 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM by Silviu Baranga · 14 years ago
  74. 7e7d5ee Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test by Kevin Enderby · 14 years ago
  75. 32a4933 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. by Silviu Baranga · 14 years ago
  76. ca658c2 Use uint16_t to store registers and opcode in static tables in the target specific backends. by Craig Topper · 14 years ago
  77. eed9992 Tidy up. Remove dead code that slipped into previous commit. by Jim Grosbach · 14 years ago
  78. ed428bc ARM more NEON VLD/VST composite physical register refactoring. by Jim Grosbach · 14 years ago
  79. 13a292c ARM refactor more NEON VLD/VST instructions to use composite physregs by Jim Grosbach · 14 years ago
  80. 520eb3b Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. by Kevin Enderby · 14 years ago
  81. e5307f9 ARM Refactor VLD/VST spaced pair instructions. by Jim Grosbach · 14 years ago
  82. c988e0c ARM refactor away a bunch of VLD/VST pseudo instructions. by Jim Grosbach · 14 years ago
  83. 56b662c Make MemoryObject accessor members const again by Derek Schuff · 14 years ago
  84. 1489b52 Fix the symbolic operand added for the C disassmbler API for the ARM bl by Kevin Enderby · 14 years ago
  85. 6fbcd8d Updated the llvm-mc disassembler C API to support for the X86 target. by Kevin Enderby · 14 years ago
  86. b22310f Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. by Jia Liu · 14 years ago
  87. 428704e Make the EDis tables const. by Benjamin Kramer · 14 years ago
  88. e55c556 Convert assert(0) to llvm_unreachable by Craig Topper · 14 years ago
  89. 8b2dcad Enable streaming of bitcode by Derek Schuff · 14 years ago
  90. 46a9f01 More dead code removal (using -Wunreachable-code) by David Blaikie · 14 years ago
  91. 4a5c887 ARM NEON VTBL/VTBX assembly parsing and encoding. by Jim Grosbach · 14 years ago
  92. 88ac761 ARM NEON refactor VST2 w/ writeback instructions. by Jim Grosbach · 14 years ago
  93. 8d24618 ARM NEON VST2 assembly parsing and encoding. by Jim Grosbach · 14 years ago
  94. d146a02 ARM assembly parsing and encoding for VLD2 with writeback. by Jim Grosbach · 14 years ago
  95. 23c30b9 Remove unused variable by Matt Beaumont-Gay · 14 years ago
  96. a68c9a8 ARM parsing for VLD1 all lanes, with writeback. by Jim Grosbach · 14 years ago
  97. 5ee209c ARM assembly parsing and encoding for four-register VST1. by Jim Grosbach · 14 years ago
  98. 98d032f ARM assembly parsing and encoding for three-register VST1. by Jim Grosbach · 14 years ago
  99. 05060f0 Fix a misplaced paren bug. by Owen Anderson · 14 years ago
  100. 0ac9058 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. by Owen Anderson · 14 years ago