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gerrit-public.fairphone.software / toolchain / llvm-project / d3e65e702f45ea3476f3bda2b8f69a3e3729e9e2 / llvm / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. 5230041 Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. by Owen Anderson · 14 years ago
  2. 924bcfc Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. by Owen Anderson · 14 years ago
  3. 9b7bd15 Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. by Owen Anderson · 14 years ago
  4. eb1367b Reject invalid imod values in t2CPS instructions. by Owen Anderson · 14 years ago
  5. df698b0 Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. by Owen Anderson · 14 years ago
  6. 721c370 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. by Owen Anderson · 14 years ago
  7. ac92e77 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. by Owen Anderson · 14 years ago
  8. b498132 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. by Owen Anderson · 14 years ago
  9. 96b7ad2 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. by Owen Anderson · 14 years ago
  10. 192a760 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. by Owen Anderson · 14 years ago
  11. 5d2db89 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. by Owen Anderson · 14 years ago
  12. 67d6f11 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. by Owen Anderson · 14 years ago
  13. d14b70d Tidy up. 80 columns. by Jim Grosbach · 14 years ago
  14. 46dd413 ARM clean up the imm_sr operand class representation. by Jim Grosbach · 14 years ago
  15. 187e1e4 Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array. by Owen Anderson · 14 years ago
  16. a4043c4 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. by Owen Anderson · 14 years ago
  17. 91a8f9b Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. by Owen Anderson · 14 years ago
  18. a6201f0 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. by Owen Anderson · 14 years ago
  19. 1d5d2ca Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. by Owen Anderson · 14 years ago
  20. b9d82f4 Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. by Owen Anderson · 14 years ago
  21. 2d1d7a1 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. by Owen Anderson · 14 years ago
  22. 60138ea Fix decoding of ARM-mode STRH. by Owen Anderson · 14 years ago
  23. 3987a61 Fix decoding of pre-indexed stores. by Owen Anderson · 14 years ago
  24. c5798a3a5 Separate decoding for STREXD and LDREXD to make each work better. by Owen Anderson · 14 years ago
  25. e259421 ARM STRT assembly parsing and encoding. by Jim Grosbach · 14 years ago
  26. ff0b442 Add another accidentally omitted predicate operand. by Owen Anderson · 14 years ago
  27. 2f7aa73 Add missing predicate operand on SMLA and friends. by Owen Anderson · 14 years ago
  28. b685c9f Fix decoding support for STREXD and LDREXD. by Owen Anderson · 14 years ago
  29. 3a850f2 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. by Owen Anderson · 14 years ago
  30. 6066340 Continue to tighten decoding by performing more operand validation. by Owen Anderson · 14 years ago
  31. 2a50260 ARM STRBT assembly parsing and encoding. by Jim Grosbach · 14 years ago
  32. 3477f2c Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. by Owen Anderson · 14 years ago
  33. 0e15b48 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. by Owen Anderson · 14 years ago
  34. ed25385 Improve error checking in the new ARM disassembler. Patch by James Molloy. by Owen Anderson · 14 years ago
  35. d5d6359 ARM LDRT assembly parsing and encoding. by Jim Grosbach · 14 years ago
  36. c86a5bd Add initial support for decoding NEON instructions in Thumb2 mode. by Owen Anderson · 14 years ago
  37. 5d69f63 Cleanups based on Nick Lewycky's feedback. by Owen Anderson · 14 years ago
  38. 8059f0c Push GPRnopc through a large number of instruction definitions to tighten operand decoding. by Owen Anderson · 14 years ago
  39. 92b942b Tighten operand checking of register-shifted-register operands. by Owen Anderson · 14 years ago
  40. e008931 Tighten operand checking on memory barrier instructions. by Owen Anderson · 14 years ago
  41. 3d2e0e9d Tighten operand checking on CPS instructions. by Owen Anderson · 14 years ago
  42. 042619f Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. by Owen Anderson · 14 years ago
  43. 406dc17 ARM Disassembler: sign extend branch immediates. by Benjamin Kramer · 14 years ago
  44. d151b09 Silence an false-positive warning. by Owen Anderson · 14 years ago
  45. 7a2401d Tighten Thumb1 branch predicate decoding. by Owen Anderson · 14 years ago
  46. e0152a7 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. by Owen Anderson · 14 years ago
  47. d359571 ARM refactoring assembly parsing of memory address operands. by Jim Grosbach · 14 years ago
  48. dc62e59 Fix typo in the comment. by Johnny Chen · 15 years ago
  49. 9377a52 Adding support for printing operands symbolically to llvm's public 'C' by Kevin Enderby · 15 years ago
  50. 923f3da Fixed the t2PLD and friends disassembly and add two test cases. by Johnny Chen · 15 years ago
  51. 02e59ad Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer! by Johnny Chen · 15 years ago
  52. dd9eb21 Plug a leak in the arm disassembler and put the tests back. by Benjamin Kramer · 15 years ago
  53. 7ca3ddc For ARM Disassembler, start a newline to dump the opcode and friends for an instruction. by Johnny Chen · 15 years ago
  54. 9363d41 LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. by Johnny Chen · 15 years ago
  55. 4ebf471 Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. by Owen Anderson · 15 years ago
  56. 99ea8a3 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. by Owen Anderson · 15 years ago
  57. 943fb60 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. by Owen Anderson · 15 years ago
  58. 8335e8f Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the by Owen Anderson · 15 years ago
  59. 6f36042 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. by Evan Cheng · 15 years ago
  60. d100ed8 Detabify and clean up 80 column violations. by Jim Grosbach · 15 years ago
  61. 3da4255 Add ARM Disassembler to the CMake build. by Oscar Fuentes · 15 years ago
  62. 7a23aa0 ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255. by NAKAMURA Takumi · 15 years ago
  63. 74491bb The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td by Johnny Chen · 15 years ago
  64. add51311 Move the ARM SSAT and USAT optional shift amount operand out of the by Bob Wilson · 15 years ago
  65. 7be315c For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', by Johnny Chen · 16 years ago
  66. f3dd8b9 More IT instruction error-handling improvements from fuzzing. by Johnny Chen · 16 years ago
  67. e62b680 Better error handling of invalid IT mask '0000', instead of just asserting. by Johnny Chen · 16 years ago
  68. ed9bee1 Fixed logic error. Should check Builder for validity before calling SetSession by Johnny Chen · 16 years ago
  69. 7637827 Fixed another assert exposed by fuzzing. The utility function getRegisterEnum() by Johnny Chen · 16 years ago
  70. 814e69b Fixed a nasty layering violation in the edis source by Sean Callanan · 16 years ago
  71. dacfd2c Get rid of traling whitespaces. No functionality change. by Johnny Chen · 16 years ago
  72. dba13e7 The disassembler impl. of MCDisassembler::getInstruction() was using the pattern by Johnny Chen · 16 years ago
  73. 7b999ea Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen by Johnny Chen · 16 years ago
  74. 1b4e8cc --- Reverse-merging r98637 into '.': by Bob Wilson · 16 years ago
  75. 3d9327b Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend by Johnny Chen · 16 years ago