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gerrit-public.fairphone.software / toolchain / llvm-project / d4c4671aa70a3e18f97cd0fd00352a73b18b1d40 / llvm / lib / Target / AMDGPU / SIISelLowering.cpp
  1. d4c4671 [Alignment][NFC] Remove LogAlignment functions by Guillaume Chatelet · 6 years ago
  2. 60169ed AMDGPU/GlobalISel: Set type on vgpr live in special arguments by Matt Arsenault · 6 years ago
  3. c0ceca5 AMDGPU/GlobalISel: First pass at attempting to legalize load/stores by Matt Arsenault · 6 years ago
  4. 3729b17 [Alignment][NFC] Use llvm::Align for TargetLowering::getPrefLoopAlignment by Guillaume Chatelet · 6 years ago
  5. acc9571 AMDGPU: Remove pointless wrapper nodes for init.exec intrinsics by Matt Arsenault · 6 years ago
  6. aff45e4 [LLVM][Alignment] Make functions using log of alignment explicit by Guillaume Chatelet · 6 years ago
  7. f581d57 AMDGPU: Add intrinsics for address space identification by Matt Arsenault · 6 years ago
  8. 6e18266 Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0" by Jay Foad · 6 years ago
  9. 0c096da AMDGPU: Fix crash from inconsistent register types for v3i16/v3f16 by Matt Arsenault · 6 years ago
  10. 0c47611 Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM by Daniel Sanders · 6 years ago
  11. 1f2b727 MVT: Add v3i16/v3f16 vectors by Matt Arsenault · 6 years ago
  12. a05c384 Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10 by Austin Kerbow · 6 years ago
  13. 37aa8ad Revert "[AMDGPU] Use S_DENORM_MODE for gfx10" by Dmitri Gribenko · 6 years ago
  14. 8d229dbb [AMDGPU] Use S_DENORM_MODE for gfx10 by Austin Kerbow · 6 years ago
  15. 3922392 AMDGPU: Correct behavior of f16 buffer loads by Matt Arsenault · 6 years ago
  16. 0e0a1c8 AMDGPU: Correct behavior of f16/i16 non-format store intrinsics by Matt Arsenault · 6 years ago
  17. c97a3d1 [LLVM][Alignment] Introduce Alignment Type by Guillaume Chatelet · 6 years ago
  18. e204786 AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec} by Nicolai Haehnle · 6 years ago
  19. 2bea69b Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC by Daniel Sanders · 6 years ago
  20. bb582eb AMDGPU: Remove v0 workaround for DS_GWS_* instructions by Matt Arsenault · 6 years ago
  21. aff2995 AMDGPU: Use tablegen pattern for sendmsg intrinsics by Matt Arsenault · 6 years ago
  22. 450afce [AMDGPU] Reserve all AGPRs on targets which do not have them by Stanislav Mekhanoshin · 6 years ago
  23. 20235ef [AMDGPU] Enable v4f16 and above for v_pk_fma instructions by David Stuttard · 6 years ago
  24. 0b28357 [AMDGPU] Move WQM/WWM intrinsic instruction selection to AMDGPUISelDAGToDAG by Carl Ritson · 6 years ago
  25. a85af76 AMDGPU: Don't assert on v4f16 arguments to shader calling conventions by Matt Arsenault · 6 years ago
  26. 85f3890 AMDGPU: Force s_waitcnt after GWS instructions by Matt Arsenault · 6 years ago
  27. fecf43e AMDGPU/GlobalISel: Rewrite lowerFormalArguments by Matt Arsenault · 6 years ago
  28. 1022c0d AMDGPU: Decompose all values to 32-bit pieces for calling conventions by Matt Arsenault · 6 years ago
  29. 6e0fa29 [AMDGPU] Change register type for v32 vectors by Stanislav Mekhanoshin · 6 years ago
  30. 49169a9 AMDGPU: Add 24-bit mul intrinsics by Matt Arsenault · 6 years ago
  31. 1dfae6f [AMDGPU] use v32f32 for 3 mfma intrinsics by Stanislav Mekhanoshin · 6 years ago
  32. 51a05d7 AMDGPU: Drop remnants of byval support for shaders by Matt Arsenault · 6 years ago
  33. e67cc38 [AMDGPU] gfx908 mfma support by Stanislav Mekhanoshin · 6 years ago
  34. e93279f [AMDGPU] gfx908 atomic fadd and atomic pk_fadd by Stanislav Mekhanoshin · 6 years ago
  35. 50d7f464 [AMDGPU] gfx908 mAI instructions, MC part by Stanislav Mekhanoshin · 6 years ago
  36. b2d24bd [AMDGPU] Created a sub-register class for the return address operand in the return instruction. by Christudasan Devadasan · 6 years ago
  37. 71dfb7e AMDGPU: Make s34 the FP register by Matt Arsenault · 6 years ago
  38. 5816889 [AMDGPU] Custom lower INSERT_SUBVECTOR v3, v4, v5, v8 by Tim Renouf · 6 years ago
  39. 5fe851b AMDGPU: Custom lower vector_shuffle for v4i16/v4f16 by Matt Arsenault · 6 years ago
  40. 10c911d AMDGPU/GFX10: implement ds_ordered_count changes by Nicolai Haehnle · 6 years ago
  41. 4dc3b2b AMDGPU: Support GDS atomics by Nicolai Haehnle · 6 years ago
  42. 07fd88d [AMDGPU] Packed thread ids in function call ABI by Stanislav Mekhanoshin · 6 years ago
  43. 2710171 AMDGPU: Write LDS objects out as global symbols in code generation by Nicolai Haehnle · 6 years ago
  44. 22e3dc6 AMDGPU: Fix not using s33 for scratch wave offset in kernels by Matt Arsenault · 6 years ago
  45. d88db6d AMDGPU: Always use s33 for global scratch wave offset by Matt Arsenault · 6 years ago
  46. 740322f AMDGPU: Add intrinsics for DS GWS semaphore instructions by Matt Arsenault · 6 years ago
  47. 8ad1dec AMDGPU: Insert mem_viol check loop around GWS pre-GFX9 by Matt Arsenault · 6 years ago
  48. e4c2e9b AMDGPU: Consolidate some getGeneration checks by Matt Arsenault · 6 years ago
  49. 4d55d02 Reapply "AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics" by Matt Arsenault · 6 years ago
  50. 128ce93 Revert rL363678 : AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics by Simon Pilgrim · 6 years ago
  51. 8d35dcd AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics by Matt Arsenault · 6 years ago
  52. 6d71be4 AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0 by Nicolai Haehnle · 6 years ago
  53. 490e83c AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsic by Nicolai Haehnle · 6 years ago
  54. 5250021 [AMDGPU] gfx10 conditional registers handling by Stanislav Mekhanoshin · 6 years ago
  55. 68a2fef [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 by Stanislav Mekhanoshin · 6 years ago
  56. 5f581c9 [AMDGPU] gfx1010 premlane instructions by Stanislav Mekhanoshin · 6 years ago
  57. 4e0648a [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR42123) by Simon Pilgrim · 6 years ago
  58. 266f439 [TargetLowering] Add allowsMemoryAccess(MachineMemOperand) helper wrapper. NFCI. by Simon Pilgrim · 6 years ago
  59. 9b11e93 [AMDGPU] Optimize image_[load|store]_mip by Piotr Sobczak · 6 years ago
  60. 37bd9bd [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd by Alexander Timofeev · 6 years ago
  61. 34c8b83 AMDGPU: Don't fix emergency stack slot at offset 0 by Matt Arsenault · 6 years ago
  62. b812b7a AMDGPU: Invert frame index offset interpretation by Matt Arsenault · 6 years ago
  63. 8dbeb92 TTI: Improve default costs for addrspacecast by Matt Arsenault · 7 years ago
  64. d5443f8 AMDGPU: Return address lowering by Aakanksha Patil · 7 years ago
  65. 5fc1dfa [AMDGPU] Correct the handling of inlineasm output registers. by Michael Liao · 7 years ago
  66. ba447ba [AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence. by Alexander Timofeev · 7 years ago
  67. 3b93737 Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence." by Peter Collingbourne · 7 years ago
  68. dffedea [AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence. by Alexander Timofeev · 7 years ago
  69. 5c714cb AMDGPU: Correct maximum possible private allocation size by Matt Arsenault · 7 years ago
  70. 99e6f4d AMDGPU: Introduce TokenFactor for ABI register copies in call sequence by Matt Arsenault · 7 years ago
  71. 28a1936 [AMDGPU] gfx1010: use fmac instructions by Stanislav Mekhanoshin · 7 years ago
  72. 93f15c9 [AMDGPU] gfx1010 loop alignment by Stanislav Mekhanoshin · 7 years ago
  73. 284472b [SelectionDAG] remove constant folding limitations based on FP exceptions by Sanjay Patel · 7 years ago
  74. 64399da [AMDGPU] gfx1010 lost VOP2 forms of some add/sub by Stanislav Mekhanoshin · 7 years ago
  75. 692560d [AMDGPU] gfx1010 MIMG implementation by Stanislav Mekhanoshin · 7 years ago
  76. a224f68 [AMDGPU] gfx1010 DS implementation by Stanislav Mekhanoshin · 7 years ago
  77. 180f1ae [TargetLowering] Change getOptimalMemOpType to take a function attribute list by Sjoerd Meijer · 7 years ago
  78. 055e4dc AMDGPU: Remove dx10-clamp from subtarget features by Matt Arsenault · 7 years ago
  79. 6f0191a [AMDGPU] Use three- and five-dword result type in image ops by Tim Renouf · 7 years ago
  80. 677387d [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics by Tim Renouf · 7 years ago
  81. 033f99a [AMDGPU] Added v5i32 and v5f32 register classes by Tim Renouf · 7 years ago
  82. 361b5b2 [AMDGPU] Support for v3i32/v3f32 by Tim Renouf · 7 years ago
  83. fc2a747 [AMDGPU] Allow MIMG with no uses in adjustWritemask in isel by David Stuttard · 7 years ago
  84. 00e063a [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics by Ryan Taylor · 7 years ago
  85. e85f6bd [AMDGPU] Ban i8 min3 promotion. by Neil Henning · 7 years ago
  86. 2e94f6e [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers by Tim Renouf · 7 years ago
  87. 523dab0 [AMDGPU] Add an experimental buffer fat pointer address space. by Neil Henning · 7 years ago
  88. bc6d07c MIR: Allow targets to serialize MachineFunctionInfo by Matt Arsenault · 7 years ago
  89. caf1316 IR: Add immarg attribute by Matt Arsenault · 7 years ago
  90. 26e76ef DAG: Don't try to cluster loads with tied inputs by Matt Arsenault · 7 years ago
  91. ef92035 [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instructions s_set_gpr_idx_on and s_set_gpr_idx_mode by Dmitry Preobrazhensky · 7 years ago
  92. da1628e [AMDGPU] Fixed hang during DAG combine by Stanislav Mekhanoshin · 7 years ago
  93. aa6fb4c AMDGPU: Remove debugger related subtarget features by Matt Arsenault · 7 years ago
  94. 42e229e [AMDGPU] fix commuted case of sub combine by Stanislav Mekhanoshin · 7 years ago
  95. 871821f [AMDGPU] Ressociate 'add (add x, y), z' to use SALU by Stanislav Mekhanoshin · 7 years ago
  96. 0e858b0 [AMDGPU] Split dot-insts feature by Stanislav Mekhanoshin · 7 years ago
  97. 784929d Implementation of asm-goto support in LLVM by Craig Topper · 7 years ago
  98. a8b4339 AMDGPU/GlobalISel: Legalize addrspacecast by Matt Arsenault · 7 years ago
  99. e2c5847 [AMDGPU] Consider XOR in waterfall loop as a terminator by Scott Linder · 7 years ago
  100. d19d197 [AMDGPU] Support emitting GOT relocations for function calls by Scott Linder · 7 years ago