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gerrit-public.fairphone.software / toolchain / llvm-project / d545ad130180ba15c894cd137a457fcd30c75c73 / llvm / lib / CodeGen / LiveIntervalAnalysis.cpp
  1. fccbd0a Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information. by Evan Cheng · 16 years ago
  2. a894053 When computing live intervals for earlyclobber operands, by Dale Johannesen · 16 years ago
  3. 9367ec8 Fix -Asserts warning. by Daniel Dunbar · 16 years ago
  4. a38ff3e Another try at early partial coalescing. Identity phi source copies (their sources are defined by phi join def) are coalesced. And the phi join copy is backward copy propagated into the other copies. by Evan Cheng · 16 years ago
  5. 7f78959 Add early coalescing to liveintervals. This is work in progress and is known to miscompute some tests. Read it at your own rish, I have aged 10 year while writing this. by Evan Cheng · 16 years ago
  6. dad2da5 Moved some more index operations over to LiveIntervals. by Lang Hames · 16 years ago
  7. fe4d1e6 80 col violations. by Evan Cheng · 16 years ago
  8. 3fffe62 Replaces uses of unsigned for indexes in LiveInterval and VNInfo with by Lang Hames · 16 years ago
  9. 1362602 Change Pass::print to take a raw ostream instead of std::ostream, by Chris Lattner · 16 years ago
  10. a6f074f remove various std::ostream version of printing methods from by Chris Lattner · 16 years ago
  11. 1f28992 remove a dead class. by Chris Lattner · 16 years ago
  12. dfcc42f Convert DOUT to DEBUG(errs()...). by Bill Wendling · 16 years ago
  13. 3b90d97 Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. by Lang Hames · 16 years ago
  14. 3794292 Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs. by Evan Cheng · 16 years ago
  15. ec9bc28 by David Greene · 16 years ago
  16. 0402315 Use setPreservesAll and setPreservesCFG in CodeGen passes. by Dan Gohman · 16 years ago
  17. 0dd5e1e More migration to raw_ostream, the water has dried up around the iostream hole. by Daniel Dunbar · 16 years ago
  18. 8ef0735 Move to raw_ostream. by Daniel Dunbar · 16 years ago
  19. e88680e by David Greene · 16 years ago
  20. 1eede6c revert r76602, 76603, and r76615, pending design discussions. by Chris Lattner · 16 years ago
  21. ef1f36d by David Greene · 16 years ago
  22. f08b003 Simplify the coalescer (finally!) by making LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands. by Evan Cheng · 16 years ago
  23. 357645e Changed my mind. We now allow remat of instructions whose defs have subreg indices. by Evan Cheng · 16 years ago
  24. 8451744 Let callers decide the sub-register index on the def operand of rematerialized instructions. by Evan Cheng · 16 years ago
  25. fbcc663 llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. by Torok Edwin · 16 years ago
  26. 56d0659 assert(0) -> LLVM_UNREACHABLE. by Torok Edwin · 16 years ago
  27. ccb29cd Convert more assert(0)+abort() -> LLVM_UNREACHABLE, by Torok Edwin · 16 years ago
  28. 45210aa Avoid compiler warnings if assertions turned off. by Duncan Sands · 16 years ago
  29. dab7b06 Improved tracking of value number kills. VN kills are now represented by Lang Hames · 16 years ago
  30. 2a5efe1 Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def. by Evan Cheng · 16 years ago
  31. d379e89 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. by Evan Cheng · 16 years ago
  32. 0dc101b Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. by Evan Cheng · 16 years ago
  33. c91e8c7 When doing remat, don't consider uses of non-allocatable physregs. Patch by Chris Lattner · 16 years ago
  34. 6b2c960 More VNInfo tweaking, plus a little progress on intra-block splitting. by Lang Hames · 16 years ago
  35. 32270cc Improved PHI def marking, replaced some gotos with breaks. by Lang Hames · 16 years ago
  36. 16cab19 VNInfo cleanup. by Lang Hames · 16 years ago
  37. 085caf1 Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them. by Evan Cheng · 16 years ago
  38. fc968ef Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. by Lang Hames · 17 years ago
  39. 7d287cb LiveVariables::VarInfo contains an AliveBlocks BitVector, which has as many by Jeffrey Yasskin · 17 years ago
  40. 210fc62 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. by Evan Cheng · 17 years ago
  41. 093e4c5 Fix PR4076. Correctly create live interval of physical register with two-address update. by Evan Cheng · 17 years ago
  42. 0f85bd3 Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass. by Evan Cheng · 17 years ago
  43. 1a99a5f It has finally happened. Spiller is now using live interval info. by Evan Cheng · 17 years ago
  44. d67efaa Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g. by Evan Cheng · 17 years ago
  45. 1d50407 Don't abort on an aliasing physical register that does not have by Dan Gohman · 17 years ago
  46. 5185617 Fix pr3954. The register scavenger asserts for inline assembly with by Bob Wilson · 17 years ago
  47. ad3e549 Implement support for using modeling implicit-zero-extension on x86-64 by Dan Gohman · 17 years ago
  48. 76a561f Don't assign a new stack slot if the pre-alloc splitter already assigned one. by Owen Anderson · 17 years ago
  49. f858466 Fix PR3391 and PR3864. Reg allocator infinite looping. by Evan Cheng · 17 years ago
  50. 968c3b0 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. by Evan Cheng · 17 years ago
  51. 8d5baa0 Fix the Win32 VS2008 build: by Sebastian Redl · 17 years ago
  52. 1361cbb Added MachineInstr::isRegTiedToDefOperand to check for two-addressness. by Evan Cheng · 17 years ago
  53. f0bfc6a Fix how livein live intervals are handled. Previously it could end at MBB start. Sorry, no small test case possible. by Evan Cheng · 17 years ago
  54. b378363 Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register. by Evan Cheng · 17 years ago
  55. 76a2736 Exit with nice warnings when register allocator run out of registers. by Evan Cheng · 17 years ago
  56. c544cb0 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. by Evan Cheng · 17 years ago
  57. f6768bd The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: by Evan Cheng · 17 years ago
  58. 0869f78 Fix PR3149. If an early clobber def is a physical register and it is tied to an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this. by Evan Cheng · 17 years ago
  59. 9de2ac8 Clarify some comments. by Dan Gohman · 17 years ago
  60. 43c0891 Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing. by Evan Cheng · 17 years ago
  61. 994faaf Fix comment. by Evan Cheng · 17 years ago
  62. d24be45 Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant. by Dan Gohman · 17 years ago
  63. 69cc2cb Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. by Dan Gohman · 17 years ago
  64. 3336b1f LiveRanges are represented as half-open ranges. Fix the findLiveInMBBs code by Dan Gohman · 17 years ago
  65. cb181bb Silence unused variable warnings. by Devang Patel · 17 years ago
  66. 8fed4ce Use find_first/find_next to iterate through all the set bits in a by Dan Gohman · 17 years ago
  67. 5efcb61 Remove some debugging code made redundant by the change to do by Dan Gohman · 17 years ago
  68. 938e201 - Rewrite code that update register live interval that's split. by Evan Cheng · 17 years ago
  69. b00b267 by David Greene · 17 years ago
  70. 4bac4d0 Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now). by Evan Cheng · 17 years ago
  71. 2dadd3b By min, I mean max. by Evan Cheng · 17 years ago
  72. ac4e70d When creating intervals, leave min(1, numdefs) holes after each instruction. by Evan Cheng · 17 years ago
  73. 1d338fc Add an option to enable StrongPHIElimination, for ease of testing. by Owen Anderson · 17 years ago
  74. 0d1e9a8 Switch the MachineOperand accessors back to the short names like by Dan Gohman · 17 years ago
  75. f4a3640 Fix a simple error in renumbering kill markaers, that took an inordinant amount of time to track down. by Owen Anderson · 17 years ago
  76. 9156bd2 Re-apply 56835 along with header file changes. by Evan Cheng · 17 years ago
  77. 2b9adce Revert commit 56835 since it breaks the build. by Duncan Sands · 17 years ago
  78. 9469049 If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. by Evan Cheng · 17 years ago
  79. c36660d Next round of earlyclobber handling. Approach the by Dale Johannesen · 17 years ago
  80. df8f1cb Fetch the starting index of the block when assigning intervals. This gets live-in indices by Owen Anderson · 17 years ago
  81. e519bd4 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis by Dale Johannesen · 17 years ago
  82. f8610eb Add a bit to mark operands of asm's that conflict by Dale Johannesen · 17 years ago
  83. 82ab1e7 Live intervals for live-in registers should begin at the beginning of a basic block, not at the first by Owen Anderson · 17 years ago
  84. 38453ee Remove isImm(), isReg(), and friends, in favor of by Dan Gohman · 17 years ago
  85. 2a45877 Allow the fast-path spilling code to attempt folding, but still leaving out remat and splitting. by Owen Anderson · 17 years ago
  86. c75ae13 The fast-path still needs to set kill markers and spill/restore points as appropriate. by Owen Anderson · 17 years ago
  87. 442dc6f Add a flag to enable the fast spilling path. by Owen Anderson · 17 years ago
  88. a57c570 Fix a few more bugs: by Owen Anderson · 17 years ago
  89. 60f6b2c Fix several bugs in the new fast-path: by Owen Anderson · 17 years ago
  90. e996a12 Clients of addIntervalForSpills expect the added intervals to be returned sorted by starting index. by Owen Anderson · 17 years ago
  91. 75e27d2 Simplify the fast-patch interval spilling by using MachineRegisterInfo::reg_iterator. by Owen Anderson · 17 years ago
  92. cc9314b Resurrect some ancient code to add spill ranges without attempting folding, remat, or splitting. This code has been updated to current APIs by Owen Anderson · 17 years ago
  93. 706f6b7 Expunge the last uses of std::map from LiveIntervals. by Owen Anderson · 17 years ago
  94. 767b5cc Move r2iMap_ over to DenseMap from std::map. by Owen Anderson · 17 years ago
  95. 51f689a Make the allocation of LiveIntervals explicit, rather than holding them in the r2iMap_ by value. This will prevent references to them from being invalidated by Owen Anderson · 17 years ago
  96. d184929 Oops, didn't mean to commit this. by Owen Anderson · 17 years ago
  97. 03dddbb Only remap each VNInfo once when doing renumbering. by Owen Anderson · 17 years ago
  98. 7b5f535 Value numbers whose def index is a special sentinel value should not be remapped. by Owen Anderson · 17 years ago
  99. e9a0bae More fixes for corner cases when remapping live range indices. by Owen Anderson · 17 years ago
  100. 2532e75 Don't decrement the BB remap when we don't need to. by Owen Anderson · 17 years ago