- d6dada1 [mips] Removal of microMIPS64R6 by Aleksandar Beserminji · 8 years ago
- 169df4e [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version by Simon Dardis · 8 years ago
- 51a7ae2 [mips] Place certain 64 bit FPU instructions in their own decoder namespace by Simon Dardis · 8 years ago
- 72982e69 [mips] Fix calculation of a branch instruction offset to escape left shift of negative value by Simon Atanasyan · 8 years ago
- 55e4467 [mips] Implement the 'dext' aliases and it's disassembly alias. by Simon Dardis · 8 years ago
- 6f83ae3 [mips] Implement the 'dins' aliases. by Simon Dardis · 8 years ago
- 79220eae [Mips] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
- 6bda14b Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
- cac14b5 [Mips] Fix for decoding DINS instruction - disassembler by Strahinja Petrovic · 9 years ago
- a5f52dc [mips][mc] Fix a crash when disassembling odd sized sections by Simon Dardis · 9 years ago
- 926883e [Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 9 years ago
- dcd8433 Fix spelling mistakes in MIPS target comments. NFC. by Simon Pilgrim · 9 years ago
- b3fd189 [mips] Fix aui/daui/dahi/dati for MIPSR6 by Simon Dardis · 9 years ago
- f42454b Move the global variables representing each Target behind accessor function by Mehdi Amini · 9 years ago
- 1d56e88 [mips] Fix previous revert r281726. by Simon Dardis · 9 years ago
- e53cfa7 Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6" by Simon Dardis · 9 years ago
- cf06079 [mips] Fix aui/daui/dahi/dati for MIPSR6 by Simon Dardis · 9 years ago
- f0ed16e [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations by Hrvoje Varga · 9 years ago
- b03fd12 Replace "fallthrough" comments with LLVM_FALLTHROUGH by Justin Bogner · 9 years ago
- cba9f80 [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support by Zlatko Buljan · 9 years ago
- 4fbf76f [mips][atomics] Fix atomic instruction descriptions and uses. by Simon Dardis · 9 years ago
- c962c49 [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions by Hrvoje Varga · 9 years ago
- 672c710 [MIPS][LLVM-MC] Fix Disassemble of Negative Offset by Sagar Thakur · 9 years ago
- 84e4d59 [mips][microMIPS] Implement BEQZC and BNEZC instructions by Zoran Jovanovic · 9 years ago
- 6f09cdf [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions by Hrvoje Varga · 9 years ago
- cf6a781 Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions" by Hrvoje Varga · 9 years ago
- 52c9bed [mips][microMIPS] Implement CFC*, CTC* and LDC* instructions by Hrvoje Varga · 9 years ago
- ba553a6 [mips][microMIPS] Implement LWP and SWP instructions by Zlatko Buljan · 9 years ago
- f6344ff2 [mips][microMIPS] Revert commit r266861. by Zoran Jovanovic · 10 years ago
- fdbd0a3 [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions by Zoran Jovanovic · 10 years ago
- 117625a [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions by Hrvoje Varga · 10 years ago
- 85fd10b [mips] Range check simm16 by Daniel Sanders · 10 years ago
- 6221be8 [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions by Zlatko Buljan · 10 years ago
- 2cb74ac [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions by Hrvoje Varga · 10 years ago
- 9729777 [mips] Range check simm7. by Daniel Sanders · 10 years ago
- 19b7f76 [mips] Range check uimm6_lsl2. by Daniel Sanders · 10 years ago
- 78e8902 [mips] Range check simm4. by Daniel Sanders · 10 years ago
- 36901dd Revert "[mips] Promote the result of SETCC nodes to GPR width." by Vasileios Kalintiris · 10 years ago
- 3a8f7f9 [mips] Promote the result of SETCC nodes to GPR width. by Vasileios Kalintiris · 10 years ago
- f57c197 Reflect the MC/MCDisassembler split on the include/ level. by Benjamin Kramer · 10 years ago
- 5da2f6c [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions by Zlatko Buljan · 10 years ago
- a887b36 [mips][microMIPS] Fix issue with offset operand of BALC and BC instructions by Zoran Jovanovic · 10 years ago
- ebee612 Fix UMRs in Mips disassembler on invalid instruction streams by Reid Kleckner · 10 years ago
- 797c2ae [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions by Zlatko Buljan · 10 years ago
- ea4f653 [mips][ias] Range check uimm2 operands and fix a bug this revealed. by Daniel Sanders · 10 years ago
- 1814867 [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions by Hrvoje Varga · 10 years ago
- 3c88fbd [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions by Hrvoje Varga · 10 years ago
- 3ef4dd7 [mips][microMIPS] Implement LLE and SCE instructions by Hrvoje Varga · 10 years ago
- df19a5e [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values. by Daniel Sanders · 10 years ago
- dc4b8c2 [mips][microMIPS] Fix an issue with disassembling lwm32 instruction by Zoran Jovanovic · 10 years ago
- e4e83a7 [mips] Added support for various EVA ASE instructions. by Daniel Sanders · 10 years ago
- 6b28f09 [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions by Zoran Jovanovic · 10 years ago
- d979079 [mips][microMIPS] Implement CACHEE and PREFE instructions by Zoran Jovanovic · 10 years ago
- 9eaa30d [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions by Zoran Jovanovic · 10 years ago
- ada7091 [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions by Zoran Jovanovic · 10 years ago
- a6593ff [mips][microMIPS] Implement SW and SWE instructions by Zoran Jovanovic · 10 years ago
- 366783e [mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions by Zoran Jovanovic · 10 years ago
- a3134fa [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. by Daniel Sanders · 10 years ago
- 6499b5f [mips] Fix some UB by shifting before sign-extending by Justin Bogner · 10 years ago
- 3adf9b8 [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. by Kai Nacke · 10 years ago
- db0712f Use std::bitset for SubtargetFeatures. by Michael Kuperstein · 10 years ago
- e9119e4 MC: Modernize MCOperand API naming. NFC. by Jim Grosbach · 10 years ago
- c3434b3 Reverting r237234, "Use std::bitset for SubtargetFeatures" by Michael Kuperstein · 10 years ago
- aba4a34 Use std::bitset for SubtargetFeatures by Michael Kuperstein · 10 years ago
- 676d601 [mips][microMIPSr6] Implement disassembler support by Jozef Kolek · 11 years ago
- 29704e7 Revert "Use std::bitset for SubtargetFeatures" by Michael Kuperstein · 11 years ago
- 774b441 Use std::bitset for SubtargetFeatures by Michael Kuperstein · 11 years ago
- efd7a96 Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures. by Michael Kuperstein · 11 years ago
- ba5b04c Use std::bitset for SubtargetFeatures by Michael Kuperstein · 11 years ago
- a19216c [mips] Merge disassemblers into a single implementation. by Daniel Sanders · 11 years ago
- 4168867 [mips][microMIPS] Implement movep instruction by Zoran Jovanovic · 11 years ago
- d68d424a [mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16 by Jozef Kolek · 11 years ago
- df464ae [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. by Vladimir Medic · 11 years ago
- e10a02e [mips][microMIPS] Implement LWGP instruction by Jozef Kolek · 11 years ago
- 4ea2f60 [mips] fix spelling of 'disassembler' by Alexei Starovoitov · 11 years ago
- 5cfebdd [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B by Jozef Kolek · 11 years ago
- 2c6d732 [mips][microMIPS] Implement ADDIUPC instruction by Jozef Kolek · 11 years ago
- 435cf8a [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. by Vladimir Medic · 11 years ago
- 0d49117 Reverted revision 226577. by Jozef Kolek · 11 years ago
- 45f7f9c [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B by Jozef Kolek · 11 years ago
- 9761e96 [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions by Jozef Kolek · 11 years ago
- ab6d1cc [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions by Jozef Kolek · 11 years ago
- 12c6982 [mips][microMIPS] Implement LWSP and SWSP instructions by Jozef Kolek · 11 years ago
- 2c55974 Fix UBSan bootstrap: replace shift of negative value with multiplication. by Alexey Samsonov · 11 years ago
- e886093 The single check for N64 inside MipsDisassemblerBase's subclasses is actually wrong. It should be testing for FeatureGP64bit.There are no functional changes. by Vladimir Medic · 11 years ago
- 2deca34 [mips][microMIPS] Implement SWP and LWP instructions by Zoran Jovanovic · 11 years ago
- d7ecf49 Add disassembler tests for mips3 platform. There are no functional changes. by Vladimir Medic · 11 years ago
- b682ddf The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. by Vladimir Medic · 11 years ago
- f9a0250 [mips][microMIPS] Implement SWM16 and LWM16 instructions by Zoran Jovanovic · 11 years ago
- b4484d6 [mips] Add synci instruction. by Daniel Sanders · 11 years ago
- aa2b927 [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 by Jozef Kolek · 11 years ago
- 315e7ec [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16 by Jozef Kolek · 11 years ago
- 1904fa2 [mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0 by Jozef Kolek · 11 years ago
- ea22c4c [mips][microMIPS] Implement disassembler support for 16-bit instructions by Jozef Kolek · 11 years ago
- a4c4b5f [mips][micromips] Implement SWM32 and LWM32 instructions by Zoran Jovanovic · 11 years ago
- 7fc5b87 Pass an ArrayRef to MCDisassembler::getInstruction. by Rafael Espindola · 11 years ago
- 4aa6bea Misc style fixes. NFC. by Rafael Espindola · 11 years ago
- b0852e5 [mips][microMIPS] Implement microMIPS 16-bit instructions registers by Zoran Jovanovic · 11 years ago
- 92db6b7 [mips] Fix disassembly of [ls][wd]c[23], cache, and pref by Daniel Sanders · 11 years ago
- d37bab6 Fix left shifts of negative values in MipsDisassembler. by Alexey Samsonov · 11 years ago