Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / e55c556a247a9c0decb4e256d9e897dfc9cf841d / llvm / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. e55c556 Convert assert(0) to llvm_unreachable by Craig Topper · 14 years ago
  2. 8b2dcad Enable streaming of bitcode by Derek Schuff · 14 years ago
  3. 46a9f01 More dead code removal (using -Wunreachable-code) by David Blaikie · 14 years ago
  4. 4a5c887 ARM NEON VTBL/VTBX assembly parsing and encoding. by Jim Grosbach · 14 years ago
  5. 88ac761 ARM NEON refactor VST2 w/ writeback instructions. by Jim Grosbach · 14 years ago
  6. 8d24618 ARM NEON VST2 assembly parsing and encoding. by Jim Grosbach · 14 years ago
  7. d146a02 ARM assembly parsing and encoding for VLD2 with writeback. by Jim Grosbach · 14 years ago
  8. 23c30b9 Remove unused variable by Matt Beaumont-Gay · 14 years ago
  9. a68c9a8 ARM parsing for VLD1 all lanes, with writeback. by Jim Grosbach · 14 years ago
  10. 5ee209c ARM assembly parsing and encoding for four-register VST1. by Jim Grosbach · 14 years ago
  11. 98d032f ARM assembly parsing and encoding for three-register VST1. by Jim Grosbach · 14 years ago
  12. 05060f0 Fix a misplaced paren bug. by Owen Anderson · 14 years ago
  13. 0ac9058 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. by Owen Anderson · 14 years ago
  14. 8ca13de Re-apply 144430, this time with the associated isel and disassmbler bits. by Jim Grosbach · 14 years ago
  15. 48b5bbf Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. by Benjamin Kramer · 14 years ago
  16. ec5c5f70 The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. by Owen Anderson · 14 years ago
  17. fad59da Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. by Owen Anderson · 14 years ago
  18. 69e54a7 Fix disassembly of some VST1 instructions. by Owen Anderson · 14 years ago
  19. 05df460 ARM VST1 w/ writeback assembly parsing and encoding. by Jim Grosbach · 14 years ago
  20. 40703f4 More not-crashing NEON disassembly updates for the vld refactoring. by Owen Anderson · 14 years ago
  21. dde461c Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. by Owen Anderson · 14 years ago
  22. 8a6ebd0 Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. by Owen Anderson · 14 years ago
  23. 17ec1a1 ARM assembly parsing and encoding for VLD1 with writeback. by Jim Grosbach · 14 years ago
  24. 92fd05e ARM assembly parsing and encoding for VLD1 w/ writeback. by Jim Grosbach · 14 years ago
  25. 2098cb1 ARM refactor am6offset usage for VLD1. by Jim Grosbach · 14 years ago
  26. 295b1e8 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. by Owen Anderson · 14 years ago
  27. 0d6d098 Move various generated tables into read-only memory, fixing up const correctness along the way. by Benjamin Kramer · 14 years ago
  28. 11c0b34 Assembly parsing for 4-register sequential variant of VLD2. by Jim Grosbach · 14 years ago
  29. 118b38c Assembly parsing for 2-register sequential variant of VLD2. by Jim Grosbach · 14 years ago
  30. 846bcff Assembly parsing for 4-register variant of VLD1. by Jim Grosbach · 14 years ago
  31. c4360fe Assembly parsing for 3-register variant of VLD1. by Jim Grosbach · 14 years ago
  32. 2f2e3c4 ARM VLD parsing and encoding. by Jim Grosbach · 14 years ago
  33. 79ebc51 Tidy up. Trailing whitespace. by Jim Grosbach · 14 years ago
  34. 3495791 Removed set, but unused variables. by Chad Rosier · 14 years ago
  35. 8b47836 Fix a non-firing assert. Change: by Richard Trieu · 14 years ago
  36. a7ad9f3 Fix undefined shift. Patch by Ahmed Charles. by Eli Friedman · 14 years ago
  37. 44f76ea SETEND is not allowed in an IT block. by Owen Anderson · 14 years ago
  38. a098a89 ARM addrmode5 represents the 'U' bit of the encoding backwards. by Jim Grosbach · 14 years ago
  39. 54a20ed Thumb2 assembly parsing and encoding for LDC/STC. by Jim Grosbach · 14 years ago
  40. 8007320 addrmode2 is gone from these, so no need for the reg0 operand. by Jim Grosbach · 14 years ago
  41. 6a5c150 Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. by Owen Anderson · 14 years ago
  42. 5dcda64 Adding back support for printing operands symbolically to ARM's new disassembler by Kevin Enderby · 14 years ago
  43. efc761a ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. by Jim Grosbach · 14 years ago
  44. f01e2de ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. by Owen Anderson · 14 years ago
  45. 987a878 Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. by Owen Anderson · 14 years ago
  46. ffa8428 Revert r140412. This affects more instructions than intended. by Owen Anderson · 14 years ago
  47. 7591d0c Thumb2 register-shifted-register loads cannot target the PC or the SP. by Owen Anderson · 14 years ago
  48. 163be01 tMOVSr is not allowed in an IT block either. by Owen Anderson · 14 years ago
  49. 61e4604 CPS instructions are UNPREDICTABLE inside IT blocks. by Owen Anderson · 14 years ago
  50. f902d92 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. by Owen Anderson · 14 years ago
  51. 05541f4 Thumb2 assembly parsing and encoding for TBB/TBH. by Jim Grosbach · 14 years ago
  52. ddfcec9 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. by Owen Anderson · 14 years ago
  53. 502cd9d Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. by Owen Anderson · 14 years ago
  54. b925e93 Fix bitfield decoding based on Eli's feedback. by Owen Anderson · 14 years ago
  55. bcfa9a6 Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. by Owen Anderson · 14 years ago
  56. 3ca958c Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). by Owen Anderson · 14 years ago
  57. fe82365 Fix disassembly of Thumb2 LDRSH with a #-0 offset. by Owen Anderson · 14 years ago
  58. a0c3b97 Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. by Owen Anderson · 14 years ago
  59. f1e3844 Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. by Owen Anderson · 14 years ago
  60. a9ebf6f Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. by Owen Anderson · 14 years ago
  61. 53db43b LDM writeback is not allowed if Rn is in the target register list. by Owen Anderson · 14 years ago
  62. 5bfb0e0 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. by Owen Anderson · 14 years ago
  63. 29cfe6c Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. by Owen Anderson · 14 years ago
  64. a05627e Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. by Jim Grosbach · 14 years ago
  65. 33d3953 All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. by Owen Anderson · 14 years ago
  66. 2fefa42 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. by Owen Anderson · 14 years ago
  67. 7db8d69 Thumb2 assembly parsing and encoding for LDRD(immediate). by Jim Grosbach · 14 years ago
  68. f174959 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. by Owen Anderson · 14 years ago
  69. 18d17aa Create Thumb2 versions of STC/LDC, and reenable the relevant tests. by Owen Anderson · 14 years ago
  70. 8067df9 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. by James Molloy · 14 years ago
  71. cd5612d Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. by Owen Anderson · 14 years ago
  72. 4c493e8 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. by James Molloy · 14 years ago
  73. ed96b58 Merge the ARM disassembler header into the implementation file, since it is not externally exposed. by Owen Anderson · 14 years ago
  74. 03aadae Fix 80 columns violations. by Owen Anderson · 14 years ago
  75. db4ce60 Fix up r137380 based on post-commit review by Jim Grosbach. by James Molloy · 14 years ago
  76. 4af0aa9 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. by Owen Anderson · 14 years ago
  77. 2fa06a7 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. by Owen Anderson · 14 years ago
  78. b205c02 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. by Owen Anderson · 14 years ago
  79. 240d20a Spelling fail. by Owen Anderson · 14 years ago
  80. 16d33f3 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. by Owen Anderson · 14 years ago
  81. 5658b49 Update for feedback from Jim. by Owen Anderson · 14 years ago
  82. aa38dba ARMDisassembler: Always return a size, even when disassembling fails. by Benjamin Kramer · 14 years ago
  83. a01bcbf Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. by Owen Anderson · 14 years ago
  84. 1496956 Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. by Owen Anderson · 14 years ago
  85. 5e30972 Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. by Owen Anderson · 14 years ago
  86. 37612a3 Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. by Owen Anderson · 14 years ago
  87. 216cfaa Be careful not to walk off the end of the operand info list while updating VFP predicates. by Owen Anderson · 14 years ago
  88. 2bb4035 Move TargetRegistry and TargetSelect from Target to Support where they belong. by Evan Cheng · 14 years ago
  89. 5230041 Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. by Owen Anderson · 14 years ago
  90. 924bcfc Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. by Owen Anderson · 14 years ago
  91. 9b7bd15 Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. by Owen Anderson · 14 years ago
  92. eb1367b Reject invalid imod values in t2CPS instructions. by Owen Anderson · 14 years ago
  93. df698b0 Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. by Owen Anderson · 14 years ago
  94. 721c370 Fix another batch of VLD/VST decoding crashes discovered by randomized testing. by Owen Anderson · 14 years ago
  95. ac92e77 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. by Owen Anderson · 14 years ago
  96. b498132 Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. by Owen Anderson · 14 years ago
  97. 96b7ad2 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. by Owen Anderson · 14 years ago
  98. 192a760 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. by Owen Anderson · 14 years ago
  99. 5d2db89 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. by Owen Anderson · 14 years ago
  100. 67d6f11 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. by Owen Anderson · 14 years ago