- e493f17 [AArch64] Allow access to all system registers with MRS/MSR instructions. by Tom Coxon · 11 years ago
- 2c13e71 [AArch64] Remove unnecessary whitespace. (Test commit) by Tom Coxon · 11 years ago
- 729b12e Fix left shifts of negative integers in AArch64 InstPrinter/Disassembler by Alexey Samsonov · 11 years ago
- 1f8930e Run sort_includes.py on the AArch64 backend. by Benjamin Kramer · 11 years ago
- 35910d7 AArch64: remove "arm64_be" support in favour of "aarch64_be". by Tim Northover · 11 years ago
- 3b0846e AArch64/ARM64: move ARM64 into AArch64's place by Tim Northover · 11 years ago[Renamed (69%) from llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp]
- cc08e1f AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. by Tim Northover · 11 years ago
- 4a3ab28 ARM64: model pre/post-indexed operations properly. by Tim Northover · 11 years ago
- c350acf ARM64: separate load/store operands to simplify assembler by Tim Northover · 11 years ago
- c3b931d [ARM64] Split tbz/tbnz into W/X register variant by Bradley Smith · 11 years ago
- e0483f9c [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted by Bradley Smith · 11 years ago
- 618850b AArch64/ARM64: implement diagnosis of unpredictable loads & stores by Tim Northover · 11 years ago
- 523b5a4 ARM64: refactor NEON post-indexed loads & stores (MC). by Tim Northover · 11 years ago
- f57d5ca [ARM64] Conditionalize CPU specific system registers on subtarget features by Bradley Smith · 11 years ago
- d53a671 AArch64/ARM64: expunge CPSR from the sources by Tim Northover · 11 years ago
- 79ec019 AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands by Tim Northover · 11 years ago
- 650cb57 [ARM64] Add a big endian version of the ARM64 target machine, and update all users. by James Molloy · 11 years ago
- 84e68b2 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 11 years ago
- d174b72 [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some by Chandler Carruth · 11 years ago
- 9d205d4 ARM64: Extended addressing mode source reg is 64-bit. by Jim Grosbach · 11 years ago
- a1bc0f5 [MC] Require an MCContext when constructing an MCDisassembler. by Lang Hames · 12 years ago
- 30120c0 Make helper static and place random global into the llvm namespace. by Benjamin Kramer · 12 years ago
- 95400e2 Remove redundant symbolization support from MCDisassembler interface. by Lang Hames · 12 years ago
- a2308f4 [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. by Bradley Smith · 12 years ago
- a19b7e8 [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. by Bradley Smith · 12 years ago
- af2710c [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. by Bradley Smith · 12 years ago
- eb4ca04 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. by Bradley Smith · 12 years ago
- 4925be9 [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. by Bradley Smith · 12 years ago
- 08c391c [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. by Bradley Smith · 12 years ago
- 2ba17a4 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. by Bradley Smith · 12 years ago
- 8c0b88c [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. by Bradley Smith · 12 years ago
- 35cadc5 [ARM64] STRHro and STRBro were not being decoded at all. by Bradley Smith · 12 years ago
- 87c60e0 [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4. by Bradley Smith · 12 years ago
- cd91e5c [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined. by Bradley Smith · 12 years ago
- d1726ee Fixing warnings in the MSVC build. No functional changes intended. by Aaron Ballman · 12 years ago
- 23aaf2a Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() always initialize Size argument. by Alexey Samsonov · 12 years ago
- 7b7a67c [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is by Chandler Carruth · 12 years ago
- 00ed996 ARM64: initial backend import by Tim Northover · 12 years ago