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gerrit-public.fairphone.software / toolchain / llvm-project / e94ee833f9444b629bdbbd9fd08b51a04560c1a0 / llvm / lib / Target / RISCV / RISCVSubtarget.h
  1. 3969425 [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation by Shiva Chen · 7 years ago
  2. 9f6aec4 [RISCV] MC layer support for load/store instructions of the C (compressed) extension by Alex Bradbury · 8 years ago
  3. 7bc2a95 [RISCV] MC layer support for the standard RV32D instruction set extension by Alex Bradbury · 8 years ago
  4. 0d6cf90 [RISCV] MC layer support for the standard RV32F instruction set extension by Alex Bradbury · 8 years ago
  5. b3bde2e Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
  6. 8c345c5 [RISCV] MC layer support for the standard RV32A instruction set extension by Alex Bradbury · 8 years ago
  7. a47514c [RISCV] MC layer support for the standard RV32M instruction set extension by Alex Bradbury · 8 years ago
  8. 8971842 [RISCV] Initial codegen support for ALU operations by Alex Bradbury · 8 years ago