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gerrit-public.fairphone.software / toolchain / llvm-project / eb952fd93b71ecb83b1510c47b00b65ce3d26a26 / llvm / lib / Target / AMDGPU / SIInstrInfo.cpp
  1. 9dba9bd AMDGPU: Use source modifiers with f16->f32 conversions by Matt Arsenault · 9 years ago
  2. 74f6483 AMDGPU: Allow clustering flat memory operations by Matt Arsenault · 9 years ago
  3. 9f5e0ef AMDGPU: Implement early ifcvt target hooks. by Matt Arsenault · 9 years ago
  4. 6ec3e3a [AMDGPU] Prevent spills before exec mask is restored by Stanislav Mekhanoshin · 9 years ago
  5. 116bbab [CodeGen] Rename MachineInstrBuilder::addOperand. NFC by Diana Picus · 9 years ago
  6. 4c1e9ec AMDGPU: Don't add same instruction multiple times to worklist by Matt Arsenault · 9 years ago
  7. 4bd7236 AMDGPU: Fix handling of 16-bit immediates by Matt Arsenault · 9 years ago
  8. 8485fa0 AMDGPU : Add S_SETREG instructions to fix fdiv precision issues. by Tom Stellard · 9 years ago
  9. 26faed3 AMDGPU: Consolidate inline immediate predicate functions by Matt Arsenault · 9 years ago
  10. 97279a8 AMDGPU: Rename flat operands to match mubuf by Matt Arsenault · 9 years ago
  11. 437fd71 AMDGPU: Use else if by Matt Arsenault · 9 years ago
  12. 79c0587 AMDGPU/SI: Add back reverted SGPR spilling code, but disable it by Marek Olsak · 9 years ago
  13. e3895bf Revert "AMDGPU: Implement SGPR spilling with scalar stores" by Marek Olsak · 9 years ago
  14. a45dae4 Revert "AMDGPU: Make m0 unallocatable" by Marek Olsak · 9 years ago
  15. 9e5c7b1 AMDGPU: Make m0 unallocatable by Matt Arsenault · 9 years ago
  16. ce2b589 AMDGPU: Fix legalization of MUBUF instructions in shaders by Nicolai Haehnle · 9 years ago
  17. 0d162b1 AMDGPU/SI: Avoid creating unnecessary copies in the SIFixSGPRCopies pass by Tom Stellard · 9 years ago
  18. 3666629 AMDGPU: Analyze mubuf with immediate soffset by Matt Arsenault · 9 years ago
  19. ea91cca [AMDGPU] Add wave barrier builtin by Stanislav Mekhanoshin · 9 years ago
  20. dc45274 AMDGPU: Implement SGPR spilling with scalar stores by Matt Arsenault · 9 years ago
  21. f86e4b7 [AMDGPU] Add f16 support (VI+) by Konstantin Zhuravlyov · 9 years ago
  22. 52f14ec AMDGPU: Preserve vcc undef flags when inverting branch by Matt Arsenault · 9 years ago
  23. 314cbf7 AMDGPU: Refactor copyPhysReg by Matt Arsenault · 9 years ago
  24. 368972c AMDGPU: Allow additional implicit operands on MOVRELS instructions by Nicolai Haehnle · 9 years ago
  25. 3d46319 AMDGPU: Default to using scalar mov to materialize immediate by Matt Arsenault · 9 years ago
  26. 2d8c289 AMDGPU: Workaround for instruction size with literals by Matt Arsenault · 9 years ago
  27. c88ba36 AMDGPU: Use 1/2pi inline imm on VI by Matt Arsenault · 9 years ago
  28. 6695ba0 AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructions by Tom Stellard · 9 years ago
  29. 7b64755 AMDGPU: Add definitions for scalar store instructions by Matt Arsenault · 9 years ago
  30. 08906a3 AMDGPU: Fix using incorrect private resource with no allocation by Matt Arsenault · 9 years ago
  31. 1110f14 AMDGPU: Fix counting si_mask_branch as 4 bytes by Matt Arsenault · 9 years ago
  32. a785209 AMDGPU: Fix Two Address problems with v_movreld by Nicolai Haehnle · 9 years ago
  33. c96b5d7 [AMDGPU] Emit 32-bit lo/hi got and pc relative variant kinds for external and global address space variables by Konstantin Zhuravlyov · 9 years ago
  34. d486d3f AMDGPU: Initial implementation of VGPR indexing mode by Matt Arsenault · 9 years ago
  35. 6bc43d8 BranchRelaxation: Support expanding unconditional branches by Matt Arsenault · 9 years ago
  36. 5d8eb25 AMDGPU: Use unsigned compare for eq/ne by Matt Arsenault · 9 years ago
  37. e674075 AMDGPU: Partially fix control flow at -O0 by Matt Arsenault · 9 years ago
  38. 7b1dc2c AMDGPU: Use i64 scalar compare instructions by Matt Arsenault · 9 years ago
  39. 7ccf6cd AMDGPU: Use SOPK compare instructions by Matt Arsenault · 9 years ago
  40. 1b9fc8e Finish renaming remaining analyzeBranch functions by Matt Arsenault · 9 years ago
  41. e8e0f5c Make analyzeBranch family of instruction names consistent by Matt Arsenault · 9 years ago
  42. a2b036e AArch64: Use TTI branch functions in branch relaxation by Matt Arsenault · 9 years ago
  43. 25dba30 AMDGPU: Support commuting a FrameIndex operand by Matt Arsenault · 9 years ago
  44. e58e0e3 AMDGPU: Do not clobber SCC in SIWholeQuadMode by Nicolai Haehnle · 9 years ago
  45. 3354f42 AMDGPU: Implement is{LoadFrom|StoreTo}FrameIndex by Matt Arsenault · 9 years ago
  46. 124384f AMDGPU: Fix immediate folding logic when shrinking instructions by Matt Arsenault · 9 years ago
  47. 1eeb11b AMDGPU] Assembler: better support for immediate literals in assembler. by Sam Kolton · 9 years ago
  48. d745c28 AMDGPU: Sign extend constants when splitting them by Matt Arsenault · 9 years ago
  49. bbb47da AMDGPU: Support commuting with immediate in src0 by Matt Arsenault · 9 years ago
  50. 1d65026 [AMDGPU] Wave and register controls by Konstantin Zhuravlyov · 9 years ago
  51. 2add8a1 AMDGPU/SI: Teach SIInstrInfo::FoldImmediate() to fold immediates into copies by Tom Stellard · 9 years ago
  52. ac42ba8 AMDGPU: Set sizes of spill pseudos by Matt Arsenault · 9 years ago
  53. 2510a31 AMDGPU: Fix spilling of m0 by Matt Arsenault · 9 years ago
  54. 662f330 AMDGPU/SI: Query AA, if available, in areMemAccessesTriviallyDisjoint() by Tom Stellard · 9 years ago
  55. 22e4179 AMDGPU: Move cndmask pseudo to be isel pseudo by Matt Arsenault · 9 years ago
  56. b03fd12 Replace "fallthrough" comments with LLVM_FALLTHROUGH by Justin Bogner · 9 years ago
  57. c1ebd82 AMDGPU: Fix not estimating MBB operand sizes correctly by Matt Arsenault · 9 years ago
  58. 11587d9 AMDGPU: Remove unnecessary cast by Matt Arsenault · 9 years ago
  59. 941a705 MachineFunction: Return reference for getFrameInfo(); NFC by Matthias Braun · 9 years ago
  60. 19f4301 AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling by Tom Stellard · 9 years ago
  61. 52ef401 AMDGPU: Make AMDGPUMachineFunction fields private by Matt Arsenault · 9 years ago
  62. cb540bc AMDGPU: Expand register indexing pseudos in custom inserter by Matt Arsenault · 9 years ago
  63. 73d2f89 AMDGPU: Fix verifier error from partially undef copy by Matt Arsenault · 9 years ago
  64. 71c30a1 Rename AnalyzeBranch* to analyzeBranch*. by Jacques Pienaar · 9 years ago
  65. fc7e6a0 AMDGPU: Cleanup pseudoinstructions by Matt Arsenault · 9 years ago
  66. 52a4d9b AMDGPU: Move R600 only pieces into R600 classes by Matt Arsenault · 9 years ago
  67. 1322b6f AMDGPU: Improve offset folding for register indexing by Matt Arsenault · 9 years ago
  68. 95c7897 AMDGPU: Simplify isSchedulingBoundary by Matt Arsenault · 9 years ago
  69. 4d29511 AMDGPU: Remove implicit iterator conversions, NFC by Duncan P. N. Exon Smith · 9 years ago
  70. ffc8275 AMDGPU: Fix folding SGPRs into madak/madmk src0 by Matt Arsenault · 9 years ago
  71. 9cfc75c CodeGen: Use MachineInstr& in TargetInstrInfo, NFC by Duncan P. N. Exon Smith · 9 years ago
  72. 3d84650 AMDGPU: Remove unused function by Matt Arsenault · 9 years ago
  73. 43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
  74. 529cf25 AMDGPU: readlane/writelane do not read exec by Matt Arsenault · 9 years ago
  75. fd92154 Reformat blank lines. by NAKAMURA Takumi · 9 years ago
  76. fe1202c Untabify. by NAKAMURA Takumi · 9 years ago
  77. 3e06e1e AMDGPU/SI: Propagate the Kill flag in storeRegToStackSlot and eliminateFrameIndex by Changpeng Fang · 9 years ago
  78. bf3e6e5 AMDGPU/SI: Refactor fixup handling for constant addrspace variables by Tom Stellard · 9 years ago
  79. b1a523f Revert "AMDGPU/SI: Refactor fixup handling for constant addrspace variables" by Tom Stellard · 9 years ago
  80. 5e6298b AMDGPU/SI: Refactor fixup handling for constant addrspace variables by Tom Stellard · 9 years ago
  81. e93f6d6 AMDGPU/SI: Set INDEX_STRIDE for scratch coalescing by Marek Olsak · 9 years ago
  82. 80bc355 AMDGPU: Fix post-RA verifier errors with trackLivenessAfterRegAlloc by Matt Arsenault · 9 years ago
  83. bdc4956 Pass DebugLoc and SDLoc by const ref. by Benjamin Kramer · 9 years ago
  84. 02458c2 AMDGPU: Add function for getting instruction size by Matt Arsenault · 9 years ago
  85. 43578ec AMDGPU: Handle flat in getMemOpBaseRegImmOfs by Matt Arsenault · 9 years ago
  86. 598f553 AMDGPU: Fix incorrectly setting kill flag when copying register tuples by Matt Arsenault · 9 years ago
  87. b6e1cc2 AMDGPU: Fix verifier error when spilling SGPRs by Matt Arsenault · 9 years ago
  88. 4945905 AMDGPU: Handle cbranch vccz/vccnz by Matt Arsenault · 9 years ago
  89. 72fcd5f AMDGPU: Implement ReverseBranchCondition by Matt Arsenault · 9 years ago
  90. 6d09380 AMDGPU: Implement AnalyzeBranch by Matt Arsenault · 9 years ago
  91. 999f7dd AMDGPU: Remove verifier check for scc live ins by Matt Arsenault · 9 years ago
  92. 341e293 AMDGPU/SI: Fix bug in SIInstrInfo::insertWaitStates() uncovered by r268260 by Tom Stellard · 10 years ago
  93. cb6ba62 AMDGPU/SI: Enable the post-ra scheduler by Tom Stellard · 10 years ago
  94. 92b24f3 AMDGPU/SI: Add offset field to ds_permute/ds_bpermute instructions by Tom Stellard · 10 years ago
  95. 06c14ec Fix incorrect redundant expression in target AMDGPU. by Etienne Bergeron · 10 years ago
  96. b0c9748 AMDGPU/SI: add llvm.amdgcn.ps.live intrinsic by Nicolai Haehnle · 10 years ago
  97. e2dda4f AMDGPU: Guard VOPC instructions against incorrect commute by Nicolai Haehnle · 10 years ago
  98. 4c5bd58 [MachineScheduler]Add support for store clustering by Jun Bum Lim · 10 years ago
  99. 3d1c1de AMDGPU: Run SIFoldOperands after PeepholeOptimizer by Matt Arsenault · 10 years ago
  100. 703b2ec AMDGPU/SI: Fix spilling of 96-bit registers by Tom Stellard · 10 years ago