- 4e55c1e AMDGPU: Update isFPImmLegal for f16 by Matt Arsenault · 9 years ago
- 6f9ef14 AMDGPU/SI: Add a MachineMemOperand when lowering llvm.amdgcn.buffer.load.* by Tom Stellard · 9 years ago
- 0b38636 AMDGPU: Fix asserting on returned tail calls by Matt Arsenault · 9 years ago
- f5bf03c Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled." by Nirav Dave · 9 years ago
- 8527ab0 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. by Nirav Dave · 9 years ago
- 17c7f70 Replace APFloatBase static fltSemantics data members with getter functions by Stephan Bergmann · 9 years ago
- 38d8ed2 AMDGPU: Fix i128 mul by Matt Arsenault · 9 years ago
- bedb5d9 Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled." by Nirav Dave · 9 years ago
- fd51ff4 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. by Nirav Dave · 9 years ago
- 8485fa0 AMDGPU : Add S_SETREG instructions to fix fdiv precision issues. by Tom Stellard · 9 years ago
- 7bee6ac AMDGPU: Refactor exp instructions by Matt Arsenault · 9 years ago
- 0ee250e [AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies by Stanislav Mekhanoshin · 9 years ago
- c79dc70 AMDGPU: Fix f16 fabs/fneg by Matt Arsenault · 9 years ago
- f86e4b7 [AMDGPU] Add f16 support (VI+) by Konstantin Zhuravlyov · 9 years ago
- 6fc8a1c Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies" by Stanislav Mekhanoshin · 9 years ago
- 21f9ce1 [DAG Combiner] Fix the native computation of the Newton series for reciprocals by Evandro Menezes · 9 years ago
- 115a615 AMDGPU: Add VI i16 support by Tom Stellard · 9 years ago
- 92e01ee [AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies by Stanislav Mekhanoshin · 9 years ago
- 2d2d33f Revert "AMDGPU: Add VI i16 support" by Tom Stellard · 9 years ago
- 2b3379c AMDGPU: Add VI i16 support by Tom Stellard · 9 years ago
- d971a11 [AMDGPU] Check if type transforms to i16 (VI+) when getting AMDGPUISD::FFBH_U32 by Konstantin Zhuravlyov · 9 years ago
- 9677b60 AMDGPU: Fix buildbots broken by r285704 by Tom Stellard · 9 years ago
- 94c21bc AMDGPU: Implement expansion of f16 = FP_TO_FP16 f64 by Tom Stellard · 9 years ago
- 8a89d36 [AMDGPU] Expand vector mulhu/mulhs by Valery Pykhtin · 9 years ago
- 6c7dd98 AMDGPU/SI: Fix crash caused by r284267 by Tom Stellard · 9 years ago
- 0051efc [Target] remove TargetRecip class; 2nd try by Sanjay Patel · 9 years ago
- 19601fa revert r284495: [Target] remove TargetRecip class by Sanjay Patel · 9 years ago
- 08fff9c [Target] remove TargetRecip class; move reciprocal estimate isel functionality to TargetLowering by Sanjay Patel · 9 years ago
- 09c2bd6 AMDGPU/SI: Use new SimplifyDemandedBits helper for multi-use operations by Tom Stellard · 9 years ago
- a81682a Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled." by Nirav Dave · 9 years ago
- 4b36957 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. by Nirav Dave · 9 years ago
- 5c924d7 Target: Remove unused entities. by Peter Collingbourne · 9 years ago
- e524f50 Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled." by Nirav Dave · 9 years ago
- e17e055 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. by Nirav Dave · 9 years ago
- d99ef11 AMDGPU: Push bitcasts through build_vector by Matt Arsenault · 9 years ago
- 7998db6 AMDGPU/SI: Fix kernel argument ABI for HSA by Tom Stellard · 9 years ago
- bbeb45a AMDGPU: Refactor kernel argument lowering by Tom Stellard · 9 years ago
- fa5f767 AMDGPU: Improve splitting 64-bit bit ops by constants by Matt Arsenault · 9 years ago
- b2869eb AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is 8-byte aligned for HSA by Tom Stellard · 9 years ago
- b50eb8d AMDGPU: Fix introducing stack access on unaligned v16i8 by Matt Arsenault · 9 years ago
- ba57308 AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is at least 4-byte aligned by Tom Stellard · 9 years ago
- 77ed6af AMDGPU/R600: Remove MergeVectorStores from legalization by Jan Vesely · 9 years ago
- 2712d4a AMDGPU: Select mulhi 24-bit instructions by Matt Arsenault · 9 years ago
- f679530 [X86] Heuristic to selectively build Newton-Raphson SQRT estimation by Nikolai Bozhenov · 9 years ago
- 07e0371 AMDGPU : Add intrinsics for compare with the full wavefront result by Wei Ding · 9 years ago
- edc7dcb AMDGPU: Turn dead checks into asserts by Matt Arsenault · 9 years ago
- 52ef401 AMDGPU: Make AMDGPUMachineFunction fields private by Matt Arsenault · 9 years ago
- 32fc527 AMDGPU: Add fp legacy instruction intrinsics by Matt Arsenault · 9 years ago
- cdae95b AMDGPU: Delete dead code by Matt Arsenault · 9 years ago
- b40d860 AMDGPU: Delete dead code by Matt Arsenault · 9 years ago
- 03006fd AMDGPU: Only use legal inline immediates with kill pseudo by Matt Arsenault · 9 years ago
- b51dcb9 AMDGPU: Fix missing switch case warning by Matt Arsenault · 9 years ago
- a65e6b8 AMDGPU: Remove brev intrinsic by Matt Arsenault · 9 years ago
- 11d3e21 AMDGPU: Remove AMDGPU.ldexp by Matt Arsenault · 9 years ago
- 9c37581 [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends. by Justin Lebar · 9 years ago
- 0bf9984 AMDGPU: Remove dead code by Matt Arsenault · 9 years ago
- f071102 AMDGPU: Remove last AMDIL intrinsics by Matt Arsenault · 9 years ago
- 8af47a0 AMDGPU: Expand unaligned accesses early by Matt Arsenault · 9 years ago
- 327bb5a AMDGPU: Improve load/store of illegal types. by Matt Arsenault · 9 years ago
- 43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
- e440f99 [AMDGPU] Remove exit-on-error in test (PR27761) by Diana Picus · 9 years ago
- 9babdf4 AMDGPU: Fix verifier errors in SILowerControlFlow by Matt Arsenault · 9 years ago
- e935f05 AMDGPU: Fix kernel argument alignment impacting stack size by Matt Arsenault · 9 years ago
- bf3e6e5 AMDGPU/SI: Refactor fixup handling for constant addrspace variables by Tom Stellard · 9 years ago
- b1a523f Revert "AMDGPU/SI: Refactor fixup handling for constant addrspace variables" by Tom Stellard · 9 years ago
- 5e6298b AMDGPU/SI: Refactor fixup handling for constant addrspace variables by Tom Stellard · 9 years ago
- bdc4956 Pass DebugLoc and SDLoc by const ref. by Benjamin Kramer · 9 years ago
- 52dec8d AMDGPU: Temporary fix for broken store combine by Matt Arsenault · 9 years ago
- 1cc4991 AMDGPU: Fix inconsistent lowering of select of vectors by Matt Arsenault · 9 years ago
- 71e6676 AMDGPU: Cleanup lowering actions by Matt Arsenault · 9 years ago
- 81a7095 AMDGPU: Fix high bits after division optimization by Matt Arsenault · 9 years ago
- 4e3d383 AMDGPU: Remove pointless conversions by Matt Arsenault · 9 years ago
- 9430b91 AMDGPU: Fix assert when erroring on a call by Matt Arsenault · 9 years ago
- 91aacad AMDGPU: Unify LowerGlobalAddress by Jan Vesely · 9 years ago
- 27233b7 AMDGPU: Move R600 specific code out of AMDGPUISelLowering.cpp by Tom Stellard · 10 years ago
- 33772c5 [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. by Craig Topper · 10 years ago
- 128f873 [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI. by Ahmed Bougacha · 10 years ago
- dfaf426 AMDGPU: Add DAG to debug dump by Matt Arsenault · 10 years ago
- efa3fe1 AMDGPU: Re-visit nodes in performAndCombine by Matt Arsenault · 10 years ago
- 9c499c3 AMDGPU: Remove custom load/store scalarization by Matt Arsenault · 10 years ago
- 7900334 AMDGPU: Fold bitcasts of scalar constants to vectors by Matt Arsenault · 10 years ago
- a9dbdca AMDGPU: Add atomic_inc + atomic_dec intrinsics by Matt Arsenault · 10 years ago
- 354a43c AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2} by Tom Stellard · 10 years ago
- ef0fe1e Silencing warnings from MSVC 2015 Update 2. All of these changes silence "C4334 '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)". NFC. by Aaron Ballman · 10 years ago
- 6b6a2c3 AMDGPU: R600 code splitting cleanup by Matt Arsenault · 10 years ago
- 81d0601 AMDGPU: Move function only used by R600 by Matt Arsenault · 10 years ago
- 8226fc4 AMDGPU: Simplify boolean conditional return statements by Matt Arsenault · 10 years ago
- d275fca AMDGPU: Don't emit build_pair during udivrem legalization by Matt Arsenault · 10 years ago
- 59b8b77 AMDGPU: Set HasExtractBitInsn by Matt Arsenault · 10 years ago
- 79963e8 AMDGPU: Rename intrinsic to better match instruction name by Matt Arsenault · 10 years ago
- 16f7bcb AMDGPU: Fix mishandling alignment when scalarizing vector loads/stores by Matt Arsenault · 10 years ago
- 9524566 AMDGPU: Split R600 and SI store lowering by Matt Arsenault · 10 years ago
- 6dfda96 AMDGPU: Split R600 and SI load lowering by Matt Arsenault · 10 years ago
- f8dfb47 [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI. by Ahmed Bougacha · 10 years ago
- 92edab2 AMDGPU: Remove bfi and bfm intrinsics by Matt Arsenault · 10 years ago
- 7f83397 AMDGPU: Account for LDS alignment by Matt Arsenault · 10 years ago
- 7e7d983 Refactor backend diagnostics for unsupported features by Oliver Stannard · 10 years ago
- 295875e AMDGPU: Remove 24-bit intrinsics by Matt Arsenault · 10 years ago
- 5b39b34 AMDGPU: Match fmed3 patterns with legacy fmin/fmax by Matt Arsenault · 10 years ago
- f639c32 AMDGPU: Match some med3 patterns by Matt Arsenault · 10 years ago