1. f435b09 Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. by Richard Barton · 14 years ago
  2. c407cc7 For ARM disassembly only print 32 unsigned bits for the address of branch by Kevin Enderby · 14 years ago
  3. 1c0541b Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. by Benjamin Kramer · 14 years ago
  4. dab9e35 Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. by Craig Topper · 14 years ago
  5. 54bfde7 Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. by Craig Topper · 14 years ago
  6. ed428bc ARM more NEON VLD/VST composite physical register refactoring. by Jim Grosbach · 14 years ago
  7. 13a292c ARM refactor more NEON VLD/VST instructions to use composite physregs by Jim Grosbach · 14 years ago
  8. 63ee881 Tidy up. Kill some dead code. by Jim Grosbach · 14 years ago
  9. e5307f9 ARM Refactor VLD/VST spaced pair instructions. by Jim Grosbach · 14 years ago
  10. c988e0c ARM refactor away a bunch of VLD/VST pseudo instructions. by Jim Grosbach · 14 years ago
  11. fd93a59 Make MCRegisterInfo available to the the MCInstPrinter. by Jim Grosbach · 14 years ago
  12. f0269b4 Change ARMInstPrinter::printPredicateOperand() so it will not abort if it by Kevin Enderby · 14 years ago
  13. 636a3d6 Remove dead code. Improve llvm_unreachable text. Simplify some control flow. by Ahmed Charles · 14 years ago
  14. e55c556 Convert assert(0) to llvm_unreachable by Craig Topper · 14 years ago
  15. 086cbfa NEON VLD4(all lanes) assembly parsing and encoding. by Jim Grosbach · 14 years ago
  16. b78403c NEON VLD3(all lanes) assembly parsing and encoding. by Jim Grosbach · 14 years ago
  17. ed561fc NEON VLD4(multiple 4 element structures) assembly parsing. by Jim Grosbach · 14 years ago
  18. ac2af3f NEON VLD3(multiple 3-element structures) assembly parsing. by Jim Grosbach · 14 years ago
  19. ea23191 ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). by Jim Grosbach · 14 years ago
  20. c5af54e ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. by Jim Grosbach · 14 years ago
  21. 8648c10 ARM assembly parsing and encoding support for LDRD(label). by Jim Grosbach · 14 years ago
  22. 8d24618 ARM NEON VST2 assembly parsing and encoding. by Jim Grosbach · 14 years ago
  23. 3ecf976 ARM parsing for VLD1 two register all lanes, no writeback. by Jim Grosbach · 14 years ago
  24. cd6f5e7 ARM parsing aliases for VLD1 single register all lanes. by Jim Grosbach · 14 years ago
  25. 69d57cf Simplify some uses of utohexstr. by Benjamin Kramer · 14 years ago
  26. fbb704f Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. by Owen Anderson · 14 years ago
  27. 846bcff Assembly parsing for 4-register variant of VLD1. by Jim Grosbach · 14 years ago
  28. c4360fe Assembly parsing for 3-register variant of VLD1. by Jim Grosbach · 14 years ago
  29. 2f2e3c4 ARM VLD parsing and encoding. by Jim Grosbach · 14 years ago
  30. 20cb505 whitespace. by Jim Grosbach · 14 years ago
  31. ad47cfc ARM VTBL (one register) assembly parsing and encoding. by Jim Grosbach · 14 years ago
  32. 4839958 ARM parsing and encoding for the <option> form of LDC/STC instructions. by Jim Grosbach · 14 years ago
  33. d74c0e7 80 columns. by Jim Grosbach · 14 years ago
  34. 6966411 Tidy up. Formatting. by Jim Grosbach · 14 years ago
  35. d0637bf ARM NEON assembly parsing and encoding for VDUP(scalar). by Jim Grosbach · 14 years ago
  36. 10c5b12 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. by Owen Anderson · 14 years ago
  37. 5dcda64 Adding back support for printing operands symbolically to ARM's new disassembler by Kevin Enderby · 14 years ago
  38. efc761a ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. by Jim Grosbach · 14 years ago
  39. 21efa7d Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. by James Molloy · 14 years ago
  40. 737beaf Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. by Owen Anderson · 14 years ago
  41. fbe52c0 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. by Owen Anderson · 14 years ago
  42. f52c68f Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. by Owen Anderson · 14 years ago
  43. bcc3fad These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. by Owen Anderson · 14 years ago
  44. 69fa8ff In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. by Owen Anderson · 14 years ago
  45. 05541f4 Thumb2 assembly parsing and encoding for TBB/TBH. by Jim Grosbach · 14 years ago
  46. fe82365 Fix disassembly of Thumb2 LDRSH with a #-0 offset. by Owen Anderson · 14 years ago
  47. a0c3b97 Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. by Owen Anderson · 14 years ago
  48. d181479 Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode. by Owen Anderson · 14 years ago
  49. 7f0e98f Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. by Owen Anderson · 14 years ago
  50. a05627e Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. by Jim Grosbach · 14 years ago
  51. 4c493e8 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. by James Molloy · 14 years ago
  52. 967674d Improve handling of #-0 offsets for many more pre-indexed addressing modes. by Owen Anderson · 14 years ago
  53. af2f827 When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate. by Jim Grosbach · 14 years ago
  54. e364ad5 Clean up Thumb load/store multiple definitions. by Jim Grosbach · 14 years ago
  55. 2597722 Thumb parsing and encoding support for NOP. by Jim Grosbach · 14 years ago
  56. 90103cc Thumb assembly parsing and encoding for LDM instruction. by Jim Grosbach · 14 years ago
  57. 50aafea Remove extraneous newline from operand print method. PR10569. by Jim Grosbach · 14 years ago
  58. 46dd413 ARM clean up the imm_sr operand class representation. by Jim Grosbach · 14 years ago
  59. e33c95d Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. by Owen Anderson · 14 years ago
  60. 27ad83d ARM push of a single register encodes as pre-indexed STR. by Jim Grosbach · 14 years ago
  61. 8ba76c6 ARM pop of a single register encodes as post-indexed LDR. by Jim Grosbach · 14 years ago
  62. a70fbfd5 ARM simplify the postidx_reg operand encoding. by Jim Grosbach · 14 years ago
  63. bafce84 ARM use a dedicated printer for postidx_reg operands. by Jim Grosbach · 14 years ago
  64. ce51903 LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them. by Owen Anderson · 14 years ago
  65. d359571 ARM refactoring assembly parsing of memory address operands. by Jim Grosbach · 14 years ago
  66. a5f7a8c ARM rot_imm printing adjustment. by Jim Grosbach · 14 years ago
  67. d265913 ARM cleanup of rot_imm encoding. by Jim Grosbach · 14 years ago
  68. 475c6db ARM assembly parsing and encoding for SSAT16 instruction. by Jim Grosbach · 14 years ago
  69. 3a9cbee ARM assembly parsing and encoding for SSAT instruction. by Jim Grosbach · 14 years ago
  70. ad5f485 Sink ARM mc routines into MCTargetDesc. by Evan Cheng · 14 years ago
  71. 801e0a3 ARM SSAT instruction 5-bit immediate handling. by Jim Grosbach · 14 years ago
  72. 0491270 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. by Owen Anderson · 14 years ago
  73. a20cde3 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. by Evan Cheng · 14 years ago
  74. a288b1c ARM PKH shift ammount operand printing tweaks. by Jim Grosbach · 14 years ago
  75. d25c2cd Tweak ARM assembly parsing and printing of MSR instruction. by Jim Grosbach · 14 years ago
  76. 83c6c4f Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. by Owen Anderson · 14 years ago
  77. 7dcd135 Flesh out ARM Parser support for shifted-register operands. by Jim Grosbach · 14 years ago
  78. 581da64 Simplify printing of ARM shifted immediates. by Jim Grosbach · 14 years ago
  79. d686052 Don't hardcode the %reg format in the streamer. by Rafael Espindola · 15 years ago
  80. 33d3a9f Constants with multiple encodings (ARM): by Johnny Chen · 15 years ago
  81. bda3632 - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT by Bruno Cardoso Lopes · 15 years ago
  82. ab83050 Apply again changes to support ARM memory asm parsing. I removed by Bruno Cardoso Lopes · 15 years ago
  83. c2452a6 Revert r128632 again, until I figure out what break the tests by Bruno Cardoso Lopes · 15 years ago
  84. 4c0aebf Reapply r128585 without generating a lib depedency cycle. An updated log: by Bruno Cardoso Lopes · 15 years ago
  85. 73906b0 Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" by Matt Beaumont-Gay · 15 years ago
  86. 280264b - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and by Bruno Cardoso Lopes · 15 years ago
  87. f170f8b Add asm parsing support w/ testcases for strex/ldrex family of instructions by Bruno Cardoso Lopes · 15 years ago
  88. c5efcba Remove some dead patterns. by Jim Grosbach · 15 years ago
  89. e7410dd Preliminary support for ARM frame save directives emission via MI flags. by Anton Korobeynikov · 15 years ago
  90. 9cd4397 Add assembly parsing support for "msr" and also fix its encoding. Also add by Bruno Cardoso Lopes · 15 years ago
  91. 90d1dfe Fix encoding and add parsing support for the arm/thumb CPS instruction: by Bruno Cardoso Lopes · 15 years ago
  92. 4ebf471 Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. by Owen Anderson · 15 years ago
  93. 5a13d4f Add support for printing out floating point values from the ARM assembly by Bill Wendling · 15 years ago
  94. 57990c4 Revert 124230. It was causing test failures. by Bill Wendling · 15 years ago
  95. 624cef6 The floating point value is encoded in its binary form as an Imm. Convert it by Bill Wendling · 15 years ago
  96. c3c7f5d Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting by Owen Anderson · 15 years ago
  97. 092a7bd The tLDR et al instructions were emitting either a reg/reg or reg/imm by Bill Wendling · 15 years ago
  98. 99ea8a3 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. by Owen Anderson · 15 years ago
  99. ca7eaaa When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the by Jim Grosbach · 15 years ago
  100. 7ec3d34 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw by Jim Grosbach · 15 years ago