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gerrit-public.fairphone.software / toolchain / llvm-project / fa5597b24da47d5ecec4560f3f76f4bb08b405bc / llvm / lib / Target / AMDGPU / SILoadStoreOptimizer.cpp
  1. 44b30b4 AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers by Tom Stellard · 7 years ago
  2. d34e60c Rename DEBUG macro to LLVM_DEBUG. by Nicola Zaghen · 7 years ago
  3. 6cf306d AMDGPU: Track physreg uses in SILoadStoreOptimizer by Nicolai Haehnle · 8 years ago
  4. 770397f AMDGPU: Do not combine loads/store across physreg defs by Nicolai Haehnle · 8 years ago
  5. b02cebf AMDGPU: Fix incorrect reordering when inline asm defines LDS address by Matt Arsenault · 8 years ago
  6. b2cc779 AMDGPU: Remove the s_buffer workaround for GFX9 chips by Marek Olsak · 8 years ago
  7. 7687d42 [AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64 by Mark Searles · 8 years ago
  8. f1caa28 MachineFunction: Return reference from getFunction(); NFC by Matthias Braun · 8 years ago
  9. 84445dd AMDGPU: Use gfx9 carry-less add/sub instructions by Matt Arsenault · 8 years ago
  10. 3f71c0e AMDGPU: Select DS insts without m0 initialization by Matt Arsenault · 8 years ago
  11. b4f28de AMDGPU: Re-organize the outer loop of SILoadStoreOptimizer by Nicolai Haehnle · 8 years ago
  12. dd059c1 AMDGPU: Consider memory dependencies with moved instructions in SILoadStoreOptimizer by Nicolai Haehnle · 8 years ago
  13. bee1964 Fix "default label in switch which covers all enumeration values" warning by Vitaly Buka · 8 years ago
  14. 58410f3 AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4 by Marek Olsak · 8 years ago
  15. 4c421a2d AMDGPU: Merge BUFFER_LOAD_DWORD_OFFSET into x2, x4 by Marek Olsak · 8 years ago
  16. 6a0548a AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4 by Marek Olsak · 8 years ago
  17. b953cc3 AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4 by Marek Olsak · 8 years ago
  18. aba2b3d SILoadStoreOptimizer.cpp: Fix build; Clang doesn't like "using anonymous struct" since rL315256. by NAKAMURA Takumi · 8 years ago
  19. 67e72de AMDGPU: Use set for tracked registers by Matt Arsenault · 8 years ago
  20. 3cb6163 AMDGPU: Don't look for DS merge candidates with one use address by Matt Arsenault · 8 years ago
  21. 2d69c92 AMDGPU: Fix typo by Matt Arsenault · 8 years ago
  22. 59e1282 [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
  23. 8b61764 [LegacyPassManager] Remove TargetMachine constructors by Francis Visoiu Mistrih · 8 years ago
  24. 86b0a54 [AMDGPU] added SIInstrInfo::getAddNoCarry() helper by Stanislav Mekhanoshin · 9 years ago
  25. dbc9ba3 Fix -Wunused-value warning by Reid Kleckner · 9 years ago
  26. d026f79 [AMDGPU] Combine DS operations with offsets bigger than byte by Stanislav Mekhanoshin · 9 years ago
  27. 6620376 [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 9 years ago
  28. 116bbab [CodeGen] Rename MachineInstrBuilder::addOperand. NFC by Diana Picus · 9 years ago
  29. f867a40 [AMDGPU][CodeGen] To improve CGEMM performance: combine LDS reads. by Alexander Timofeev · 9 years ago
  30. 7b0e25b AMDGPU: Fix SILoadStoreOptimizer when writes cannot be merged due register dependencies by Nicolai Haehnle · 9 years ago
  31. 117296c Use StringRef in Pass/PassManager APIs (NFC) by Mehdi Amini · 9 years ago
  32. 9720f57 SILoadStoreOptimizer.cpp: Fix a warning in r279991. [-Wunused-variable] by NAKAMURA Takumi · 9 years ago
  33. c2ff0eb AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the scheduler by Tom Stellard · 9 years ago
  34. e175d8a AMDGPU/SI: Canonicalize offset order for merged DS instructions by Tom Stellard · 9 years ago
  35. 90799ce MachineFunction: Introduce NoPHIs property by Matthias Braun · 9 years ago
  36. 0dd9ed1 Fix more dereferenced end() iterators after r278532 by Hans Wennborg · 9 years ago
  37. 03d8584 AMDGPU: Move subtarget feature checks into passes by Matt Arsenault · 9 years ago
  38. 43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
  39. 4897588 Delete some dead code. by Rafael Espindola · 9 years ago
  40. 7de74af Add optimization bisect opt-in calls for AMDGPU passes by Andrew Kaylor · 10 years ago
  41. ecc7cbf Test commit access by Konstantin Zhuravlyov · 10 years ago
  42. 3ac9cc6 CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC by Duncan P. N. Exon Smith · 10 years ago
  43. 84db5d9 AMDGPU/SI: Fix read2 merging into a super register. by Matt Arsenault · 10 years ago
  44. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/SILoadStoreOptimizer.cpp]
  45. 381a94a R600/SI: Remove explicit m0 operand from DS instructions by Tom Stellard · 10 years ago
  46. 799003b Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. by Benjamin Kramer · 11 years ago
  47. 065e3d4 R600/SI: Move gds operand to the end of operand list by Tom Stellard · 11 years ago
  48. 7792e32 Reuse a bunch of cached subtargets and remove getSubtarget calls by Eric Christopher · 11 years ago
  49. 0d2832a R600/SI: Fix live range error hidden by SIFoldOperands by Matt Arsenault · 11 years ago
  50. a99ada5 R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction by Tom Stellard · 11 years ago
  51. da00cf5 Work around bugs in MSVC "14" CTP 3's conversion logic by Reid Kleckner · 11 years ago
  52. fe0a2e6 R600/SI: Match read2/write2 stride 64 versions by Matt Arsenault · 11 years ago
  53. 4103328 R600/SI: Add load / store machine optimizer pass. by Matt Arsenault · 11 years ago