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Roy Huang088eec12007-06-21 11:34:16 +08001/*
2 * file: include/asm-blackfin/mach-bf548/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_548_H_
32#define _MEM_MAP_548_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
40#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
42#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50
51/* Level 1 Memory */
52
53/* Memory Map for ADSP-BF548 processors */
54#ifdef CONFIG_BLKFIN_ICACHE
55#define BLKFIN_ICACHESIZE (16*1024)
56#else
57#define BLKFIN_ICACHESIZE (0*1024)
58#endif
59
60#define L1_CODE_START 0xFFA00000
61#define L1_DATA_A_START 0xFF800000
62#define L1_DATA_B_START 0xFF900000
63
64#define L1_CODE_LENGTH 0xC000
65
66#ifdef CONFIG_BLKFIN_DCACHE
67
68#ifdef CONFIG_BLKFIN_DCACHE_BANKA
69#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
70#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
71#define L1_DATA_B_LENGTH 0x8000
72#define BLKFIN_DCACHESIZE (16*1024)
73#define BLKFIN_DSUPBANKS 1
74#else
75#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
77#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
78#define BLKFIN_DCACHESIZE (32*1024)
79#define BLKFIN_DSUPBANKS 2
80#endif
81
82#else
83#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
84#define L1_DATA_A_LENGTH 0x8000
85#define L1_DATA_B_LENGTH 0x8000
86#define BLKFIN_DCACHESIZE (0*1024)
87#define BLKFIN_DSUPBANKS 0
88#endif /*CONFIG_BLKFIN_DCACHE*/
89
90/* Scratch Pad Memory */
91
92#if defined(CONFIG_BF54x)
93#define L1_SCRATCH_START 0xFFB00000
94#define L1_SCRATCH_LENGTH 0x1000
95#endif
96
97#endif/* _MEM_MAP_548_H_ */