blob: 4466787a52aa0a4682bb007c20c8f4083b3cbd0b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/sh/mm/cache-sh4.c
3 *
4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
Paul Mundtd10040f2007-09-24 16:38:25 +09005 * Copyright (C) 2001 - 2007 Paul Mundt
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * Copyright (C) 2003 Richard Curnow
Chris Smith09b5a102008-07-02 15:17:11 +09007 * Copyright (c) 2007 STMicroelectronics (R&D) Ltd.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/mm.h>
Paul Mundt52e27782006-11-21 11:09:41 +090015#include <linux/io.h>
16#include <linux/mutex.h>
Paul Mundt2277ab42009-07-22 19:20:49 +090017#include <linux/fs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <asm/mmu_context.h>
19#include <asm/cacheflush.h>
20
Paul Mundt28ccf7f2006-09-27 18:30:07 +090021/*
22 * The maximum number of pages we support up to when doing ranged dcache
23 * flushing. Anything exceeding this will simply flush the dcache in its
24 * entirety.
25 */
26#define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */
Chris Smith09b5a102008-07-02 15:17:11 +090027#define MAX_ICACHE_PAGES 32
Paul Mundt28ccf7f2006-09-27 18:30:07 +090028
Richard Curnowb638d0b2006-09-27 14:09:26 +090029static void __flush_dcache_segment_1way(unsigned long start,
30 unsigned long extent);
31static void __flush_dcache_segment_2way(unsigned long start,
32 unsigned long extent);
33static void __flush_dcache_segment_4way(unsigned long start,
34 unsigned long extent);
35
36static void __flush_cache_4096(unsigned long addr, unsigned long phys,
Paul Mundta2527102006-09-27 11:29:55 +090037 unsigned long exec_offset);
Richard Curnowb638d0b2006-09-27 14:09:26 +090038
39/*
40 * This is initialised here to ensure that it is not placed in the BSS. If
41 * that were to happen, note that cache_init gets called before the BSS is
42 * cleared, so this would get nulled out which would be hopeless.
43 */
44static void (*__flush_dcache_segment_fn)(unsigned long, unsigned long) =
45 (void (*)(unsigned long, unsigned long))0xdeadbeef;
46
Linus Torvalds1da177e2005-04-16 15:20:36 -070047/*
48 * SH-4 has virtually indexed and physically tagged cache.
49 */
Paul Mundtecba1062009-08-15 11:05:42 +090050void __init sh4_cache_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051{
Paul Mundt27d59ec2009-08-15 11:11:16 +090052 printk("PVR=%08x CVR=%08x PRR=%08x\n",
53 ctrl_inl(CCN_PVR),
54 ctrl_inl(CCN_CVR),
55 ctrl_inl(CCN_PRR));
Richard Curnowb638d0b2006-09-27 14:09:26 +090056
Paul Mundt7ec9d6f2007-09-21 18:05:20 +090057 switch (boot_cpu_data.dcache.ways) {
Richard Curnowb638d0b2006-09-27 14:09:26 +090058 case 1:
59 __flush_dcache_segment_fn = __flush_dcache_segment_1way;
60 break;
61 case 2:
62 __flush_dcache_segment_fn = __flush_dcache_segment_2way;
63 break;
64 case 4:
65 __flush_dcache_segment_fn = __flush_dcache_segment_4way;
66 break;
67 default:
Paul Mundt27d59ec2009-08-15 11:11:16 +090068 panic("unknown number of cache ways\n");
Richard Curnowb638d0b2006-09-27 14:09:26 +090069 break;
70 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070071}
72
73/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 * Write back the range of D-cache, and purge the I-cache.
75 *
Chris Smith09b5a102008-07-02 15:17:11 +090076 * Called from kernel/module.c:sys_init_module and routine for a.out format,
77 * signal handler code and kprobes code
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 */
79void flush_icache_range(unsigned long start, unsigned long end)
80{
Chris Smith09b5a102008-07-02 15:17:11 +090081 int icacheaddr;
82 unsigned long flags, v;
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 int i;
84
Chris Smith09b5a102008-07-02 15:17:11 +090085 /* If there are too many pages then just blow the caches */
86 if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
87 flush_cache_all();
88 } else {
89 /* selectively flush d-cache then invalidate the i-cache */
90 /* this is inefficient, so only use for small ranges */
91 start &= ~(L1_CACHE_BYTES-1);
92 end += L1_CACHE_BYTES-1;
93 end &= ~(L1_CACHE_BYTES-1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
Chris Smith09b5a102008-07-02 15:17:11 +090095 local_irq_save(flags);
96 jump_to_uncached();
Linus Torvalds1da177e2005-04-16 15:20:36 -070097
Chris Smith09b5a102008-07-02 15:17:11 +090098 for (v = start; v < end; v+=L1_CACHE_BYTES) {
99 asm volatile("ocbwb %0"
100 : /* no output */
101 : "m" (__m(v)));
Richard Curnowb638d0b2006-09-27 14:09:26 +0900102
Chris Smith09b5a102008-07-02 15:17:11 +0900103 icacheaddr = CACHE_IC_ADDRESS_ARRAY | (
104 v & cpu_data->icache.entry_mask);
Richard Curnowb638d0b2006-09-27 14:09:26 +0900105
Chris Smith09b5a102008-07-02 15:17:11 +0900106 for (i = 0; i < cpu_data->icache.ways;
107 i++, icacheaddr += cpu_data->icache.way_incr)
108 /* Clear i-cache line valid-bit */
109 ctrl_outl(0, icacheaddr);
110 }
111
112 back_to_cached();
113 local_irq_restore(flags);
114 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115}
116
117static inline void flush_cache_4096(unsigned long start,
118 unsigned long phys)
119{
Paul Mundt33573c02006-09-27 18:37:30 +0900120 unsigned long flags, exec_offset = 0;
121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 /*
Richard Curnowb638d0b2006-09-27 14:09:26 +0900123 * All types of SH-4 require PC to be in P2 to operate on the I-cache.
124 * Some types of SH-4 require PC to be in P2 to operate on the D-cache.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 */
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900126 if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
Paul Mundt33573c02006-09-27 18:37:30 +0900127 (start < CACHE_OC_ADDRESS_ARRAY))
Paul Mundt510c72ad2006-11-27 12:06:26 +0900128 exec_offset = 0x20000000;
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900129
Paul Mundt33573c02006-09-27 18:37:30 +0900130 local_irq_save(flags);
131 __flush_cache_4096(start | SH_CACHE_ASSOC,
132 P1SEGADDR(phys), exec_offset);
133 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134}
135
136/*
137 * Write back & invalidate the D-cache of the page.
138 * (To avoid "alias" issues)
139 */
140void flush_dcache_page(struct page *page)
141{
Paul Mundt2277ab42009-07-22 19:20:49 +0900142 struct address_space *mapping = page_mapping(page);
143
144#ifndef CONFIG_SMP
145 if (mapping && !mapping_mapped(mapping))
146 set_bit(PG_dcache_dirty, &page->flags);
147 else
148#endif
149 {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150 unsigned long phys = PHYSADDR(page_address(page));
Richard Curnowb638d0b2006-09-27 14:09:26 +0900151 unsigned long addr = CACHE_OC_ADDRESS_ARRAY;
152 int i, n;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153
154 /* Loop all the D-cache */
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900155 n = boot_cpu_data.dcache.n_aliases;
Paul Mundt510c72ad2006-11-27 12:06:26 +0900156 for (i = 0; i < n; i++, addr += 4096)
Richard Curnowb638d0b2006-09-27 14:09:26 +0900157 flush_cache_4096(addr, phys);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158 }
Paul Mundtfdfc74f2006-09-27 14:05:52 +0900159
160 wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161}
162
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900163/* TODO: Selective icache invalidation through IC address array.. */
Paul Mundt205a3b42008-09-05 18:00:29 +0900164static void __uses_jump_to_uncached flush_icache_all(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165{
166 unsigned long flags, ccr;
167
168 local_irq_save(flags);
Stuart Menefycbaa1182007-11-30 17:06:36 +0900169 jump_to_uncached();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170
171 /* Flush I-cache */
172 ccr = ctrl_inl(CCR);
173 ccr |= CCR_CACHE_ICI;
174 ctrl_outl(ccr, CCR);
175
Paul Mundt29847622006-09-27 14:57:44 +0900176 /*
Stuart Menefycbaa1182007-11-30 17:06:36 +0900177 * back_to_cached() will take care of the barrier for us, don't add
Paul Mundt29847622006-09-27 14:57:44 +0900178 * another one!
179 */
180
Stuart Menefycbaa1182007-11-30 17:06:36 +0900181 back_to_cached();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 local_irq_restore(flags);
183}
184
Paul Mundt0b445dc2009-08-15 11:22:50 +0900185static inline void flush_dcache_all(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186{
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900187 (*__flush_dcache_segment_fn)(0UL, boot_cpu_data.dcache.way_size);
Paul Mundtfdfc74f2006-09-27 14:05:52 +0900188 wmb();
Paul Mundta2527102006-09-27 11:29:55 +0900189}
190
191void flush_cache_all(void)
192{
193 flush_dcache_all();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 flush_icache_all();
195}
196
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900197static void __flush_cache_mm(struct mm_struct *mm, unsigned long start,
198 unsigned long end)
199{
200 unsigned long d = 0, p = start & PAGE_MASK;
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900201 unsigned long alias_mask = boot_cpu_data.dcache.alias_mask;
202 unsigned long n_aliases = boot_cpu_data.dcache.n_aliases;
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900203 unsigned long select_bit;
204 unsigned long all_aliases_mask;
205 unsigned long addr_offset;
206 pgd_t *dir;
207 pmd_t *pmd;
208 pud_t *pud;
209 pte_t *pte;
210 int i;
211
212 dir = pgd_offset(mm, p);
213 pud = pud_offset(dir, p);
214 pmd = pmd_offset(pud, p);
215 end = PAGE_ALIGN(end);
216
217 all_aliases_mask = (1 << n_aliases) - 1;
218
219 do {
220 if (pmd_none(*pmd) || unlikely(pmd_bad(*pmd))) {
221 p &= PMD_MASK;
222 p += PMD_SIZE;
223 pmd++;
224
225 continue;
226 }
227
228 pte = pte_offset_kernel(pmd, p);
229
230 do {
231 unsigned long phys;
232 pte_t entry = *pte;
233
234 if (!(pte_val(entry) & _PAGE_PRESENT)) {
235 pte++;
236 p += PAGE_SIZE;
237 continue;
238 }
239
240 phys = pte_val(entry) & PTE_PHYS_MASK;
241
242 if ((p ^ phys) & alias_mask) {
243 d |= 1 << ((p & alias_mask) >> PAGE_SHIFT);
244 d |= 1 << ((phys & alias_mask) >> PAGE_SHIFT);
245
246 if (d == all_aliases_mask)
247 goto loop_exit;
248 }
249
250 pte++;
251 p += PAGE_SIZE;
252 } while (p < end && ((unsigned long)pte & ~PAGE_MASK));
253 pmd++;
254 } while (p < end);
255
256loop_exit:
257 addr_offset = 0;
258 select_bit = 1;
259
260 for (i = 0; i < n_aliases; i++) {
261 if (d & select_bit) {
262 (*__flush_dcache_segment_fn)(addr_offset, PAGE_SIZE);
263 wmb();
264 }
265
266 select_bit <<= 1;
267 addr_offset += PAGE_SIZE;
268 }
269}
270
271/*
272 * Note : (RPC) since the caches are physically tagged, the only point
273 * of flush_cache_mm for SH-4 is to get rid of aliases from the
274 * D-cache. The assumption elsewhere, e.g. flush_cache_range, is that
275 * lines can stay resident so long as the virtual address they were
276 * accessed with (hence cache set) is in accord with the physical
277 * address (i.e. tag). It's no different here. So I reckon we don't
278 * need to flush the I-cache, since aliases don't matter for that. We
279 * should try that.
280 *
281 * Caller takes mm->mmap_sem.
282 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283void flush_cache_mm(struct mm_struct *mm)
284{
Paul Mundte7b8b7f2009-08-15 02:21:16 +0900285 if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT)
286 return;
287
Richard Curnowb638d0b2006-09-27 14:09:26 +0900288 /*
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900289 * If cache is only 4k-per-way, there are never any 'aliases'. Since
290 * the cache is physically tagged, the data can just be left in there.
Richard Curnowb638d0b2006-09-27 14:09:26 +0900291 */
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900292 if (boot_cpu_data.dcache.n_aliases == 0)
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900293 return;
294
295 /*
296 * Don't bother groveling around the dcache for the VMA ranges
297 * if there are too many PTEs to make it worthwhile.
298 */
299 if (mm->nr_ptes >= MAX_DCACHE_PAGES)
300 flush_dcache_all();
301 else {
302 struct vm_area_struct *vma;
303
304 /*
305 * In this case there are reasonably sized ranges to flush,
306 * iterate through the VMA list and take care of any aliases.
307 */
308 for (vma = mm->mmap; vma; vma = vma->vm_next)
309 __flush_cache_mm(mm, vma->vm_start, vma->vm_end);
310 }
311
312 /* Only touch the icache if one of the VMAs has VM_EXEC set. */
313 if (mm->exec_vm)
314 flush_icache_all();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315}
316
317/*
318 * Write back and invalidate I/D-caches for the page.
319 *
320 * ADDR: Virtual Address (U0 address)
321 * PFN: Physical page number
322 */
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900323void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
324 unsigned long pfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325{
326 unsigned long phys = pfn << PAGE_SHIFT;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900327 unsigned int alias_mask;
328
Paul Mundte7b8b7f2009-08-15 02:21:16 +0900329 if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
330 return;
331
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900332 alias_mask = boot_cpu_data.dcache.alias_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333
334 /* We only need to flush D-cache when we have alias */
Richard Curnowb638d0b2006-09-27 14:09:26 +0900335 if ((address^phys) & alias_mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 /* Loop 4K of the D-cache */
337 flush_cache_4096(
Richard Curnowb638d0b2006-09-27 14:09:26 +0900338 CACHE_OC_ADDRESS_ARRAY | (address & alias_mask),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339 phys);
340 /* Loop another 4K of the D-cache */
341 flush_cache_4096(
Richard Curnowb638d0b2006-09-27 14:09:26 +0900342 CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 phys);
344 }
345
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900346 alias_mask = boot_cpu_data.icache.alias_mask;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900347 if (vma->vm_flags & VM_EXEC) {
348 /*
349 * Evict entries from the portion of the cache from which code
350 * may have been executed at this address (virtual). There's
351 * no need to evict from the portion corresponding to the
352 * physical address as for the D-cache, because we know the
353 * kernel has never executed the code through its identity
354 * translation.
355 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 flush_cache_4096(
Richard Curnowb638d0b2006-09-27 14:09:26 +0900357 CACHE_IC_ADDRESS_ARRAY | (address & alias_mask),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 phys);
Richard Curnowb638d0b2006-09-27 14:09:26 +0900359 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360}
361
362/*
363 * Write back and invalidate D-caches.
364 *
365 * START, END: Virtual Address (U0 address)
366 *
367 * NOTE: We need to flush the _physical_ page entry.
368 * Flushing the cache lines for U0 only isn't enough.
369 * We need to flush for P1 too, which may contain aliases.
370 */
371void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
372 unsigned long end)
373{
Paul Mundte7b8b7f2009-08-15 02:21:16 +0900374 if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
375 return;
376
Richard Curnowb638d0b2006-09-27 14:09:26 +0900377 /*
378 * If cache is only 4k-per-way, there are never any 'aliases'. Since
379 * the cache is physically tagged, the data can just be left in there.
380 */
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900381 if (boot_cpu_data.dcache.n_aliases == 0)
Richard Curnowb638d0b2006-09-27 14:09:26 +0900382 return;
383
Paul Mundta2527102006-09-27 11:29:55 +0900384 /*
385 * Don't bother with the lookup and alias check if we have a
386 * wide range to cover, just blow away the dcache in its
387 * entirety instead. -- PFM.
388 */
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900389 if (((end - start) >> PAGE_SHIFT) >= MAX_DCACHE_PAGES)
Paul Mundta2527102006-09-27 11:29:55 +0900390 flush_dcache_all();
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900391 else
392 __flush_cache_mm(vma->vm_mm, start, end);
Richard Curnowb638d0b2006-09-27 14:09:26 +0900393
394 if (vma->vm_flags & VM_EXEC) {
395 /*
396 * TODO: Is this required??? Need to look at how I-cache
397 * coherency is assured when new programs are loaded to see if
398 * this matters.
399 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 flush_icache_all();
Richard Curnowb638d0b2006-09-27 14:09:26 +0900401 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402}
403
404/*
405 * flush_icache_user_range
406 * @vma: VMA of the process
407 * @page: page
408 * @addr: U0 address
409 * @len: length of the range (< page size)
410 */
411void flush_icache_user_range(struct vm_area_struct *vma,
412 struct page *page, unsigned long addr, int len)
413{
414 flush_cache_page(vma, addr, page_to_pfn(page));
Paul Mundtfdfc74f2006-09-27 14:05:52 +0900415 mb();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416}
417
Richard Curnowb638d0b2006-09-27 14:09:26 +0900418/**
419 * __flush_cache_4096
420 *
421 * @addr: address in memory mapped cache array
422 * @phys: P1 address to flush (has to match tags if addr has 'A' bit
423 * set i.e. associative write)
424 * @exec_offset: set to 0x20000000 if flush has to be executed from P2
425 * region else 0x0
426 *
427 * The offset into the cache array implied by 'addr' selects the
428 * 'colour' of the virtual address range that will be flushed. The
429 * operation (purge/write-back) is selected by the lower 2 bits of
430 * 'phys'.
431 */
432static void __flush_cache_4096(unsigned long addr, unsigned long phys,
433 unsigned long exec_offset)
434{
435 int way_count;
436 unsigned long base_addr = addr;
437 struct cache_info *dcache;
438 unsigned long way_incr;
439 unsigned long a, ea, p;
440 unsigned long temp_pc;
441
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900442 dcache = &boot_cpu_data.dcache;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900443 /* Write this way for better assembly. */
444 way_count = dcache->ways;
445 way_incr = dcache->way_incr;
446
447 /*
448 * Apply exec_offset (i.e. branch to P2 if required.).
449 *
450 * FIXME:
451 *
452 * If I write "=r" for the (temp_pc), it puts this in r6 hence
453 * trashing exec_offset before it's been added on - why? Hence
454 * "=&r" as a 'workaround'
455 */
456 asm volatile("mov.l 1f, %0\n\t"
457 "add %1, %0\n\t"
458 "jmp @%0\n\t"
459 "nop\n\t"
460 ".balign 4\n\t"
461 "1: .long 2f\n\t"
462 "2:\n" : "=&r" (temp_pc) : "r" (exec_offset));
463
464 /*
465 * We know there will be >=1 iteration, so write as do-while to avoid
466 * pointless nead-of-loop check for 0 iterations.
467 */
468 do {
469 ea = base_addr + PAGE_SIZE;
470 a = base_addr;
471 p = phys;
472
473 do {
474 *(volatile unsigned long *)a = p;
475 /*
476 * Next line: intentionally not p+32, saves an add, p
477 * will do since only the cache tag bits need to
478 * match.
479 */
480 *(volatile unsigned long *)(a+32) = p;
481 a += 64;
482 p += 64;
483 } while (a < ea);
484
485 base_addr += way_incr;
486 } while (--way_count != 0);
487}
488
489/*
490 * Break the 1, 2 and 4 way variants of this out into separate functions to
491 * avoid nearly all the overhead of having the conditional stuff in the function
492 * bodies (+ the 1 and 2 way cases avoid saving any registers too).
493 */
494static void __flush_dcache_segment_1way(unsigned long start,
495 unsigned long extent_per_way)
496{
497 unsigned long orig_sr, sr_with_bl;
498 unsigned long base_addr;
499 unsigned long way_incr, linesz, way_size;
500 struct cache_info *dcache;
501 register unsigned long a0, a0e;
502
503 asm volatile("stc sr, %0" : "=r" (orig_sr));
504 sr_with_bl = orig_sr | (1<<28);
505 base_addr = ((unsigned long)&empty_zero_page[0]);
506
507 /*
508 * The previous code aligned base_addr to 16k, i.e. the way_size of all
509 * existing SH-4 D-caches. Whilst I don't see a need to have this
510 * aligned to any better than the cache line size (which it will be
511 * anyway by construction), let's align it to at least the way_size of
512 * any existing or conceivable SH-4 D-cache. -- RPC
513 */
514 base_addr = ((base_addr >> 16) << 16);
515 base_addr |= start;
516
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900517 dcache = &boot_cpu_data.dcache;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900518 linesz = dcache->linesz;
519 way_incr = dcache->way_incr;
520 way_size = dcache->way_size;
521
522 a0 = base_addr;
523 a0e = base_addr + extent_per_way;
524 do {
525 asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
526 asm volatile("movca.l r0, @%0\n\t"
527 "ocbi @%0" : : "r" (a0));
528 a0 += linesz;
529 asm volatile("movca.l r0, @%0\n\t"
530 "ocbi @%0" : : "r" (a0));
531 a0 += linesz;
532 asm volatile("movca.l r0, @%0\n\t"
533 "ocbi @%0" : : "r" (a0));
534 a0 += linesz;
535 asm volatile("movca.l r0, @%0\n\t"
536 "ocbi @%0" : : "r" (a0));
537 asm volatile("ldc %0, sr" : : "r" (orig_sr));
538 a0 += linesz;
539 } while (a0 < a0e);
540}
541
542static void __flush_dcache_segment_2way(unsigned long start,
543 unsigned long extent_per_way)
544{
545 unsigned long orig_sr, sr_with_bl;
546 unsigned long base_addr;
547 unsigned long way_incr, linesz, way_size;
548 struct cache_info *dcache;
549 register unsigned long a0, a1, a0e;
550
551 asm volatile("stc sr, %0" : "=r" (orig_sr));
552 sr_with_bl = orig_sr | (1<<28);
553 base_addr = ((unsigned long)&empty_zero_page[0]);
554
555 /* See comment under 1-way above */
556 base_addr = ((base_addr >> 16) << 16);
557 base_addr |= start;
558
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900559 dcache = &boot_cpu_data.dcache;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900560 linesz = dcache->linesz;
561 way_incr = dcache->way_incr;
562 way_size = dcache->way_size;
563
564 a0 = base_addr;
565 a1 = a0 + way_incr;
566 a0e = base_addr + extent_per_way;
567 do {
568 asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
569 asm volatile("movca.l r0, @%0\n\t"
570 "movca.l r0, @%1\n\t"
571 "ocbi @%0\n\t"
572 "ocbi @%1" : :
573 "r" (a0), "r" (a1));
574 a0 += linesz;
575 a1 += linesz;
576 asm volatile("movca.l r0, @%0\n\t"
577 "movca.l r0, @%1\n\t"
578 "ocbi @%0\n\t"
579 "ocbi @%1" : :
580 "r" (a0), "r" (a1));
581 a0 += linesz;
582 a1 += linesz;
583 asm volatile("movca.l r0, @%0\n\t"
584 "movca.l r0, @%1\n\t"
585 "ocbi @%0\n\t"
586 "ocbi @%1" : :
587 "r" (a0), "r" (a1));
588 a0 += linesz;
589 a1 += linesz;
590 asm volatile("movca.l r0, @%0\n\t"
591 "movca.l r0, @%1\n\t"
592 "ocbi @%0\n\t"
593 "ocbi @%1" : :
594 "r" (a0), "r" (a1));
595 asm volatile("ldc %0, sr" : : "r" (orig_sr));
596 a0 += linesz;
597 a1 += linesz;
598 } while (a0 < a0e);
599}
600
601static void __flush_dcache_segment_4way(unsigned long start,
602 unsigned long extent_per_way)
603{
604 unsigned long orig_sr, sr_with_bl;
605 unsigned long base_addr;
606 unsigned long way_incr, linesz, way_size;
607 struct cache_info *dcache;
608 register unsigned long a0, a1, a2, a3, a0e;
609
610 asm volatile("stc sr, %0" : "=r" (orig_sr));
611 sr_with_bl = orig_sr | (1<<28);
612 base_addr = ((unsigned long)&empty_zero_page[0]);
613
614 /* See comment under 1-way above */
615 base_addr = ((base_addr >> 16) << 16);
616 base_addr |= start;
617
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900618 dcache = &boot_cpu_data.dcache;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900619 linesz = dcache->linesz;
620 way_incr = dcache->way_incr;
621 way_size = dcache->way_size;
622
623 a0 = base_addr;
624 a1 = a0 + way_incr;
625 a2 = a1 + way_incr;
626 a3 = a2 + way_incr;
627 a0e = base_addr + extent_per_way;
628 do {
629 asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
630 asm volatile("movca.l r0, @%0\n\t"
631 "movca.l r0, @%1\n\t"
632 "movca.l r0, @%2\n\t"
633 "movca.l r0, @%3\n\t"
634 "ocbi @%0\n\t"
635 "ocbi @%1\n\t"
636 "ocbi @%2\n\t"
637 "ocbi @%3\n\t" : :
638 "r" (a0), "r" (a1), "r" (a2), "r" (a3));
639 a0 += linesz;
640 a1 += linesz;
641 a2 += linesz;
642 a3 += linesz;
643 asm volatile("movca.l r0, @%0\n\t"
644 "movca.l r0, @%1\n\t"
645 "movca.l r0, @%2\n\t"
646 "movca.l r0, @%3\n\t"
647 "ocbi @%0\n\t"
648 "ocbi @%1\n\t"
649 "ocbi @%2\n\t"
650 "ocbi @%3\n\t" : :
651 "r" (a0), "r" (a1), "r" (a2), "r" (a3));
652 a0 += linesz;
653 a1 += linesz;
654 a2 += linesz;
655 a3 += linesz;
656 asm volatile("movca.l r0, @%0\n\t"
657 "movca.l r0, @%1\n\t"
658 "movca.l r0, @%2\n\t"
659 "movca.l r0, @%3\n\t"
660 "ocbi @%0\n\t"
661 "ocbi @%1\n\t"
662 "ocbi @%2\n\t"
663 "ocbi @%3\n\t" : :
664 "r" (a0), "r" (a1), "r" (a2), "r" (a3));
665 a0 += linesz;
666 a1 += linesz;
667 a2 += linesz;
668 a3 += linesz;
669 asm volatile("movca.l r0, @%0\n\t"
670 "movca.l r0, @%1\n\t"
671 "movca.l r0, @%2\n\t"
672 "movca.l r0, @%3\n\t"
673 "ocbi @%0\n\t"
674 "ocbi @%1\n\t"
675 "ocbi @%2\n\t"
676 "ocbi @%3\n\t" : :
677 "r" (a0), "r" (a1), "r" (a2), "r" (a3));
678 asm volatile("ldc %0, sr" : : "r" (orig_sr));
679 a0 += linesz;
680 a1 += linesz;
681 a2 += linesz;
682 a3 += linesz;
683 } while (a0 < a0e);
684}