blob: c6097bcd97fd4a5b1799024c7ee881534bd93bad [file] [log] [blame]
Jamie Lenehana09749d2006-09-27 15:05:39 +09001/*
2 * arch/sh/drivers/pci/ops-titan.c
3 *
4 * Ported to new API by Paul Mundt <lethal@linux-sh.org>
5 *
6 * Modified from ops-snapgear.c written by David McCullough
7 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
8 *
9 * May be copied or modified under the terms of the GNU General Public
10 * License. See linux/COPYING for more information.
11 *
12 * PCI initialization for the Titan boards
13 */
14
15#include <linux/config.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/init.h>
Paul Mundt0f08f332006-09-27 17:03:56 +090019#include <linux/pci.h>
Jamie Lenehana09749d2006-09-27 15:05:39 +090020#include <asm/io.h>
21#include <asm/titan.h>
Paul Mundt959f85f2006-09-27 16:43:28 +090022#include "pci-sh4.h"
Jamie Lenehana09749d2006-09-27 15:05:39 +090023
Paul Mundt959f85f2006-09-27 16:43:28 +090024int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
Jamie Lenehana09749d2006-09-27 15:05:39 +090025{
26 int irq = -1;
27
28 switch (slot) {
29 case 0: irq = TITAN_IRQ_WAN; break; /* eth0 (WAN) */
30 case 1: irq = TITAN_IRQ_LAN; break; /* eth1 (LAN) */
31 case 2: irq = TITAN_IRQ_MPCIA; break; /* mPCI A */
32 case 3: irq = TITAN_IRQ_MPCIB; break; /* mPCI B */
33 case 4: irq = TITAN_IRQ_USB; break; /* USB */
34 default:
Paul Mundt959f85f2006-09-27 16:43:28 +090035 printk(KERN_INFO "PCI: Bad IRQ mapping "
36 "request for slot %d\n", slot);
Jamie Lenehana09749d2006-09-27 15:05:39 +090037 return -1;
38 }
39
40 printk("PCI: Mapping TITAN IRQ for slot %d, pin %c to irq %d\n",
41 slot, pin - 1 + 'A', irq);
42
43 return irq;
44}
45
46static struct resource sh7751_io_resource = {
47 .name = "SH7751_IO",
48 .start = SH7751_PCI_IO_BASE,
49 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
50 .flags = IORESOURCE_IO
51};
52
53static struct resource sh7751_mem_resource = {
54 .name = "SH7751_mem",
55 .start = SH7751_PCI_MEMORY_BASE,
56 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
57 .flags = IORESOURCE_MEM
58};
59
Jamie Lenehana09749d2006-09-27 15:05:39 +090060struct pci_channel board_pci_channels[] = {
Paul Mundt959f85f2006-09-27 16:43:28 +090061 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
Jamie Lenehana09749d2006-09-27 15:05:39 +090062 { NULL, NULL, NULL, 0, 0 },
63};
64EXPORT_SYMBOL(board_pci_channels);
65
Paul Mundt959f85f2006-09-27 16:43:28 +090066static struct sh4_pci_address_map sh7751_pci_map = {
Jamie Lenehana09749d2006-09-27 15:05:39 +090067 .window0 = {
68 .base = SH7751_CS2_BASE_ADDR,
69 .size = SH7751_MEM_REGION_SIZE*2, /* cs2 and cs3 */
70 },
71
72 .window1 = {
73 .base = SH7751_CS2_BASE_ADDR,
74 .size = SH7751_MEM_REGION_SIZE*2,
75 },
76
Paul Mundt959f85f2006-09-27 16:43:28 +090077 .flags = SH4_PCIC_NO_RESET,
Jamie Lenehana09749d2006-09-27 15:05:39 +090078};
79
80int __init pcibios_init_platform(void)
81{
82 return sh7751_pcic_init(&sh7751_pci_map);
83}