Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1 | /* |
Sujith Manoharan | 5b68138 | 2011-05-17 13:36:18 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 18 | #include <linux/slab.h> |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 19 | #include <asm/unaligned.h> |
| 20 | |
Luis R. Rodriguez | af03abe | 2009-09-09 02:33:11 -0700 | [diff] [blame] | 21 | #include "hw.h" |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 22 | #include "hw-ops.h" |
Luis R. Rodriguez | cfe8cba | 2009-09-13 23:39:31 -0700 | [diff] [blame] | 23 | #include "rc.h" |
Luis R. Rodriguez | b622a72 | 2010-04-15 17:39:28 -0400 | [diff] [blame] | 24 | #include "ar9003_mac.h" |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 25 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 26 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 27 | |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 28 | MODULE_AUTHOR("Atheros Communications"); |
| 29 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); |
| 30 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); |
| 31 | MODULE_LICENSE("Dual BSD/GPL"); |
| 32 | |
| 33 | static int __init ath9k_init(void) |
| 34 | { |
| 35 | return 0; |
| 36 | } |
| 37 | module_init(ath9k_init); |
| 38 | |
| 39 | static void __exit ath9k_exit(void) |
| 40 | { |
| 41 | return; |
| 42 | } |
| 43 | module_exit(ath9k_exit); |
| 44 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 45 | /* Private hardware callbacks */ |
| 46 | |
| 47 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) |
| 48 | { |
| 49 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); |
| 50 | } |
| 51 | |
| 52 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) |
| 53 | { |
| 54 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); |
| 55 | } |
| 56 | |
Luis R. Rodriguez | 6477396 | 2010-04-15 17:38:17 -0400 | [diff] [blame] | 57 | static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, |
| 58 | struct ath9k_channel *chan) |
| 59 | { |
| 60 | return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); |
| 61 | } |
| 62 | |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 63 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 64 | { |
| 65 | if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) |
| 66 | return; |
| 67 | |
| 68 | ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); |
| 69 | } |
| 70 | |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 71 | static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) |
| 72 | { |
| 73 | /* You will not have this callback if using the old ANI */ |
| 74 | if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) |
| 75 | return; |
| 76 | |
| 77 | ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); |
| 78 | } |
| 79 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 80 | /********************/ |
| 81 | /* Helper Functions */ |
| 82 | /********************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 83 | |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 84 | static void ath9k_hw_set_clockrate(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 85 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 86 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 87 | struct ath_common *common = ath9k_hw_common(ah); |
| 88 | unsigned int clockrate; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 89 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 90 | if (!ah->curchan) /* should really check for CCK instead */ |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 91 | clockrate = ATH9K_CLOCK_RATE_CCK; |
| 92 | else if (conf->channel->band == IEEE80211_BAND_2GHZ) |
| 93 | clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; |
| 94 | else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) |
| 95 | clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; |
Vasanthakumar Thiagarajan | e555372 | 2010-04-26 15:04:33 -0400 | [diff] [blame] | 96 | else |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 97 | clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; |
| 98 | |
| 99 | if (conf_is_ht40(conf)) |
| 100 | clockrate *= 2; |
| 101 | |
| 102 | common->clockrate = clockrate; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 103 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 104 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 105 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 106 | { |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 107 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 108 | |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 109 | return usecs * common->clockrate; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 110 | } |
| 111 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 112 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 113 | { |
| 114 | int i; |
| 115 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 116 | BUG_ON(timeout < AH_TIME_QUANTUM); |
| 117 | |
| 118 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 119 | if ((REG_READ(ah, reg) & mask) == val) |
| 120 | return true; |
| 121 | |
| 122 | udelay(AH_TIME_QUANTUM); |
| 123 | } |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 124 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 125 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, |
| 126 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
| 127 | timeout, reg, REG_READ(ah, reg), mask, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 128 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 129 | return false; |
| 130 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 131 | EXPORT_SYMBOL(ath9k_hw_wait); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 132 | |
Felix Fietkau | a9b6b25 | 2011-03-23 20:57:27 +0100 | [diff] [blame] | 133 | void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, |
| 134 | int column, unsigned int *writecnt) |
| 135 | { |
| 136 | int r; |
| 137 | |
| 138 | ENABLE_REGWRITE_BUFFER(ah); |
| 139 | for (r = 0; r < array->ia_rows; r++) { |
| 140 | REG_WRITE(ah, INI_RA(array, r, 0), |
| 141 | INI_RA(array, r, column)); |
| 142 | DO_DELAY(*writecnt); |
| 143 | } |
| 144 | REGWRITE_BUFFER_FLUSH(ah); |
| 145 | } |
| 146 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 147 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) |
| 148 | { |
| 149 | u32 retval; |
| 150 | int i; |
| 151 | |
| 152 | for (i = 0, retval = 0; i < n; i++) { |
| 153 | retval = (retval << 1) | (val & 1); |
| 154 | val >>= 1; |
| 155 | } |
| 156 | return retval; |
| 157 | } |
| 158 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 159 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 160 | u8 phy, int kbps, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 161 | u32 frameLen, u16 rateix, |
| 162 | bool shortPreamble) |
| 163 | { |
| 164 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 165 | |
| 166 | if (kbps == 0) |
| 167 | return 0; |
| 168 | |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 169 | switch (phy) { |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 170 | case WLAN_RC_PHY_CCK: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 171 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 172 | if (shortPreamble) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 173 | phyTime >>= 1; |
| 174 | numBits = frameLen << 3; |
| 175 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); |
| 176 | break; |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 177 | case WLAN_RC_PHY_OFDM: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 178 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 179 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
| 180 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 181 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 182 | txTime = OFDM_SIFS_TIME_QUARTER |
| 183 | + OFDM_PREAMBLE_TIME_QUARTER |
| 184 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 185 | } else if (ah->curchan && |
| 186 | IS_CHAN_HALF_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 187 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
| 188 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 189 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 190 | txTime = OFDM_SIFS_TIME_HALF + |
| 191 | OFDM_PREAMBLE_TIME_HALF |
| 192 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); |
| 193 | } else { |
| 194 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; |
| 195 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 196 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 197 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME |
| 198 | + (numSymbols * OFDM_SYMBOL_TIME); |
| 199 | } |
| 200 | break; |
| 201 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 202 | ath_err(ath9k_hw_common(ah), |
| 203 | "Unknown phy %u (rate ix %u)\n", phy, rateix); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 204 | txTime = 0; |
| 205 | break; |
| 206 | } |
| 207 | |
| 208 | return txTime; |
| 209 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 210 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 211 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 212 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 213 | struct ath9k_channel *chan, |
| 214 | struct chan_centers *centers) |
| 215 | { |
| 216 | int8_t extoff; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 217 | |
| 218 | if (!IS_CHAN_HT40(chan)) { |
| 219 | centers->ctl_center = centers->ext_center = |
| 220 | centers->synth_center = chan->channel; |
| 221 | return; |
| 222 | } |
| 223 | |
| 224 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
| 225 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { |
| 226 | centers->synth_center = |
| 227 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; |
| 228 | extoff = 1; |
| 229 | } else { |
| 230 | centers->synth_center = |
| 231 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; |
| 232 | extoff = -1; |
| 233 | } |
| 234 | |
| 235 | centers->ctl_center = |
| 236 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 237 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 238 | centers->ext_center = |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 239 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 240 | } |
| 241 | |
| 242 | /******************/ |
| 243 | /* Chip Revisions */ |
| 244 | /******************/ |
| 245 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 246 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 247 | { |
| 248 | u32 val; |
| 249 | |
Vasanthakumar Thiagarajan | ecb1d38 | 2011-04-19 19:29:18 +0530 | [diff] [blame] | 250 | switch (ah->hw_version.devid) { |
| 251 | case AR5416_AR9100_DEVID: |
| 252 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; |
| 253 | break; |
| 254 | case AR9300_DEVID_AR9340: |
| 255 | ah->hw_version.macVersion = AR_SREV_VERSION_9340; |
| 256 | val = REG_READ(ah, AR_SREV); |
| 257 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); |
| 258 | return; |
| 259 | } |
| 260 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 261 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
| 262 | |
| 263 | if (val == 0xFF) { |
| 264 | val = REG_READ(ah, AR_SREV); |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 265 | ah->hw_version.macVersion = |
| 266 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; |
| 267 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 268 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 269 | } else { |
| 270 | if (!AR_SREV_9100(ah)) |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 271 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 272 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 273 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 274 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 275 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 276 | ah->is_pciexpress = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 277 | } |
| 278 | } |
| 279 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 280 | /************************************/ |
| 281 | /* HW Attach, Detach, Init Routines */ |
| 282 | /************************************/ |
| 283 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 284 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 285 | { |
Felix Fietkau | 040b74f | 2010-12-12 00:51:07 +0100 | [diff] [blame] | 286 | if (!AR_SREV_5416(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 287 | return; |
| 288 | |
| 289 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 290 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 291 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); |
| 292 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); |
| 293 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); |
| 294 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); |
| 295 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 296 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 297 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); |
| 298 | |
| 299 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
| 300 | } |
| 301 | |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 302 | /* This should work for all families including legacy */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 303 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 304 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 305 | struct ath_common *common = ath9k_hw_common(ah); |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 306 | u32 regAddr[2] = { AR_STA_ID0 }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 307 | u32 regHold[2]; |
Joe Perches | 07b2fa5 | 2010-11-20 18:38:53 -0800 | [diff] [blame] | 308 | static const u32 patternData[4] = { |
| 309 | 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 |
| 310 | }; |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 311 | int i, j, loop_max; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 312 | |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 313 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 314 | loop_max = 2; |
| 315 | regAddr[1] = AR_PHY_BASE + (8 << 2); |
| 316 | } else |
| 317 | loop_max = 1; |
| 318 | |
| 319 | for (i = 0; i < loop_max; i++) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 320 | u32 addr = regAddr[i]; |
| 321 | u32 wrData, rdData; |
| 322 | |
| 323 | regHold[i] = REG_READ(ah, addr); |
| 324 | for (j = 0; j < 0x100; j++) { |
| 325 | wrData = (j << 16) | j; |
| 326 | REG_WRITE(ah, addr, wrData); |
| 327 | rdData = REG_READ(ah, addr); |
| 328 | if (rdData != wrData) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 329 | ath_err(common, |
| 330 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", |
| 331 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 332 | return false; |
| 333 | } |
| 334 | } |
| 335 | for (j = 0; j < 4; j++) { |
| 336 | wrData = patternData[j]; |
| 337 | REG_WRITE(ah, addr, wrData); |
| 338 | rdData = REG_READ(ah, addr); |
| 339 | if (wrData != rdData) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 340 | ath_err(common, |
| 341 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", |
| 342 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 343 | return false; |
| 344 | } |
| 345 | } |
| 346 | REG_WRITE(ah, regAddr[i], regHold[i]); |
| 347 | } |
| 348 | udelay(100); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 349 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 350 | return true; |
| 351 | } |
| 352 | |
Luis R. Rodriguez | b8b0f37 | 2009-08-03 12:24:43 -0700 | [diff] [blame] | 353 | static void ath9k_hw_init_config(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 354 | { |
| 355 | int i; |
| 356 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 357 | ah->config.dma_beacon_response_time = 2; |
| 358 | ah->config.sw_beacon_response_time = 10; |
| 359 | ah->config.additional_swba_backoff = 0; |
| 360 | ah->config.ack_6mb = 0x0; |
| 361 | ah->config.cwm_ignore_extcca = 0; |
| 362 | ah->config.pcie_powersave_enable = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 363 | ah->config.pcie_clock_req = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 364 | ah->config.pcie_waen = 0; |
| 365 | ah->config.analog_shiftreg = 1; |
Luis R. Rodriguez | 03c7251 | 2010-06-12 00:33:46 -0400 | [diff] [blame] | 366 | ah->config.enable_ani = true; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 367 | |
| 368 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 369 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
| 370 | ah->config.spurchans[i][1] = AR_NO_SPUR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 371 | } |
| 372 | |
Luis R. Rodriguez | 6f48101 | 2011-01-20 17:47:39 -0800 | [diff] [blame] | 373 | /* PAPRD needs some more work to be enabled */ |
| 374 | ah->config.paprd_disable = 1; |
| 375 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 376 | ah->config.rx_intr_mitigation = true; |
Luis R. Rodriguez | 6a0ec30 | 2010-06-21 18:38:49 -0400 | [diff] [blame] | 377 | ah->config.pcieSerDesWrite = true; |
Luis R. Rodriguez | 6158425 | 2009-03-12 18:18:49 -0400 | [diff] [blame] | 378 | |
| 379 | /* |
| 380 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) |
| 381 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). |
| 382 | * This means we use it for all AR5416 devices, and the few |
| 383 | * minor PCI AR9280 devices out there. |
| 384 | * |
| 385 | * Serialization is required because these devices do not handle |
| 386 | * well the case of two concurrent reads/writes due to the latency |
| 387 | * involved. During one read/write another read/write can be issued |
| 388 | * on another CPU while the previous read/write may still be working |
| 389 | * on our hardware, if we hit this case the hardware poops in a loop. |
| 390 | * We prevent this by serializing reads and writes. |
| 391 | * |
| 392 | * This issue is not present on PCI-Express devices or pre-AR5416 |
| 393 | * devices (legacy, 802.11abg). |
| 394 | */ |
| 395 | if (num_possible_cpus() > 1) |
David S. Miller | 2d6a5e9 | 2009-03-17 15:01:30 -0700 | [diff] [blame] | 396 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 397 | } |
| 398 | |
Luis R. Rodriguez | 50aca25 | 2009-08-03 12:24:42 -0700 | [diff] [blame] | 399 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 400 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 401 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 402 | |
| 403 | regulatory->country_code = CTRY_DEFAULT; |
| 404 | regulatory->power_limit = MAX_RATE_POWER; |
| 405 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; |
| 406 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 407 | ah->hw_version.magic = AR5416_MAGIC; |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 408 | ah->hw_version.subvendorid = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 409 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 410 | ah->atim_window = 0; |
Felix Fietkau | 16f2411 | 2010-06-12 17:22:32 +0200 | [diff] [blame] | 411 | ah->sta_id1_defaults = |
| 412 | AR_STA_ID1_CRPT_MIC_ENABLE | |
| 413 | AR_STA_ID1_MCAST_KSRCH; |
Felix Fietkau | f171760 | 2011-03-19 13:55:41 +0100 | [diff] [blame] | 414 | if (AR_SREV_9100(ah)) |
| 415 | ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 416 | ah->enable_32kHz_clock = DONT_USE_32KHZ; |
Felix Fietkau | 4357c6b | 2010-12-13 08:40:50 +0100 | [diff] [blame] | 417 | ah->slottime = 20; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 418 | ah->globaltxtimeout = (u32) -1; |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 419 | ah->power_mode = ATH9K_PM_UNDEFINED; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 420 | } |
| 421 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 422 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 423 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 424 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 425 | u32 sum; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 426 | int i; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 427 | u16 eeval; |
Joe Perches | 07b2fa5 | 2010-11-20 18:38:53 -0800 | [diff] [blame] | 428 | static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 429 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 430 | sum = 0; |
| 431 | for (i = 0; i < 3; i++) { |
Luis R. Rodriguez | 4910167 | 2010-04-15 17:39:13 -0400 | [diff] [blame] | 432 | eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 433 | sum += eeval; |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 434 | common->macaddr[2 * i] = eeval >> 8; |
| 435 | common->macaddr[2 * i + 1] = eeval & 0xff; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 436 | } |
Sujith | d8baa93 | 2009-03-30 15:28:25 +0530 | [diff] [blame] | 437 | if (sum == 0 || sum == 0xffff * 3) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 438 | return -EADDRNOTAVAIL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 439 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 440 | return 0; |
| 441 | } |
| 442 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 443 | static int ath9k_hw_post_init(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 444 | { |
Sujith Manoharan | 6cae913 | 2011-01-04 13:16:37 +0530 | [diff] [blame] | 445 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 446 | int ecode; |
| 447 | |
Sujith Manoharan | 6cae913 | 2011-01-04 13:16:37 +0530 | [diff] [blame] | 448 | if (common->bus_ops->ath_bus_type != ATH_USB) { |
Sujith | 527d485 | 2010-03-17 14:25:16 +0530 | [diff] [blame] | 449 | if (!ath9k_hw_chip_test(ah)) |
| 450 | return -ENODEV; |
| 451 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 452 | |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 453 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 454 | ecode = ar9002_hw_rf_claim(ah); |
| 455 | if (ecode != 0) |
| 456 | return ecode; |
| 457 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 458 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 459 | ecode = ath9k_hw_eeprom_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 460 | if (ecode != 0) |
| 461 | return ecode; |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 462 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 463 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
| 464 | "Eeprom VER: %d, REV: %d\n", |
| 465 | ah->eep_ops->get_eeprom_ver(ah), |
| 466 | ah->eep_ops->get_eeprom_rev(ah)); |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 467 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 468 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
| 469 | if (ecode) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 470 | ath_err(ath9k_hw_common(ah), |
| 471 | "Failed allocating banks for external radio\n"); |
Rajkumar Manoharan | 48a7c3d | 2010-11-08 20:40:53 +0530 | [diff] [blame] | 472 | ath9k_hw_rf_free_ext_banks(ah); |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 473 | return ecode; |
Luis R. Rodriguez | 574d6b1 | 2009-10-19 02:33:37 -0400 | [diff] [blame] | 474 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 475 | |
Vasanthakumar Thiagarajan | 070c4d5 | 2011-04-19 19:29:05 +0530 | [diff] [blame] | 476 | if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 477 | ath9k_hw_ani_setup(ah); |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 478 | ath9k_hw_ani_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 479 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 480 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 481 | return 0; |
| 482 | } |
| 483 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 484 | static void ath9k_hw_attach_ops(struct ath_hw *ah) |
Luis R. Rodriguez | ee2bb46 | 2009-08-03 12:24:39 -0700 | [diff] [blame] | 485 | { |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 486 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 487 | ar9003_hw_attach_ops(ah); |
| 488 | else |
| 489 | ar9002_hw_attach_ops(ah); |
Luis R. Rodriguez | ee2bb46 | 2009-08-03 12:24:39 -0700 | [diff] [blame] | 490 | } |
| 491 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 492 | /* Called for all hardware families */ |
| 493 | static int __ath9k_hw_init(struct ath_hw *ah) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 494 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 495 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 496 | int r = 0; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 497 | |
Senthil Balasubramanian | ac45c12 | 2010-12-22 21:14:20 +0530 | [diff] [blame] | 498 | ath9k_hw_read_revisions(ah); |
| 499 | |
Senthil Balasubramanian | 0a8d7cb | 2010-12-22 19:17:18 +0530 | [diff] [blame] | 500 | /* |
| 501 | * Read back AR_WA into a permanent copy and set bits 14 and 17. |
| 502 | * We need to do this to avoid RMW of this register. We cannot |
| 503 | * read the reg when chip is asleep. |
| 504 | */ |
| 505 | ah->WARegVal = REG_READ(ah, AR_WA); |
| 506 | ah->WARegVal |= (AR_WA_D3_L1_DISABLE | |
| 507 | AR_WA_ASPM_TIMER_BASED_DISABLE); |
| 508 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 509 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 510 | ath_err(common, "Couldn't reset chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 511 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 512 | } |
| 513 | |
Luis R. Rodriguez | bab1f62 | 2010-04-15 17:38:20 -0400 | [diff] [blame] | 514 | ath9k_hw_init_defaults(ah); |
| 515 | ath9k_hw_init_config(ah); |
| 516 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 517 | ath9k_hw_attach_ops(ah); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 518 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 519 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 520 | ath_err(common, "Couldn't wakeup chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 521 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 522 | } |
| 523 | |
| 524 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { |
| 525 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || |
John W. Linville | 4c85ab1 | 2010-07-28 10:06:35 -0400 | [diff] [blame] | 526 | ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && |
| 527 | !ah->is_pciexpress)) { |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 528 | ah->config.serialize_regmode = |
| 529 | SER_REG_MODE_ON; |
| 530 | } else { |
| 531 | ah->config.serialize_regmode = |
| 532 | SER_REG_MODE_OFF; |
| 533 | } |
| 534 | } |
| 535 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 536 | ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 537 | ah->config.serialize_regmode); |
| 538 | |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 539 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 540 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; |
| 541 | else |
| 542 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; |
| 543 | |
Felix Fietkau | 6da5a72 | 2010-12-12 00:51:12 +0100 | [diff] [blame] | 544 | switch (ah->hw_version.macVersion) { |
| 545 | case AR_SREV_VERSION_5416_PCI: |
| 546 | case AR_SREV_VERSION_5416_PCIE: |
| 547 | case AR_SREV_VERSION_9160: |
| 548 | case AR_SREV_VERSION_9100: |
| 549 | case AR_SREV_VERSION_9280: |
| 550 | case AR_SREV_VERSION_9285: |
| 551 | case AR_SREV_VERSION_9287: |
| 552 | case AR_SREV_VERSION_9271: |
| 553 | case AR_SREV_VERSION_9300: |
| 554 | case AR_SREV_VERSION_9485: |
Vasanthakumar Thiagarajan | bca0468 | 2011-04-19 19:29:20 +0530 | [diff] [blame] | 555 | case AR_SREV_VERSION_9340: |
Felix Fietkau | 6da5a72 | 2010-12-12 00:51:12 +0100 | [diff] [blame] | 556 | break; |
| 557 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 558 | ath_err(common, |
| 559 | "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", |
| 560 | ah->hw_version.macVersion, ah->hw_version.macRev); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 561 | return -EOPNOTSUPP; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 562 | } |
| 563 | |
Vasanthakumar Thiagarajan | b99a7be | 2011-04-19 19:28:59 +0530 | [diff] [blame] | 564 | if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah)) |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 565 | ah->is_pciexpress = false; |
| 566 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 567 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 568 | ath9k_hw_init_cal_settings(ah); |
| 569 | |
| 570 | ah->ani_function = ATH9K_ANI_ALL; |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 571 | if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 572 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 573 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 574 | ah->ani_function &= ~ATH9K_ANI_MRC_CCK; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 575 | |
| 576 | ath9k_hw_init_mode_regs(ah); |
| 577 | |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 578 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 579 | if (ah->is_pciexpress) |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 580 | ath9k_hw_configpcipowersave(ah, 0, 0); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 581 | else |
| 582 | ath9k_hw_disablepcie(ah); |
| 583 | |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 584 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 585 | ar9002_hw_cck_chan14_spread(ah); |
Sujith | 193cd45 | 2009-09-18 15:04:07 +0530 | [diff] [blame] | 586 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 587 | r = ath9k_hw_post_init(ah); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 588 | if (r) |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 589 | return r; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 590 | |
| 591 | ath9k_hw_init_mode_gain_regs(ah); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 592 | r = ath9k_hw_fill_cap_info(ah); |
| 593 | if (r) |
| 594 | return r; |
| 595 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 596 | r = ath9k_hw_init_macaddr(ah); |
| 597 | if (r) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 598 | ath_err(common, "Failed to initialize MAC address\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 599 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 600 | } |
| 601 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 602 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 603 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 604 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 605 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 606 | |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 607 | ah->bb_watchdog_timeout_ms = 25; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 608 | |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 609 | common->state = ATH_HW_INITIALIZED; |
| 610 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 611 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 612 | } |
| 613 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 614 | int ath9k_hw_init(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 615 | { |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 616 | int ret; |
| 617 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 618 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 619 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ |
| 620 | switch (ah->hw_version.devid) { |
| 621 | case AR5416_DEVID_PCI: |
| 622 | case AR5416_DEVID_PCIE: |
| 623 | case AR5416_AR9100_DEVID: |
| 624 | case AR9160_DEVID_PCI: |
| 625 | case AR9280_DEVID_PCI: |
| 626 | case AR9280_DEVID_PCIE: |
| 627 | case AR9285_DEVID_PCIE: |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 628 | case AR9287_DEVID_PCI: |
| 629 | case AR9287_DEVID_PCIE: |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 630 | case AR2427_DEVID_PCIE: |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 631 | case AR9300_DEVID_PCIE: |
Vasanthakumar Thiagarajan | 3050c91 | 2010-12-06 04:27:36 -0800 | [diff] [blame] | 632 | case AR9300_DEVID_AR9485_PCIE: |
Vasanthakumar Thiagarajan | bca0468 | 2011-04-19 19:29:20 +0530 | [diff] [blame] | 633 | case AR9300_DEVID_AR9340: |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 634 | break; |
| 635 | default: |
| 636 | if (common->bus_ops->ath_bus_type == ATH_USB) |
| 637 | break; |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 638 | ath_err(common, "Hardware device ID 0x%04x not supported\n", |
| 639 | ah->hw_version.devid); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 640 | return -EOPNOTSUPP; |
| 641 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 642 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 643 | ret = __ath9k_hw_init(ah); |
| 644 | if (ret) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 645 | ath_err(common, |
| 646 | "Unable to initialize hardware; initialization status: %d\n", |
| 647 | ret); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 648 | return ret; |
| 649 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 650 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 651 | return 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 652 | } |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 653 | EXPORT_SYMBOL(ath9k_hw_init); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 654 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 655 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 656 | { |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 657 | ENABLE_REGWRITE_BUFFER(ah); |
| 658 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 659 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
| 660 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); |
| 661 | |
| 662 | REG_WRITE(ah, AR_QOS_NO_ACK, |
| 663 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | |
| 664 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | |
| 665 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); |
| 666 | |
| 667 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); |
| 668 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); |
| 669 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); |
| 670 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); |
| 671 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 672 | |
| 673 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 674 | } |
| 675 | |
Senthil Balasubramanian | b84628e | 2011-04-22 11:32:12 +0530 | [diff] [blame] | 676 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) |
Vivek Natarajan | b141581 | 2011-01-27 14:45:07 +0530 | [diff] [blame] | 677 | { |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 678 | REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); |
| 679 | udelay(100); |
| 680 | REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); |
| 681 | |
| 682 | while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) |
Vivek Natarajan | b141581 | 2011-01-27 14:45:07 +0530 | [diff] [blame] | 683 | udelay(100); |
Vivek Natarajan | b141581 | 2011-01-27 14:45:07 +0530 | [diff] [blame] | 684 | |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 685 | return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; |
Vivek Natarajan | b141581 | 2011-01-27 14:45:07 +0530 | [diff] [blame] | 686 | } |
| 687 | EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); |
| 688 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 689 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 690 | struct ath9k_channel *chan) |
| 691 | { |
Vasanthakumar Thiagarajan | d09b17f | 2010-12-06 04:27:44 -0800 | [diff] [blame] | 692 | u32 pll; |
| 693 | |
Vivek Natarajan | 22983c3 | 2011-01-27 14:45:09 +0530 | [diff] [blame] | 694 | if (AR_SREV_9485(ah)) { |
Vivek Natarajan | 22983c3 | 2011-01-27 14:45:09 +0530 | [diff] [blame] | 695 | |
Vasanthakumar Thiagarajan | 3dfd7f6 | 2011-04-11 16:39:40 +0530 | [diff] [blame] | 696 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ |
| 697 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
| 698 | AR_CH0_BB_DPLL2_PLL_PWD, 0x1); |
| 699 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
| 700 | AR_CH0_DPLL2_KD, 0x40); |
| 701 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
| 702 | AR_CH0_DPLL2_KI, 0x4); |
Vivek Natarajan | 22983c3 | 2011-01-27 14:45:09 +0530 | [diff] [blame] | 703 | |
Vasanthakumar Thiagarajan | 3dfd7f6 | 2011-04-11 16:39:40 +0530 | [diff] [blame] | 704 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, |
| 705 | AR_CH0_BB_DPLL1_REFDIV, 0x5); |
| 706 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, |
| 707 | AR_CH0_BB_DPLL1_NINI, 0x58); |
| 708 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, |
| 709 | AR_CH0_BB_DPLL1_NFRAC, 0x0); |
| 710 | |
| 711 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
| 712 | AR_CH0_BB_DPLL2_OUTDIV, 0x1); |
| 713 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
| 714 | AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); |
| 715 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
| 716 | AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); |
| 717 | |
| 718 | /* program BB PLL phase_shift to 0x6 */ |
| 719 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, |
| 720 | AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); |
| 721 | |
| 722 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
| 723 | AR_CH0_BB_DPLL2_PLL_PWD, 0x0); |
Vivek Natarajan | 75e0351 | 2011-03-10 11:05:42 +0530 | [diff] [blame] | 724 | udelay(1000); |
Vasanthakumar Thiagarajan | 0b488ac | 2011-04-20 10:26:15 +0530 | [diff] [blame] | 725 | } else if (AR_SREV_9340(ah)) { |
| 726 | u32 regval, pll2_divint, pll2_divfrac, refdiv; |
| 727 | |
| 728 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); |
| 729 | udelay(1000); |
| 730 | |
| 731 | REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); |
| 732 | udelay(100); |
| 733 | |
| 734 | if (ah->is_clk_25mhz) { |
| 735 | pll2_divint = 0x54; |
| 736 | pll2_divfrac = 0x1eb85; |
| 737 | refdiv = 3; |
| 738 | } else { |
| 739 | pll2_divint = 88; |
| 740 | pll2_divfrac = 0; |
| 741 | refdiv = 5; |
| 742 | } |
| 743 | |
| 744 | regval = REG_READ(ah, AR_PHY_PLL_MODE); |
| 745 | regval |= (0x1 << 16); |
| 746 | REG_WRITE(ah, AR_PHY_PLL_MODE, regval); |
| 747 | udelay(100); |
| 748 | |
| 749 | REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | |
| 750 | (pll2_divint << 18) | pll2_divfrac); |
| 751 | udelay(100); |
| 752 | |
| 753 | regval = REG_READ(ah, AR_PHY_PLL_MODE); |
| 754 | regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | |
| 755 | (0x4 << 26) | (0x18 << 19); |
| 756 | REG_WRITE(ah, AR_PHY_PLL_MODE, regval); |
| 757 | REG_WRITE(ah, AR_PHY_PLL_MODE, |
| 758 | REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); |
| 759 | udelay(1000); |
Vivek Natarajan | 22983c3 | 2011-01-27 14:45:09 +0530 | [diff] [blame] | 760 | } |
Vasanthakumar Thiagarajan | d09b17f | 2010-12-06 04:27:44 -0800 | [diff] [blame] | 761 | |
| 762 | pll = ath9k_hw_compute_pll_control(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 763 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 764 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 765 | |
Vasanthakumar Thiagarajan | 0b488ac | 2011-04-20 10:26:15 +0530 | [diff] [blame] | 766 | if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) |
Vasanthakumar Thiagarajan | 3dfd7f6 | 2011-04-11 16:39:40 +0530 | [diff] [blame] | 767 | udelay(1000); |
| 768 | |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 769 | /* Switch the core clock for ar9271 to 117Mhz */ |
| 770 | if (AR_SREV_9271(ah)) { |
Sujith | 25e2ab1 | 2010-03-17 14:25:22 +0530 | [diff] [blame] | 771 | udelay(500); |
| 772 | REG_WRITE(ah, 0x50040, 0x304); |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 773 | } |
| 774 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 775 | udelay(RTC_PLL_SETTLE_DELAY); |
| 776 | |
| 777 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |
Vasanthakumar Thiagarajan | 0b488ac | 2011-04-20 10:26:15 +0530 | [diff] [blame] | 778 | |
| 779 | if (AR_SREV_9340(ah)) { |
| 780 | if (ah->is_clk_25mhz) { |
| 781 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); |
| 782 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); |
| 783 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); |
| 784 | } else { |
| 785 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); |
| 786 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); |
| 787 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); |
| 788 | } |
| 789 | udelay(100); |
| 790 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 791 | } |
| 792 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 793 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 794 | enum nl80211_iftype opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 795 | { |
Vasanthakumar Thiagarajan | 79d1d2b | 2011-04-19 19:29:19 +0530 | [diff] [blame] | 796 | u32 sync_default = AR_INTR_SYNC_DEFAULT; |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 797 | u32 imr_reg = AR_IMR_TXERR | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 798 | AR_IMR_TXURN | |
| 799 | AR_IMR_RXERR | |
| 800 | AR_IMR_RXORN | |
| 801 | AR_IMR_BCNMISC; |
| 802 | |
Vasanthakumar Thiagarajan | 79d1d2b | 2011-04-19 19:29:19 +0530 | [diff] [blame] | 803 | if (AR_SREV_9340(ah)) |
| 804 | sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; |
| 805 | |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 806 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 807 | imr_reg |= AR_IMR_RXOK_HP; |
| 808 | if (ah->config.rx_intr_mitigation) |
| 809 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
| 810 | else |
| 811 | imr_reg |= AR_IMR_RXOK_LP; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 812 | |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 813 | } else { |
| 814 | if (ah->config.rx_intr_mitigation) |
| 815 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
| 816 | else |
| 817 | imr_reg |= AR_IMR_RXOK; |
| 818 | } |
| 819 | |
| 820 | if (ah->config.tx_intr_mitigation) |
| 821 | imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; |
| 822 | else |
| 823 | imr_reg |= AR_IMR_TXOK; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 824 | |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 825 | if (opmode == NL80211_IFTYPE_AP) |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 826 | imr_reg |= AR_IMR_MIB; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 827 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 828 | ENABLE_REGWRITE_BUFFER(ah); |
| 829 | |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 830 | REG_WRITE(ah, AR_IMR, imr_reg); |
Pavel Roskin | 74bad5c | 2010-02-23 18:15:27 -0500 | [diff] [blame] | 831 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
| 832 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 833 | |
| 834 | if (!AR_SREV_9100(ah)) { |
| 835 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); |
Vasanthakumar Thiagarajan | 79d1d2b | 2011-04-19 19:29:19 +0530 | [diff] [blame] | 836 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 837 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); |
| 838 | } |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 839 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 840 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 841 | |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 842 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 843 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); |
| 844 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); |
| 845 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); |
| 846 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); |
| 847 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 848 | } |
| 849 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 850 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 851 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 852 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 853 | val = min(val, (u32) 0xFFFF); |
| 854 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 855 | } |
| 856 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 857 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 858 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 859 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 860 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); |
| 861 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); |
| 862 | } |
| 863 | |
| 864 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) |
| 865 | { |
| 866 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 867 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); |
| 868 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 869 | } |
| 870 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 871 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 872 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 873 | if (tu > 0xFFFF) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 874 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, |
| 875 | "bad global tx timeout %u\n", tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 876 | ah->globaltxtimeout = (u32) -1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 877 | return false; |
| 878 | } else { |
| 879 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 880 | ah->globaltxtimeout = tu; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 881 | return true; |
| 882 | } |
| 883 | } |
| 884 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 885 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 886 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 887 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
| 888 | int acktimeout; |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 889 | int slottime; |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 890 | int sifstime; |
| 891 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 892 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
| 893 | ah->misc_mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 894 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 895 | if (ah->misc_mode != 0) |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 896 | REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 897 | |
| 898 | if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) |
| 899 | sifstime = 16; |
| 900 | else |
| 901 | sifstime = 10; |
| 902 | |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 903 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
| 904 | slottime = ah->slottime + 3 * ah->coverage_class; |
| 905 | acktimeout = slottime + sifstime; |
Felix Fietkau | 42c4568 | 2010-02-11 18:07:19 +0100 | [diff] [blame] | 906 | |
| 907 | /* |
| 908 | * Workaround for early ACK timeouts, add an offset to match the |
| 909 | * initval's 64us ack timeout value. |
| 910 | * This was initially only meant to work around an issue with delayed |
| 911 | * BA frames in some implementations, but it has been found to fix ACK |
| 912 | * timeout issues in other cases as well. |
| 913 | */ |
| 914 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) |
| 915 | acktimeout += 64 - sifstime - ah->slottime; |
| 916 | |
Felix Fietkau | caabf2b | 2010-12-13 08:40:51 +0100 | [diff] [blame] | 917 | ath9k_hw_setslottime(ah, ah->slottime); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 918 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
| 919 | ath9k_hw_set_cts_timeout(ah, acktimeout); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 920 | if (ah->globaltxtimeout != (u32) -1) |
| 921 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 922 | } |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 923 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 924 | |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 925 | void ath9k_hw_deinit(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 926 | { |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 927 | struct ath_common *common = ath9k_hw_common(ah); |
| 928 | |
Sujith | 736b3a2 | 2010-03-17 14:25:24 +0530 | [diff] [blame] | 929 | if (common->state < ATH_HW_INITIALIZED) |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 930 | goto free_hw; |
| 931 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 932 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 933 | |
| 934 | free_hw: |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 935 | ath9k_hw_rf_free_ext_banks(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 936 | } |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 937 | EXPORT_SYMBOL(ath9k_hw_deinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 938 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 939 | /*******/ |
| 940 | /* INI */ |
| 941 | /*******/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 942 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 943 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
Bob Copeland | 3a702e4 | 2009-03-30 22:30:29 -0400 | [diff] [blame] | 944 | { |
| 945 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); |
| 946 | |
| 947 | if (IS_CHAN_B(chan)) |
| 948 | ctl |= CTL_11B; |
| 949 | else if (IS_CHAN_G(chan)) |
| 950 | ctl |= CTL_11G; |
| 951 | else |
| 952 | ctl |= CTL_11A; |
| 953 | |
| 954 | return ctl; |
| 955 | } |
| 956 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 957 | /****************************************/ |
| 958 | /* Reset and Channel Switching Routines */ |
| 959 | /****************************************/ |
| 960 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 961 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 962 | { |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 963 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 964 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 965 | ENABLE_REGWRITE_BUFFER(ah); |
| 966 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 967 | /* |
| 968 | * set AHB_MODE not to do cacheline prefetches |
| 969 | */ |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 970 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 971 | REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 972 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 973 | /* |
| 974 | * let mac dma reads be in 128 byte chunks |
| 975 | */ |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 976 | REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 977 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 978 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 979 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 980 | /* |
| 981 | * Restore TX Trigger Level to its pre-reset value. |
| 982 | * The initial value depends on whether aggregation is enabled, and is |
| 983 | * adjusted whenever underruns are detected. |
| 984 | */ |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 985 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 986 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 987 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 988 | ENABLE_REGWRITE_BUFFER(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 989 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 990 | /* |
| 991 | * let mac dma writes be in 128 byte chunks |
| 992 | */ |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 993 | REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 994 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 995 | /* |
| 996 | * Setup receive FIFO threshold to hold off TX activities |
| 997 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 998 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
| 999 | |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 1000 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1001 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); |
| 1002 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); |
| 1003 | |
| 1004 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - |
| 1005 | ah->caps.rx_status_len); |
| 1006 | } |
| 1007 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1008 | /* |
| 1009 | * reduce the number of usable entries in PCU TXBUF to avoid |
| 1010 | * wrap around issues. |
| 1011 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1012 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1013 | /* For AR9285 the number of Fifos are reduced to half. |
| 1014 | * So set the usable tx buf size also to half to |
| 1015 | * avoid data/delimiter underruns |
| 1016 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1017 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 1018 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1019 | } else if (!AR_SREV_9271(ah)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1020 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 1021 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); |
| 1022 | } |
Vasanthakumar Thiagarajan | 744d402 | 2010-04-15 17:39:27 -0400 | [diff] [blame] | 1023 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1024 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1025 | |
Vasanthakumar Thiagarajan | 744d402 | 2010-04-15 17:39:27 -0400 | [diff] [blame] | 1026 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1027 | ath9k_hw_reset_txstatus_ring(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1028 | } |
| 1029 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1030 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1031 | { |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 1032 | u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; |
| 1033 | u32 set = AR_STA_ID1_KSRCH_MODE; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1034 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1035 | switch (opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1036 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 1037 | case NL80211_IFTYPE_MESH_POINT: |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 1038 | set |= AR_STA_ID1_ADHOC; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1039 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 1040 | break; |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 1041 | case NL80211_IFTYPE_AP: |
| 1042 | set |= AR_STA_ID1_STA_AP; |
| 1043 | /* fall through */ |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1044 | case NL80211_IFTYPE_STATION: |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 1045 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1046 | break; |
Rajkumar Manoharan | 5f841b4 | 2010-10-27 18:31:15 +0530 | [diff] [blame] | 1047 | default: |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 1048 | if (!ah->is_monitoring) |
| 1049 | set = 0; |
Rajkumar Manoharan | 5f841b4 | 2010-10-27 18:31:15 +0530 | [diff] [blame] | 1050 | break; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1051 | } |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 1052 | REG_RMW(ah, AR_STA_ID1, set, mask); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1053 | } |
| 1054 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1055 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
| 1056 | u32 *coef_mantissa, u32 *coef_exponent) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1057 | { |
| 1058 | u32 coef_exp, coef_man; |
| 1059 | |
| 1060 | for (coef_exp = 31; coef_exp > 0; coef_exp--) |
| 1061 | if ((coef_scaled >> coef_exp) & 0x1) |
| 1062 | break; |
| 1063 | |
| 1064 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); |
| 1065 | |
| 1066 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); |
| 1067 | |
| 1068 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); |
| 1069 | *coef_exponent = coef_exp - 16; |
| 1070 | } |
| 1071 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1072 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1073 | { |
| 1074 | u32 rst_flags; |
| 1075 | u32 tmpReg; |
| 1076 | |
Sujith | 7076849 | 2009-02-16 13:23:12 +0530 | [diff] [blame] | 1077 | if (AR_SREV_9100(ah)) { |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 1078 | REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, |
| 1079 | AR_RTC_DERIVED_CLK_PERIOD, 1); |
Sujith | 7076849 | 2009-02-16 13:23:12 +0530 | [diff] [blame] | 1080 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 1081 | } |
| 1082 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1083 | ENABLE_REGWRITE_BUFFER(ah); |
| 1084 | |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1085 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1086 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 1087 | udelay(10); |
| 1088 | } |
| 1089 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1090 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 1091 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1092 | |
| 1093 | if (AR_SREV_9100(ah)) { |
| 1094 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | |
| 1095 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; |
| 1096 | } else { |
| 1097 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
| 1098 | if (tmpReg & |
| 1099 | (AR_INTR_SYNC_LOCAL_TIMEOUT | |
| 1100 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1101 | u32 val; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1102 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1103 | |
| 1104 | val = AR_RC_HOSTIF; |
| 1105 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1106 | val |= AR_RC_AHB; |
| 1107 | REG_WRITE(ah, AR_RC, val); |
| 1108 | |
| 1109 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1110 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1111 | |
| 1112 | rst_flags = AR_RTC_RC_MAC_WARM; |
| 1113 | if (type == ATH9K_RESET_COLD) |
| 1114 | rst_flags |= AR_RTC_RC_MAC_COLD; |
| 1115 | } |
| 1116 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1117 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1118 | |
| 1119 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1120 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1121 | udelay(50); |
| 1122 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1123 | REG_WRITE(ah, AR_RTC_RC, 0); |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1124 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1125 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1126 | "RTC stuck in MAC reset\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1127 | return false; |
| 1128 | } |
| 1129 | |
| 1130 | if (!AR_SREV_9100(ah)) |
| 1131 | REG_WRITE(ah, AR_RC, 0); |
| 1132 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1133 | if (AR_SREV_9100(ah)) |
| 1134 | udelay(50); |
| 1135 | |
| 1136 | return true; |
| 1137 | } |
| 1138 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1139 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1140 | { |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1141 | ENABLE_REGWRITE_BUFFER(ah); |
| 1142 | |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1143 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1144 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 1145 | udelay(10); |
| 1146 | } |
| 1147 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1148 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 1149 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1150 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1151 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1152 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
| 1153 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1154 | REG_WRITE(ah, AR_RTC_RESET, 0); |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1155 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1156 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1157 | |
Senthil Balasubramanian | 84e2169 | 2010-04-15 17:38:30 -0400 | [diff] [blame] | 1158 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1159 | udelay(2); |
| 1160 | |
| 1161 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1162 | REG_WRITE(ah, AR_RC, 0); |
| 1163 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1164 | REG_WRITE(ah, AR_RTC_RESET, 1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1165 | |
| 1166 | if (!ath9k_hw_wait(ah, |
| 1167 | AR_RTC_STATUS, |
| 1168 | AR_RTC_STATUS_M, |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1169 | AR_RTC_STATUS_ON, |
| 1170 | AH_WAIT_TIMEOUT)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1171 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1172 | "RTC not waking up\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1173 | return false; |
| 1174 | } |
| 1175 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1176 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); |
| 1177 | } |
| 1178 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1179 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1180 | { |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1181 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1182 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 1183 | udelay(10); |
| 1184 | } |
| 1185 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1186 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1187 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
| 1188 | |
| 1189 | switch (type) { |
| 1190 | case ATH9K_RESET_POWER_ON: |
| 1191 | return ath9k_hw_set_reset_power_on(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1192 | case ATH9K_RESET_WARM: |
| 1193 | case ATH9K_RESET_COLD: |
| 1194 | return ath9k_hw_set_reset(ah, type); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1195 | default: |
| 1196 | return false; |
| 1197 | } |
| 1198 | } |
| 1199 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1200 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1201 | struct ath9k_channel *chan) |
| 1202 | { |
Vivek Natarajan | 42abfbe | 2009-09-17 09:27:59 +0530 | [diff] [blame] | 1203 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1204 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
| 1205 | return false; |
| 1206 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1207 | return false; |
| 1208 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1209 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1210 | return false; |
| 1211 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1212 | ah->chip_fullsleep = false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1213 | ath9k_hw_init_pll(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1214 | ath9k_hw_set_rfmode(ah, chan); |
| 1215 | |
| 1216 | return true; |
| 1217 | } |
| 1218 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1219 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1220 | struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1221 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1222 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1223 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 1224 | struct ieee80211_channel *channel = chan->chan; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1225 | u32 qnum; |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1226 | int r; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1227 | |
| 1228 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { |
| 1229 | if (ath9k_hw_numtxpending(ah, qnum)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1230 | ath_dbg(common, ATH_DBG_QUEUE, |
| 1231 | "Transmit frames pending on queue %d\n", qnum); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1232 | return false; |
| 1233 | } |
| 1234 | } |
| 1235 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1236 | if (!ath9k_hw_rfbus_req(ah)) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1237 | ath_err(common, "Could not kill baseband RX\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1238 | return false; |
| 1239 | } |
| 1240 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1241 | ath9k_hw_set_channel_regs(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1242 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1243 | r = ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1244 | if (r) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1245 | ath_err(common, "Failed to set channel\n"); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1246 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1247 | } |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 1248 | ath9k_hw_set_clockrate(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1249 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 1250 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1251 | ath9k_regd_get_ctl(regulatory, chan), |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1252 | channel->max_antenna_gain * 2, |
| 1253 | channel->max_power * 2, |
| 1254 | min((u32) MAX_RATE_POWER, |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 1255 | (u32) regulatory->power_limit), false); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1256 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1257 | ath9k_hw_rfbus_done(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1258 | |
| 1259 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1260 | ath9k_hw_set_delta_slope(ah, chan); |
| 1261 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1262 | ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1263 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1264 | return true; |
| 1265 | } |
| 1266 | |
Felix Fietkau | 691680b | 2011-03-19 13:55:38 +0100 | [diff] [blame] | 1267 | static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) |
| 1268 | { |
| 1269 | u32 gpio_mask = ah->gpio_mask; |
| 1270 | int i; |
| 1271 | |
| 1272 | for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { |
| 1273 | if (!(gpio_mask & 1)) |
| 1274 | continue; |
| 1275 | |
| 1276 | ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
| 1277 | ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); |
| 1278 | } |
| 1279 | } |
| 1280 | |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1281 | bool ath9k_hw_check_alive(struct ath_hw *ah) |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1282 | { |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1283 | int count = 50; |
| 1284 | u32 reg; |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1285 | |
Felix Fietkau | e17f83e | 2010-09-22 12:34:53 +0200 | [diff] [blame] | 1286 | if (AR_SREV_9285_12_OR_LATER(ah)) |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1287 | return true; |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1288 | |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1289 | do { |
| 1290 | reg = REG_READ(ah, AR_OBS_BUS_1); |
| 1291 | |
| 1292 | if ((reg & 0x7E7FFFEF) == 0x00702400) |
| 1293 | continue; |
| 1294 | |
| 1295 | switch (reg & 0x7E000B00) { |
| 1296 | case 0x1E000000: |
| 1297 | case 0x52000B00: |
| 1298 | case 0x18000B00: |
| 1299 | continue; |
| 1300 | default: |
| 1301 | return true; |
| 1302 | } |
| 1303 | } while (count-- > 0); |
| 1304 | |
| 1305 | return false; |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1306 | } |
Felix Fietkau | c9c99e5 | 2010-04-19 19:57:29 +0200 | [diff] [blame] | 1307 | EXPORT_SYMBOL(ath9k_hw_check_alive); |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1308 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1309 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 1310 | struct ath9k_hw_cal_data *caldata, bool bChannelChange) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1311 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1312 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1313 | u32 saveLedState; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1314 | struct ath9k_channel *curchan = ah->curchan; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1315 | u32 saveDefAntenna; |
| 1316 | u32 macStaId1; |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1317 | u64 tsf = 0; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1318 | int i, r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1319 | |
Luis R. Rodriguez | 43c2761 | 2009-09-13 21:07:07 -0700 | [diff] [blame] | 1320 | ah->txchainmask = common->tx_chainmask; |
| 1321 | ah->rxchainmask = common->rx_chainmask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1322 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1323 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1324 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1325 | |
Felix Fietkau | d9891c7 | 2010-09-29 17:15:27 +0200 | [diff] [blame] | 1326 | if (curchan && !ah->chip_fullsleep) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1327 | ath9k_hw_getnf(ah, curchan); |
| 1328 | |
Felix Fietkau | 20bd2a0 | 2010-07-31 00:12:00 +0200 | [diff] [blame] | 1329 | ah->caldata = caldata; |
| 1330 | if (caldata && |
| 1331 | (chan->channel != caldata->channel || |
| 1332 | (chan->channelFlags & ~CHANNEL_CW_INT) != |
| 1333 | (caldata->channelFlags & ~CHANNEL_CW_INT))) { |
| 1334 | /* Operating channel changed, reset channel calibration data */ |
| 1335 | memset(caldata, 0, sizeof(*caldata)); |
| 1336 | ath9k_init_nfcal_hist_buffer(ah, chan); |
| 1337 | } |
| 1338 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1339 | if (bChannelChange && |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1340 | (ah->chip_fullsleep != true) && |
| 1341 | (ah->curchan != NULL) && |
| 1342 | (chan->channel != ah->curchan->channel) && |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1343 | ((chan->channelFlags & CHANNEL_ALL) == |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1344 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
Rajkumar Manoharan | 58d7e0f | 2010-09-08 15:57:12 +0530 | [diff] [blame] | 1345 | (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1346 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1347 | if (ath9k_hw_channel_change(ah, chan)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1348 | ath9k_hw_loadnf(ah, ah->curchan); |
Felix Fietkau | 00c8659 | 2010-07-30 21:02:09 +0200 | [diff] [blame] | 1349 | ath9k_hw_start_nfcal(ah, true); |
Rajkumar Manoharan | c2ba334 | 2010-09-03 16:00:00 +0530 | [diff] [blame] | 1350 | if (AR_SREV_9271(ah)) |
| 1351 | ar9002_hw_load_ani_reg(ah, chan); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1352 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1353 | } |
| 1354 | } |
| 1355 | |
| 1356 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); |
| 1357 | if (saveDefAntenna == 0) |
| 1358 | saveDefAntenna = 1; |
| 1359 | |
| 1360 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; |
| 1361 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1362 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
Felix Fietkau | f860d52 | 2010-06-30 02:07:48 +0200 | [diff] [blame] | 1363 | if (AR_SREV_9100(ah) || |
| 1364 | (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1365 | tsf = ath9k_hw_gettsf64(ah); |
| 1366 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1367 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
| 1368 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | |
| 1369 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); |
| 1370 | |
| 1371 | ath9k_hw_mark_phy_inactive(ah); |
| 1372 | |
Vasanthakumar Thiagarajan | 45ef6a0 | 2010-12-15 07:30:53 -0800 | [diff] [blame] | 1373 | ah->paprd_table_write_done = false; |
| 1374 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 1375 | /* Only required on the first reset */ |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1376 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1377 | REG_WRITE(ah, |
| 1378 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1379 | AR9271_RADIO_RF_RST); |
| 1380 | udelay(50); |
| 1381 | } |
| 1382 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1383 | if (!ath9k_hw_chip_reset(ah, chan)) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1384 | ath_err(common, "Chip reset failed\n"); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1385 | return -EINVAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1386 | } |
| 1387 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 1388 | /* Only required on the first reset */ |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1389 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1390 | ah->htc_reset_init = false; |
| 1391 | REG_WRITE(ah, |
| 1392 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1393 | AR9271_GATE_MAC_CTL); |
| 1394 | udelay(50); |
| 1395 | } |
| 1396 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1397 | /* Restore TSF */ |
Felix Fietkau | f860d52 | 2010-06-30 02:07:48 +0200 | [diff] [blame] | 1398 | if (tsf) |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1399 | ath9k_hw_settsf64(ah, tsf); |
| 1400 | |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 1401 | if (AR_SREV_9280_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 369391d | 2009-01-21 19:24:13 +0530 | [diff] [blame] | 1402 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1403 | |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 1404 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1405 | ar9002_hw_enable_async_fifo(ah); |
| 1406 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1407 | r = ath9k_hw_process_ini(ah, chan); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1408 | if (r) |
| 1409 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1410 | |
Felix Fietkau | f860d52 | 2010-06-30 02:07:48 +0200 | [diff] [blame] | 1411 | /* |
| 1412 | * Some AR91xx SoC devices frequently fail to accept TSF writes |
| 1413 | * right after the chip reset. When that happens, write a new |
| 1414 | * value after the initvals have been applied, with an offset |
| 1415 | * based on measured time difference |
| 1416 | */ |
| 1417 | if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { |
| 1418 | tsf += 1500; |
| 1419 | ath9k_hw_settsf64(ah, tsf); |
| 1420 | } |
| 1421 | |
Jouni Malinen | 0ced0e1 | 2009-01-08 13:32:13 +0200 | [diff] [blame] | 1422 | /* Setup MFP options for CCMP */ |
| 1423 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 1424 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt |
| 1425 | * frames when constructing CCMP AAD. */ |
| 1426 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, |
| 1427 | 0xc7ff); |
| 1428 | ah->sw_mgmt_crypto = false; |
| 1429 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 1430 | /* Disable hardware crypto for management frames */ |
| 1431 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, |
| 1432 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); |
| 1433 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
| 1434 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); |
| 1435 | ah->sw_mgmt_crypto = true; |
| 1436 | } else |
| 1437 | ah->sw_mgmt_crypto = true; |
| 1438 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1439 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1440 | ath9k_hw_set_delta_slope(ah, chan); |
| 1441 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1442 | ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | d650915 | 2009-03-13 08:56:05 +0530 | [diff] [blame] | 1443 | ah->eep_ops->set_board_values(ah, chan); |
Luis R. Rodriguez | a776582 | 2009-10-19 02:33:45 -0400 | [diff] [blame] | 1444 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1445 | ENABLE_REGWRITE_BUFFER(ah); |
| 1446 | |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1447 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
| 1448 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1449 | | macStaId1 |
| 1450 | | AR_STA_ID1_RTS_USE_DEF |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1451 | | (ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1452 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1453 | | ah->sta_id1_defaults); |
Luis R. Rodriguez | 13b8155 | 2009-09-10 17:52:45 -0700 | [diff] [blame] | 1454 | ath_hw_setbssidmask(common); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1455 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
Luis R. Rodriguez | 3453ad8 | 2009-09-10 08:57:00 -0700 | [diff] [blame] | 1456 | ath9k_hw_write_associd(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1457 | REG_WRITE(ah, AR_ISR, ~0); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1458 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); |
| 1459 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1460 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1461 | |
Sujith Manoharan | 00e0003 | 2011-01-26 21:59:05 +0530 | [diff] [blame] | 1462 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
| 1463 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1464 | r = ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1465 | if (r) |
| 1466 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1467 | |
Felix Fietkau | dfdac8a | 2010-10-08 22:13:51 +0200 | [diff] [blame] | 1468 | ath9k_hw_set_clockrate(ah); |
| 1469 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1470 | ENABLE_REGWRITE_BUFFER(ah); |
| 1471 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1472 | for (i = 0; i < AR_NUM_DCU; i++) |
| 1473 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); |
| 1474 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1475 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1476 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1477 | ah->intr_txqs = 0; |
Felix Fietkau | f4c607d | 2011-03-23 20:57:28 +0100 | [diff] [blame] | 1478 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1479 | ath9k_hw_resettxqueue(ah, i); |
| 1480 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1481 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1482 | ath9k_hw_ani_cache_ini_regs(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1483 | ath9k_hw_init_qos(ah); |
| 1484 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1485 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
Felix Fietkau | 5582132 | 2010-12-17 00:57:01 +0100 | [diff] [blame] | 1486 | ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1487 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1488 | ath9k_hw_init_global_settings(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1489 | |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 1490 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 1491 | ar9002_hw_update_async_fifo(ah); |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 1492 | ar9002_hw_enable_wep_aggregation(ah); |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1493 | } |
| 1494 | |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 1495 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1496 | |
| 1497 | ath9k_hw_set_dma(ah); |
| 1498 | |
| 1499 | REG_WRITE(ah, AR_OBS, 8); |
| 1500 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 1501 | if (ah->config.rx_intr_mitigation) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1502 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
| 1503 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); |
| 1504 | } |
| 1505 | |
Vasanthakumar Thiagarajan | 7f62a13 | 2010-04-15 17:39:19 -0400 | [diff] [blame] | 1506 | if (ah->config.tx_intr_mitigation) { |
| 1507 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); |
| 1508 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); |
| 1509 | } |
| 1510 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1511 | ath9k_hw_init_bb(ah, chan); |
| 1512 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1513 | if (!ath9k_hw_init_cal(ah, chan)) |
Joe Perches | 6badaaf | 2009-06-28 09:26:32 -0700 | [diff] [blame] | 1514 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1515 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1516 | ENABLE_REGWRITE_BUFFER(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1517 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1518 | ath9k_hw_restore_chainmask(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1519 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
| 1520 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1521 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1522 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1523 | /* |
| 1524 | * For big endian systems turn on swapping for descriptors |
| 1525 | */ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1526 | if (AR_SREV_9100(ah)) { |
| 1527 | u32 mask; |
| 1528 | mask = REG_READ(ah, AR_CFG); |
| 1529 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1530 | ath_dbg(common, ATH_DBG_RESET, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 1531 | "CFG Byte Swap Set 0x%x\n", mask); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1532 | } else { |
| 1533 | mask = |
| 1534 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; |
| 1535 | REG_WRITE(ah, AR_CFG, mask); |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1536 | ath_dbg(common, ATH_DBG_RESET, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 1537 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1538 | } |
| 1539 | } else { |
Sujith | cbba8cd | 2010-06-02 15:53:31 +0530 | [diff] [blame] | 1540 | if (common->bus_ops->ath_bus_type == ATH_USB) { |
| 1541 | /* Configure AR9271 target WLAN */ |
| 1542 | if (AR_SREV_9271(ah)) |
| 1543 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); |
| 1544 | else |
| 1545 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
| 1546 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1547 | #ifdef __BIG_ENDIAN |
Vasanthakumar Thiagarajan | 2be7bfe | 2011-04-19 19:29:14 +0530 | [diff] [blame] | 1548 | else if (AR_SREV_9340(ah)) |
| 1549 | REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); |
| 1550 | else |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1551 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1552 | #endif |
| 1553 | } |
| 1554 | |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1555 | if (ah->btcoex_hw.enabled) |
Vasanthakumar Thiagarajan | 42cc41e | 2009-08-26 21:08:45 +0530 | [diff] [blame] | 1556 | ath9k_hw_btcoex_enable(ah); |
| 1557 | |
Rajkumar Manoharan | 51ac8cb | 2011-05-20 17:52:13 +0530 | [diff] [blame] | 1558 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 1559 | ar9003_hw_bb_watchdog_config(ah); |
Vasanthakumar Thiagarajan | d8903a5 | 2010-04-15 17:39:25 -0400 | [diff] [blame] | 1560 | |
Rajkumar Manoharan | 51ac8cb | 2011-05-20 17:52:13 +0530 | [diff] [blame] | 1561 | ar9003_hw_disable_phy_restart(ah); |
| 1562 | } |
| 1563 | |
Felix Fietkau | 691680b | 2011-03-19 13:55:38 +0100 | [diff] [blame] | 1564 | ath9k_hw_apply_gpio_override(ah); |
| 1565 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1566 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1567 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1568 | EXPORT_SYMBOL(ath9k_hw_reset); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1569 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1570 | /******************************/ |
| 1571 | /* Power Management (Chipset) */ |
| 1572 | /******************************/ |
| 1573 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1574 | /* |
| 1575 | * Notify Power Mgt is disabled in self-generated frames. |
| 1576 | * If requested, force chip to sleep. |
| 1577 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1578 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1579 | { |
| 1580 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1581 | if (setChip) { |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1582 | /* |
| 1583 | * Clear the RTC force wake bit to allow the |
| 1584 | * mac to go to sleep. |
| 1585 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1586 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1587 | AR_RTC_FORCE_WAKE_EN); |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1588 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1589 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
| 1590 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1591 | /* Shutdown chip. Active low */ |
Sujith | 14b3af3 | 2010-03-17 14:25:18 +0530 | [diff] [blame] | 1592 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) |
Sujith | 4921be8 | 2009-09-18 15:04:27 +0530 | [diff] [blame] | 1593 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
| 1594 | AR_RTC_RESET_EN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1595 | } |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1596 | |
| 1597 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ |
| 1598 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1599 | REG_WRITE(ah, AR_WA, |
| 1600 | ah->WARegVal & ~AR_WA_D3_L1_DISABLE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1601 | } |
| 1602 | |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1603 | /* |
| 1604 | * Notify Power Management is enabled in self-generating |
| 1605 | * frames. If request, set power mode of chip to |
| 1606 | * auto/normal. Duration in units of 128us (1/8 TU). |
| 1607 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1608 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1609 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1610 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1611 | if (setChip) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1612 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1613 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1614 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1615 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1616 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1617 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1618 | } else { |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1619 | /* |
| 1620 | * Clear the RTC force wake bit to allow the |
| 1621 | * mac to go to sleep. |
| 1622 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1623 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1624 | AR_RTC_FORCE_WAKE_EN); |
| 1625 | } |
| 1626 | } |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1627 | |
| 1628 | /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ |
| 1629 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1630 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1631 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1632 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1633 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1634 | { |
| 1635 | u32 val; |
| 1636 | int i; |
| 1637 | |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 1638 | /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ |
| 1639 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1640 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
| 1641 | udelay(10); |
| 1642 | } |
| 1643 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1644 | if (setChip) { |
| 1645 | if ((REG_READ(ah, AR_RTC_STATUS) & |
| 1646 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { |
| 1647 | if (ath9k_hw_set_reset_reg(ah, |
| 1648 | ATH9K_RESET_POWER_ON) != true) { |
| 1649 | return false; |
| 1650 | } |
Luis R. Rodriguez | e041228 | 2010-04-15 17:38:15 -0400 | [diff] [blame] | 1651 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1652 | ath9k_hw_init_pll(ah, NULL); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1653 | } |
| 1654 | if (AR_SREV_9100(ah)) |
| 1655 | REG_SET_BIT(ah, AR_RTC_RESET, |
| 1656 | AR_RTC_RESET_EN); |
| 1657 | |
| 1658 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1659 | AR_RTC_FORCE_WAKE_EN); |
| 1660 | udelay(50); |
| 1661 | |
| 1662 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
| 1663 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; |
| 1664 | if (val == AR_RTC_STATUS_ON) |
| 1665 | break; |
| 1666 | udelay(50); |
| 1667 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1668 | AR_RTC_FORCE_WAKE_EN); |
| 1669 | } |
| 1670 | if (i == 0) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1671 | ath_err(ath9k_hw_common(ah), |
| 1672 | "Failed to wakeup in %uus\n", |
| 1673 | POWER_UP_TIME / 20); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1674 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1675 | } |
| 1676 | } |
| 1677 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1678 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1679 | |
| 1680 | return true; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1681 | } |
| 1682 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1683 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1684 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1685 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1686 | int status = true, setChip = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1687 | static const char *modes[] = { |
| 1688 | "AWAKE", |
| 1689 | "FULL-SLEEP", |
| 1690 | "NETWORK SLEEP", |
| 1691 | "UNDEFINED" |
| 1692 | }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1693 | |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 1694 | if (ah->power_mode == mode) |
| 1695 | return status; |
| 1696 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1697 | ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", |
| 1698 | modes[ah->power_mode], modes[mode]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1699 | |
| 1700 | switch (mode) { |
| 1701 | case ATH9K_PM_AWAKE: |
| 1702 | status = ath9k_hw_set_power_awake(ah, setChip); |
| 1703 | break; |
| 1704 | case ATH9K_PM_FULL_SLEEP: |
| 1705 | ath9k_set_power_sleep(ah, setChip); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1706 | ah->chip_fullsleep = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1707 | break; |
| 1708 | case ATH9K_PM_NETWORK_SLEEP: |
| 1709 | ath9k_set_power_network_sleep(ah, setChip); |
| 1710 | break; |
| 1711 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1712 | ath_err(common, "Unknown power mode %u\n", mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1713 | return false; |
| 1714 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1715 | ah->power_mode = mode; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1716 | |
Luis R. Rodriguez | 69f4aab | 2010-12-07 15:13:23 -0800 | [diff] [blame] | 1717 | /* |
| 1718 | * XXX: If this warning never comes up after a while then |
| 1719 | * simply keep the ATH_DBG_WARN_ON_ONCE() but make |
| 1720 | * ath9k_hw_setpower() return type void. |
| 1721 | */ |
Sujith Manoharan | 97dcec5 | 2010-12-20 08:02:42 +0530 | [diff] [blame] | 1722 | |
| 1723 | if (!(ah->ah_flags & AH_UNPLUGGED)) |
| 1724 | ATH_DBG_WARN_ON_ONCE(!status); |
Luis R. Rodriguez | 69f4aab | 2010-12-07 15:13:23 -0800 | [diff] [blame] | 1725 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1726 | return status; |
| 1727 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1728 | EXPORT_SYMBOL(ath9k_hw_setpower); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1729 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1730 | /*******************/ |
| 1731 | /* Beacon Handling */ |
| 1732 | /*******************/ |
| 1733 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1734 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1735 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1736 | int flags = 0; |
| 1737 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1738 | ENABLE_REGWRITE_BUFFER(ah); |
| 1739 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1740 | switch (ah->opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1741 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 1742 | case NL80211_IFTYPE_MESH_POINT: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1743 | REG_SET_BIT(ah, AR_TXCFG, |
| 1744 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); |
Felix Fietkau | dd347f2 | 2011-03-22 21:54:17 +0100 | [diff] [blame] | 1745 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + |
| 1746 | TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1747 | flags |= AR_NDP_TIMER_EN; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1748 | case NL80211_IFTYPE_AP: |
Felix Fietkau | dd347f2 | 2011-03-22 21:54:17 +0100 | [diff] [blame] | 1749 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); |
| 1750 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - |
| 1751 | TU_TO_USEC(ah->config.dma_beacon_response_time)); |
| 1752 | REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - |
| 1753 | TU_TO_USEC(ah->config.sw_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1754 | flags |= |
| 1755 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; |
| 1756 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1757 | default: |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1758 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, |
| 1759 | "%s: unsupported opmode: %d\n", |
| 1760 | __func__, ah->opmode); |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1761 | return; |
| 1762 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1763 | } |
| 1764 | |
Felix Fietkau | dd347f2 | 2011-03-22 21:54:17 +0100 | [diff] [blame] | 1765 | REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); |
| 1766 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); |
| 1767 | REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); |
| 1768 | REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1769 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1770 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1771 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1772 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); |
| 1773 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1774 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1775 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1776 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1777 | const struct ath9k_beacon_state *bs) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1778 | { |
| 1779 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1780 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1781 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1782 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1783 | ENABLE_REGWRITE_BUFFER(ah); |
| 1784 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1785 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); |
| 1786 | |
| 1787 | REG_WRITE(ah, AR_BEACON_PERIOD, |
| 1788 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 1789 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, |
| 1790 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 1791 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1792 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1793 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1794 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
| 1795 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); |
| 1796 | |
| 1797 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; |
| 1798 | |
| 1799 | if (bs->bs_sleepduration > beaconintval) |
| 1800 | beaconintval = bs->bs_sleepduration; |
| 1801 | |
| 1802 | dtimperiod = bs->bs_dtimperiod; |
| 1803 | if (bs->bs_sleepduration > dtimperiod) |
| 1804 | dtimperiod = bs->bs_sleepduration; |
| 1805 | |
| 1806 | if (beaconintval == dtimperiod) |
| 1807 | nextTbtt = bs->bs_nextdtim; |
| 1808 | else |
| 1809 | nextTbtt = bs->bs_nexttbtt; |
| 1810 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1811 | ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
| 1812 | ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); |
| 1813 | ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); |
| 1814 | ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1815 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1816 | ENABLE_REGWRITE_BUFFER(ah); |
| 1817 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1818 | REG_WRITE(ah, AR_NEXT_DTIM, |
| 1819 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); |
| 1820 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); |
| 1821 | |
| 1822 | REG_WRITE(ah, AR_SLEEP1, |
| 1823 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) |
| 1824 | | AR_SLEEP1_ASSUME_DTIM); |
| 1825 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1826 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1827 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); |
| 1828 | else |
| 1829 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; |
| 1830 | |
| 1831 | REG_WRITE(ah, AR_SLEEP2, |
| 1832 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); |
| 1833 | |
| 1834 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
| 1835 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); |
| 1836 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1837 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 1838 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1839 | REG_SET_BIT(ah, AR_TIMER_MODE, |
| 1840 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | |
| 1841 | AR_DTIM_TIMER_EN); |
| 1842 | |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 1843 | /* TSF Out of Range Threshold */ |
| 1844 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1845 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1846 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1847 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1848 | /*******************/ |
| 1849 | /* HW Capabilities */ |
| 1850 | /*******************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1851 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1852 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1853 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1854 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1855 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1856 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1857 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1858 | |
Sujith Manoharan | 0ff2b5c | 2011-04-20 11:00:34 +0530 | [diff] [blame] | 1859 | u16 eeval; |
Vasanthakumar Thiagarajan | 47c80de | 2010-12-06 04:27:43 -0800 | [diff] [blame] | 1860 | u8 ant_div_ctl1, tx_chainmask, rx_chainmask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1861 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1862 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1863 | regulatory->current_rd = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1864 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1865 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
Felix Fietkau | e17f83e | 2010-09-22 12:34:53 +0200 | [diff] [blame] | 1866 | if (AR_SREV_9285_12_OR_LATER(ah)) |
Sujith | fec0de1 | 2009-02-12 10:06:43 +0530 | [diff] [blame] | 1867 | eeval |= AR9285_RDEXT_DEFAULT; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1868 | regulatory->current_rd_ext = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1869 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1870 | if (ah->opmode != NL80211_IFTYPE_AP && |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 1871 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1872 | if (regulatory->current_rd == 0x64 || |
| 1873 | regulatory->current_rd == 0x65) |
| 1874 | regulatory->current_rd += 5; |
| 1875 | else if (regulatory->current_rd == 0x41) |
| 1876 | regulatory->current_rd = 0x43; |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1877 | ath_dbg(common, ATH_DBG_REGULATORY, |
| 1878 | "regdomain mapped to 0x%x\n", regulatory->current_rd); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1879 | } |
Sujith | dc2222a | 2008-08-14 13:26:55 +0530 | [diff] [blame] | 1880 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1881 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1882 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 1883 | ath_err(common, |
| 1884 | "no band has been marked as supported in EEPROM\n"); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1885 | return -EINVAL; |
| 1886 | } |
| 1887 | |
Felix Fietkau | d465991 | 2010-10-14 16:02:39 +0200 | [diff] [blame] | 1888 | if (eeval & AR5416_OPFLAGS_11A) |
| 1889 | pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1890 | |
Felix Fietkau | d465991 | 2010-10-14 16:02:39 +0200 | [diff] [blame] | 1891 | if (eeval & AR5416_OPFLAGS_11G) |
| 1892 | pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1893 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1894 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1895 | /* |
| 1896 | * For AR9271 we will temporarilly uses the rx chainmax as read from |
| 1897 | * the EEPROM. |
| 1898 | */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1899 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1900 | !(eeval & AR5416_OPFLAGS_11A) && |
| 1901 | !(AR_SREV_9271(ah))) |
| 1902 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1903 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
Felix Fietkau | 598cdd5 | 2011-03-19 13:55:42 +0100 | [diff] [blame] | 1904 | else if (AR_SREV_9100(ah)) |
| 1905 | pCap->rx_chainmask = 0x7; |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1906 | else |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1907 | /* Use rx_chainmask from EEPROM. */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1908 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1909 | |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 1910 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1911 | |
Felix Fietkau | 02d2ebb | 2010-11-22 15:39:39 +0100 | [diff] [blame] | 1912 | /* enable key search for every frame in an aggregate */ |
| 1913 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 1914 | ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; |
| 1915 | |
Bruno Randolf | ce2220d | 2010-09-17 11:36:25 +0900 | [diff] [blame] | 1916 | common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; |
| 1917 | |
Felix Fietkau | 0db156e | 2011-03-23 20:57:29 +0100 | [diff] [blame] | 1918 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1919 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
| 1920 | else |
| 1921 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; |
| 1922 | |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 1923 | if (AR_SREV_9271(ah)) |
| 1924 | pCap->num_gpio_pins = AR9271_NUM_GPIO; |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 1925 | else if (AR_DEVID_7010(ah)) |
| 1926 | pCap->num_gpio_pins = AR7010_NUM_GPIO; |
Felix Fietkau | e17f83e | 2010-09-22 12:34:53 +0200 | [diff] [blame] | 1927 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 1928 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 1929 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1930 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
| 1931 | else |
| 1932 | pCap->num_gpio_pins = AR_NUM_GPIO; |
| 1933 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1934 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
| 1935 | pCap->hw_caps |= ATH9K_HW_CAP_CST; |
| 1936 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
| 1937 | } else { |
| 1938 | pCap->rts_aggr_limit = (8 * 1024); |
| 1939 | } |
| 1940 | |
Senthil Balasubramanian | e97275c | 2008-11-13 18:00:02 +0530 | [diff] [blame] | 1941 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1942 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
| 1943 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { |
| 1944 | ah->rfkill_gpio = |
| 1945 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); |
| 1946 | ah->rfkill_polarity = |
| 1947 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1948 | |
| 1949 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; |
| 1950 | } |
| 1951 | #endif |
Vasanthakumar Thiagarajan | d5d1154 | 2010-05-17 18:57:56 -0700 | [diff] [blame] | 1952 | if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) |
Vivek Natarajan | bde748a | 2010-04-05 14:48:05 +0530 | [diff] [blame] | 1953 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
| 1954 | else |
| 1955 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1956 | |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 1957 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1958 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 1959 | else |
| 1960 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 1961 | |
Vivek Natarajan | a6ef530 | 2011-04-26 10:39:53 +0530 | [diff] [blame] | 1962 | if (common->btcoex_enabled) { |
| 1963 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1964 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
Vivek Natarajan | a6ef530 | 2011-04-26 10:39:53 +0530 | [diff] [blame] | 1965 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300; |
| 1966 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300; |
| 1967 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300; |
| 1968 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 1969 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280; |
| 1970 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280; |
| 1971 | |
| 1972 | if (AR_SREV_9285(ah)) { |
| 1973 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
| 1974 | btcoex_hw->btpriority_gpio = |
| 1975 | ATH_BTPRIORITY_GPIO_9285; |
| 1976 | } else { |
| 1977 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
| 1978 | } |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 1979 | } |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 1980 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1981 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
Vasanthakumar Thiagarajan | c97c92d | 2009-01-02 15:35:46 +0530 | [diff] [blame] | 1982 | } |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1983 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 1984 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
Vasanthakumar Thiagarajan | 784ad50 | 2010-12-06 04:27:40 -0800 | [diff] [blame] | 1985 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; |
| 1986 | if (!AR_SREV_9485(ah)) |
| 1987 | pCap->hw_caps |= ATH9K_HW_CAP_LDPC; |
| 1988 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 1989 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
| 1990 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; |
| 1991 | pCap->rx_status_len = sizeof(struct ar9003_rxs); |
Vasanthakumar Thiagarajan | 162c3be | 2010-04-15 17:38:41 -0400 | [diff] [blame] | 1992 | pCap->tx_desc_len = sizeof(struct ar9003_txc); |
Vasanthakumar Thiagarajan | 5088c2f | 2010-04-15 17:39:34 -0400 | [diff] [blame] | 1993 | pCap->txs_len = sizeof(struct ar9003_txs); |
Luis R. Rodriguez | 6f48101 | 2011-01-20 17:47:39 -0800 | [diff] [blame] | 1994 | if (!ah->config.paprd_disable && |
| 1995 | ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) |
Felix Fietkau | 4935250 | 2010-06-12 00:33:59 -0400 | [diff] [blame] | 1996 | pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; |
Vasanthakumar Thiagarajan | 162c3be | 2010-04-15 17:38:41 -0400 | [diff] [blame] | 1997 | } else { |
| 1998 | pCap->tx_desc_len = sizeof(struct ath_desc); |
Felix Fietkau | 6b42e8d | 2010-04-26 15:04:35 -0400 | [diff] [blame] | 1999 | if (AR_SREV_9280_20(ah) && |
| 2000 | ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= |
| 2001 | AR5416_EEP_MINOR_VER_16) || |
| 2002 | ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) |
| 2003 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 2004 | } |
Vasanthakumar Thiagarajan | 1adf02f | 2010-04-15 17:38:24 -0400 | [diff] [blame] | 2005 | |
Vasanthakumar Thiagarajan | 6c84ce0 | 2010-04-15 17:39:16 -0400 | [diff] [blame] | 2006 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 2007 | pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; |
| 2008 | |
Senthil Balasubramanian | 6ee63f5 | 2010-11-10 05:03:16 -0800 | [diff] [blame] | 2009 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 2010 | ah->ent_mode = REG_READ(ah, AR_ENT_OTP); |
| 2011 | |
Felix Fietkau | a42acef | 2010-09-22 12:34:54 +0200 | [diff] [blame] | 2012 | if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) |
Vasanthakumar Thiagarajan | 6473d24 | 2010-05-13 18:42:38 -0700 | [diff] [blame] | 2013 | pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; |
| 2014 | |
Vasanthakumar Thiagarajan | 754dc53 | 2010-09-02 01:34:41 -0700 | [diff] [blame] | 2015 | if (AR_SREV_9285(ah)) |
| 2016 | if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { |
| 2017 | ant_div_ctl1 = |
| 2018 | ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); |
| 2019 | if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) |
| 2020 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; |
| 2021 | } |
Mohammed Shafi Shajakhan | ea066d5 | 2010-11-23 20:42:27 +0530 | [diff] [blame] | 2022 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 2023 | if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) |
| 2024 | pCap->hw_caps |= ATH9K_HW_CAP_APM; |
| 2025 | } |
| 2026 | |
| 2027 | |
Mohammed Shafi Shajakhan | 21d2c63 | 2011-05-13 20:29:31 +0530 | [diff] [blame] | 2028 | if (AR_SREV_9485(ah)) { |
| 2029 | ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); |
| 2030 | /* |
| 2031 | * enable the diversity-combining algorithm only when |
| 2032 | * both enable_lna_div and enable_fast_div are set |
| 2033 | * Table for Diversity |
| 2034 | * ant_div_alt_lnaconf bit 0-1 |
| 2035 | * ant_div_main_lnaconf bit 2-3 |
| 2036 | * ant_div_alt_gaintb bit 4 |
| 2037 | * ant_div_main_gaintb bit 5 |
| 2038 | * enable_ant_div_lnadiv bit 6 |
| 2039 | * enable_ant_fast_div bit 7 |
| 2040 | */ |
| 2041 | if ((ant_div_ctl1 >> 0x6) == 0x3) |
| 2042 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; |
| 2043 | } |
Vasanthakumar Thiagarajan | 754dc53 | 2010-09-02 01:34:41 -0700 | [diff] [blame] | 2044 | |
Vasanthakumar Thiagarajan | 8060e16 | 2010-12-06 04:27:42 -0800 | [diff] [blame] | 2045 | if (AR_SREV_9485_10(ah)) { |
| 2046 | pCap->pcie_lcr_extsync_en = true; |
| 2047 | pCap->pcie_lcr_offset = 0x80; |
| 2048 | } |
| 2049 | |
Vasanthakumar Thiagarajan | 47c80de | 2010-12-06 04:27:43 -0800 | [diff] [blame] | 2050 | tx_chainmask = pCap->tx_chainmask; |
| 2051 | rx_chainmask = pCap->rx_chainmask; |
| 2052 | while (tx_chainmask || rx_chainmask) { |
| 2053 | if (tx_chainmask & BIT(0)) |
| 2054 | pCap->max_txchains++; |
| 2055 | if (rx_chainmask & BIT(0)) |
| 2056 | pCap->max_rxchains++; |
| 2057 | |
| 2058 | tx_chainmask >>= 1; |
| 2059 | rx_chainmask >>= 1; |
| 2060 | } |
| 2061 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 2062 | return 0; |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 2063 | } |
| 2064 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2065 | /****************************/ |
| 2066 | /* GPIO / RFKILL / Antennae */ |
| 2067 | /****************************/ |
| 2068 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2069 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2070 | u32 gpio, u32 type) |
| 2071 | { |
| 2072 | int addr; |
| 2073 | u32 gpio_shift, tmp; |
| 2074 | |
| 2075 | if (gpio > 11) |
| 2076 | addr = AR_GPIO_OUTPUT_MUX3; |
| 2077 | else if (gpio > 5) |
| 2078 | addr = AR_GPIO_OUTPUT_MUX2; |
| 2079 | else |
| 2080 | addr = AR_GPIO_OUTPUT_MUX1; |
| 2081 | |
| 2082 | gpio_shift = (gpio % 6) * 5; |
| 2083 | |
| 2084 | if (AR_SREV_9280_20_OR_LATER(ah) |
| 2085 | || (addr != AR_GPIO_OUTPUT_MUX1)) { |
| 2086 | REG_RMW(ah, addr, (type << gpio_shift), |
| 2087 | (0x1f << gpio_shift)); |
| 2088 | } else { |
| 2089 | tmp = REG_READ(ah, addr); |
| 2090 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); |
| 2091 | tmp &= ~(0x1f << gpio_shift); |
| 2092 | tmp |= (type << gpio_shift); |
| 2093 | REG_WRITE(ah, addr, tmp); |
| 2094 | } |
| 2095 | } |
| 2096 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2097 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2098 | { |
| 2099 | u32 gpio_shift; |
| 2100 | |
Luis R. Rodriguez | 9680e8a | 2009-09-13 23:28:00 -0700 | [diff] [blame] | 2101 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2102 | |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2103 | if (AR_DEVID_7010(ah)) { |
| 2104 | gpio_shift = gpio; |
| 2105 | REG_RMW(ah, AR7010_GPIO_OE, |
| 2106 | (AR7010_GPIO_OE_AS_INPUT << gpio_shift), |
| 2107 | (AR7010_GPIO_OE_MASK << gpio_shift)); |
| 2108 | return; |
| 2109 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2110 | |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2111 | gpio_shift = gpio << 1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2112 | REG_RMW(ah, |
| 2113 | AR_GPIO_OE_OUT, |
| 2114 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), |
| 2115 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 2116 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2117 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2118 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2119 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2120 | { |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2121 | #define MS_REG_READ(x, y) \ |
| 2122 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) |
| 2123 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2124 | if (gpio >= ah->caps.num_gpio_pins) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2125 | return 0xffffffff; |
| 2126 | |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2127 | if (AR_DEVID_7010(ah)) { |
| 2128 | u32 val; |
| 2129 | val = REG_READ(ah, AR7010_GPIO_IN); |
| 2130 | return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; |
| 2131 | } else if (AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 9306990 | 2010-11-30 23:24:09 -0800 | [diff] [blame] | 2132 | return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & |
| 2133 | AR_GPIO_BIT(gpio)) != 0; |
Felix Fietkau | 783dfca | 2010-04-15 17:38:11 -0400 | [diff] [blame] | 2134 | else if (AR_SREV_9271(ah)) |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 2135 | return MS_REG_READ(AR9271, gpio) != 0; |
Felix Fietkau | a42acef | 2010-09-22 12:34:54 +0200 | [diff] [blame] | 2136 | else if (AR_SREV_9287_11_OR_LATER(ah)) |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 2137 | return MS_REG_READ(AR9287, gpio) != 0; |
Felix Fietkau | e17f83e | 2010-09-22 12:34:53 +0200 | [diff] [blame] | 2138 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2139 | return MS_REG_READ(AR9285, gpio) != 0; |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 2140 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2141 | return MS_REG_READ(AR928X, gpio) != 0; |
| 2142 | else |
| 2143 | return MS_REG_READ(AR, gpio) != 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2144 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2145 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2146 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2147 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2148 | u32 ah_signal_type) |
| 2149 | { |
| 2150 | u32 gpio_shift; |
| 2151 | |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2152 | if (AR_DEVID_7010(ah)) { |
| 2153 | gpio_shift = gpio; |
| 2154 | REG_RMW(ah, AR7010_GPIO_OE, |
| 2155 | (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), |
| 2156 | (AR7010_GPIO_OE_MASK << gpio_shift)); |
| 2157 | return; |
| 2158 | } |
| 2159 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2160 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2161 | gpio_shift = 2 * gpio; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2162 | REG_RMW(ah, |
| 2163 | AR_GPIO_OE_OUT, |
| 2164 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), |
| 2165 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 2166 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2167 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2168 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2169 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2170 | { |
Sujith | 88c1f4f | 2010-06-30 14:46:31 +0530 | [diff] [blame] | 2171 | if (AR_DEVID_7010(ah)) { |
| 2172 | val = val ? 0 : 1; |
| 2173 | REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), |
| 2174 | AR_GPIO_BIT(gpio)); |
| 2175 | return; |
| 2176 | } |
| 2177 | |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 2178 | if (AR_SREV_9271(ah)) |
| 2179 | val = ~val; |
| 2180 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2181 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
| 2182 | AR_GPIO_BIT(gpio)); |
| 2183 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2184 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2185 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2186 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2187 | { |
| 2188 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
| 2189 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2190 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2191 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2192 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2193 | { |
| 2194 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
| 2195 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2196 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2197 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2198 | /*********************/ |
| 2199 | /* General Operation */ |
| 2200 | /*********************/ |
| 2201 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2202 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2203 | { |
| 2204 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
| 2205 | u32 phybits = REG_READ(ah, AR_PHY_ERR); |
| 2206 | |
| 2207 | if (phybits & AR_PHY_ERR_RADAR) |
| 2208 | bits |= ATH9K_RX_FILTER_PHYRADAR; |
| 2209 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) |
| 2210 | bits |= ATH9K_RX_FILTER_PHYERR; |
| 2211 | |
| 2212 | return bits; |
| 2213 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2214 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2215 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2216 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2217 | { |
| 2218 | u32 phybits; |
| 2219 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 2220 | ENABLE_REGWRITE_BUFFER(ah); |
| 2221 | |
Sujith | 7ea310b | 2009-09-03 12:08:43 +0530 | [diff] [blame] | 2222 | REG_WRITE(ah, AR_RX_FILTER, bits); |
| 2223 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2224 | phybits = 0; |
| 2225 | if (bits & ATH9K_RX_FILTER_PHYRADAR) |
| 2226 | phybits |= AR_PHY_ERR_RADAR; |
| 2227 | if (bits & ATH9K_RX_FILTER_PHYERR) |
| 2228 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; |
| 2229 | REG_WRITE(ah, AR_PHY_ERR, phybits); |
| 2230 | |
| 2231 | if (phybits) |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 2232 | REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2233 | else |
Felix Fietkau | ca7a4de | 2011-03-23 20:57:26 +0100 | [diff] [blame] | 2234 | REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 2235 | |
| 2236 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2237 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2238 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2239 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2240 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2241 | { |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 2242 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
| 2243 | return false; |
| 2244 | |
| 2245 | ath9k_hw_init_pll(ah, NULL); |
| 2246 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2247 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2248 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2249 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2250 | bool ath9k_hw_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2251 | { |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 2252 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2253 | return false; |
| 2254 | |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 2255 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
| 2256 | return false; |
| 2257 | |
| 2258 | ath9k_hw_init_pll(ah, NULL); |
| 2259 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2260 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2261 | EXPORT_SYMBOL(ath9k_hw_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2262 | |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 2263 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2264 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2265 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2266 | struct ath9k_channel *chan = ah->curchan; |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 2267 | struct ieee80211_channel *channel = chan->chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2268 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2269 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2270 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 2271 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2272 | ath9k_regd_get_ctl(regulatory, chan), |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 2273 | channel->max_antenna_gain * 2, |
| 2274 | channel->max_power * 2, |
| 2275 | min((u32) MAX_RATE_POWER, |
Felix Fietkau | de40f31 | 2010-10-20 03:08:53 +0200 | [diff] [blame] | 2276 | (u32) regulatory->power_limit), test); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2277 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2278 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2279 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2280 | void ath9k_hw_setopmode(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2281 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2282 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2283 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2284 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2285 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2286 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2287 | { |
| 2288 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
| 2289 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); |
| 2290 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2291 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2292 | |
Luis R. Rodriguez | f2b2143 | 2009-09-10 08:50:20 -0700 | [diff] [blame] | 2293 | void ath9k_hw_write_associd(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2294 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 2295 | struct ath_common *common = ath9k_hw_common(ah); |
| 2296 | |
| 2297 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); |
| 2298 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | |
| 2299 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2300 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2301 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2302 | |
Benoit Papillault | 1c0fc65 | 2010-04-16 00:07:26 +0200 | [diff] [blame] | 2303 | #define ATH9K_MAX_TSF_READ 10 |
| 2304 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2305 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2306 | { |
Benoit Papillault | 1c0fc65 | 2010-04-16 00:07:26 +0200 | [diff] [blame] | 2307 | u32 tsf_lower, tsf_upper1, tsf_upper2; |
| 2308 | int i; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2309 | |
Benoit Papillault | 1c0fc65 | 2010-04-16 00:07:26 +0200 | [diff] [blame] | 2310 | tsf_upper1 = REG_READ(ah, AR_TSF_U32); |
| 2311 | for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { |
| 2312 | tsf_lower = REG_READ(ah, AR_TSF_L32); |
| 2313 | tsf_upper2 = REG_READ(ah, AR_TSF_U32); |
| 2314 | if (tsf_upper2 == tsf_upper1) |
| 2315 | break; |
| 2316 | tsf_upper1 = tsf_upper2; |
| 2317 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2318 | |
Benoit Papillault | 1c0fc65 | 2010-04-16 00:07:26 +0200 | [diff] [blame] | 2319 | WARN_ON( i == ATH9K_MAX_TSF_READ ); |
| 2320 | |
| 2321 | return (((u64)tsf_upper1 << 32) | tsf_lower); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2322 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2323 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2324 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2325 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2326 | { |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2327 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
Alina Friedrichsen | b9a1619 | 2009-03-02 23:28:38 +0100 | [diff] [blame] | 2328 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2329 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2330 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2331 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2332 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2333 | { |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 2334 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
| 2335 | AH_TSF_WRITE_TIMEOUT)) |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2336 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 2337 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 2338 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2339 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2340 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2341 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2342 | |
Sujith | 54e4cec | 2009-08-07 09:45:09 +0530 | [diff] [blame] | 2343 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2344 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2345 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2346 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2347 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2348 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2349 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2350 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2351 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2352 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2353 | { |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2354 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2355 | u32 macmode; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2356 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2357 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2358 | macmode = AR_2040_JOINED_RX_CLEAR; |
| 2359 | else |
| 2360 | macmode = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2361 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2362 | REG_WRITE(ah, AR_2040_MODE, macmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2363 | } |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2364 | |
| 2365 | /* HW Generic timers configuration */ |
| 2366 | |
| 2367 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = |
| 2368 | { |
| 2369 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2370 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2371 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2372 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2373 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2374 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2375 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2376 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2377 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, |
| 2378 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, |
| 2379 | AR_NDP2_TIMER_MODE, 0x0002}, |
| 2380 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, |
| 2381 | AR_NDP2_TIMER_MODE, 0x0004}, |
| 2382 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, |
| 2383 | AR_NDP2_TIMER_MODE, 0x0008}, |
| 2384 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, |
| 2385 | AR_NDP2_TIMER_MODE, 0x0010}, |
| 2386 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, |
| 2387 | AR_NDP2_TIMER_MODE, 0x0020}, |
| 2388 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, |
| 2389 | AR_NDP2_TIMER_MODE, 0x0040}, |
| 2390 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, |
| 2391 | AR_NDP2_TIMER_MODE, 0x0080} |
| 2392 | }; |
| 2393 | |
| 2394 | /* HW generic timer primitives */ |
| 2395 | |
| 2396 | /* compute and clear index of rightmost 1 */ |
| 2397 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) |
| 2398 | { |
| 2399 | u32 b; |
| 2400 | |
| 2401 | b = *mask; |
| 2402 | b &= (0-b); |
| 2403 | *mask &= ~b; |
| 2404 | b *= debruijn32; |
| 2405 | b >>= 27; |
| 2406 | |
| 2407 | return timer_table->gen_timer_index[b]; |
| 2408 | } |
| 2409 | |
Felix Fietkau | dd347f2 | 2011-03-22 21:54:17 +0100 | [diff] [blame] | 2410 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2411 | { |
| 2412 | return REG_READ(ah, AR_TSF_L32); |
| 2413 | } |
Felix Fietkau | dd347f2 | 2011-03-22 21:54:17 +0100 | [diff] [blame] | 2414 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2415 | |
| 2416 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
| 2417 | void (*trigger)(void *), |
| 2418 | void (*overflow)(void *), |
| 2419 | void *arg, |
| 2420 | u8 timer_index) |
| 2421 | { |
| 2422 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2423 | struct ath_gen_timer *timer; |
| 2424 | |
| 2425 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); |
| 2426 | |
| 2427 | if (timer == NULL) { |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 2428 | ath_err(ath9k_hw_common(ah), |
| 2429 | "Failed to allocate memory for hw timer[%d]\n", |
| 2430 | timer_index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2431 | return NULL; |
| 2432 | } |
| 2433 | |
| 2434 | /* allocate a hardware generic timer slot */ |
| 2435 | timer_table->timers[timer_index] = timer; |
| 2436 | timer->index = timer_index; |
| 2437 | timer->trigger = trigger; |
| 2438 | timer->overflow = overflow; |
| 2439 | timer->arg = arg; |
| 2440 | |
| 2441 | return timer; |
| 2442 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2443 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2444 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 2445 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
| 2446 | struct ath_gen_timer *timer, |
Vasanthakumar Thiagarajan | 788f687 | 2011-04-21 18:33:27 +0530 | [diff] [blame] | 2447 | u32 trig_timeout, |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 2448 | u32 timer_period) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2449 | { |
| 2450 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
Vasanthakumar Thiagarajan | 788f687 | 2011-04-21 18:33:27 +0530 | [diff] [blame] | 2451 | u32 tsf, timer_next; |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2452 | |
| 2453 | BUG_ON(!timer_period); |
| 2454 | |
| 2455 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); |
| 2456 | |
| 2457 | tsf = ath9k_hw_gettsf32(ah); |
| 2458 | |
Vasanthakumar Thiagarajan | 788f687 | 2011-04-21 18:33:27 +0530 | [diff] [blame] | 2459 | timer_next = tsf + trig_timeout; |
| 2460 | |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2461 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
| 2462 | "current tsf %x period %x timer_next %x\n", |
| 2463 | tsf, timer_period, timer_next); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2464 | |
| 2465 | /* |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2466 | * Program generic timer registers |
| 2467 | */ |
| 2468 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, |
| 2469 | timer_next); |
| 2470 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, |
| 2471 | timer_period); |
| 2472 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 2473 | gen_tmr_configuration[timer->index].mode_mask); |
| 2474 | |
| 2475 | /* Enable both trigger and thresh interrupt masks */ |
| 2476 | REG_SET_BIT(ah, AR_IMR_S5, |
| 2477 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 2478 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2479 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2480 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2481 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 2482 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2483 | { |
| 2484 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2485 | |
| 2486 | if ((timer->index < AR_FIRST_NDP_TIMER) || |
| 2487 | (timer->index >= ATH_MAX_GEN_TIMER)) { |
| 2488 | return; |
| 2489 | } |
| 2490 | |
| 2491 | /* Clear generic timer enable bits. */ |
| 2492 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 2493 | gen_tmr_configuration[timer->index].mode_mask); |
| 2494 | |
| 2495 | /* Disable both trigger and thresh interrupt masks */ |
| 2496 | REG_CLR_BIT(ah, AR_IMR_S5, |
| 2497 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 2498 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
| 2499 | |
| 2500 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2501 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2502 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2503 | |
| 2504 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) |
| 2505 | { |
| 2506 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2507 | |
| 2508 | /* free the hardware generic timer slot */ |
| 2509 | timer_table->timers[timer->index] = NULL; |
| 2510 | kfree(timer); |
| 2511 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2512 | EXPORT_SYMBOL(ath_gen_timer_free); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2513 | |
| 2514 | /* |
| 2515 | * Generic Timer Interrupts handling |
| 2516 | */ |
| 2517 | void ath_gen_timer_isr(struct ath_hw *ah) |
| 2518 | { |
| 2519 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2520 | struct ath_gen_timer *timer; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2521 | struct ath_common *common = ath9k_hw_common(ah); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2522 | u32 trigger_mask, thresh_mask, index; |
| 2523 | |
| 2524 | /* get hardware generic timer interrupt status */ |
| 2525 | trigger_mask = ah->intr_gen_timer_trigger; |
| 2526 | thresh_mask = ah->intr_gen_timer_thresh; |
| 2527 | trigger_mask &= timer_table->timer_mask.val; |
| 2528 | thresh_mask &= timer_table->timer_mask.val; |
| 2529 | |
| 2530 | trigger_mask &= ~thresh_mask; |
| 2531 | |
| 2532 | while (thresh_mask) { |
| 2533 | index = rightmost_index(timer_table, &thresh_mask); |
| 2534 | timer = timer_table->timers[index]; |
| 2535 | BUG_ON(!timer); |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2536 | ath_dbg(common, ATH_DBG_HWTIMER, |
| 2537 | "TSF overflow for Gen timer %d\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2538 | timer->overflow(timer->arg); |
| 2539 | } |
| 2540 | |
| 2541 | while (trigger_mask) { |
| 2542 | index = rightmost_index(timer_table, &trigger_mask); |
| 2543 | timer = timer_table->timers[index]; |
| 2544 | BUG_ON(!timer); |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2545 | ath_dbg(common, ATH_DBG_HWTIMER, |
| 2546 | "Gen timer[%d] trigger\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2547 | timer->trigger(timer->arg); |
| 2548 | } |
| 2549 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2550 | EXPORT_SYMBOL(ath_gen_timer_isr); |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2551 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 2552 | /********/ |
| 2553 | /* HTC */ |
| 2554 | /********/ |
| 2555 | |
| 2556 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) |
| 2557 | { |
| 2558 | ah->htc_reset_init = true; |
| 2559 | } |
| 2560 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); |
| 2561 | |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2562 | static struct { |
| 2563 | u32 version; |
| 2564 | const char * name; |
| 2565 | } ath_mac_bb_names[] = { |
| 2566 | /* Devices with external radios */ |
| 2567 | { AR_SREV_VERSION_5416_PCI, "5416" }, |
| 2568 | { AR_SREV_VERSION_5416_PCIE, "5418" }, |
| 2569 | { AR_SREV_VERSION_9100, "9100" }, |
| 2570 | { AR_SREV_VERSION_9160, "9160" }, |
| 2571 | /* Single-chip solutions */ |
| 2572 | { AR_SREV_VERSION_9280, "9280" }, |
| 2573 | { AR_SREV_VERSION_9285, "9285" }, |
Luis R. Rodriguez | 1115847 | 2009-10-27 12:59:35 -0400 | [diff] [blame] | 2574 | { AR_SREV_VERSION_9287, "9287" }, |
| 2575 | { AR_SREV_VERSION_9271, "9271" }, |
Luis R. Rodriguez | ec83903 | 2010-04-15 17:39:20 -0400 | [diff] [blame] | 2576 | { AR_SREV_VERSION_9300, "9300" }, |
Senthil Balasubramanian | 8f06ca2 | 2011-04-01 17:16:33 +0530 | [diff] [blame] | 2577 | { AR_SREV_VERSION_9485, "9485" }, |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2578 | }; |
| 2579 | |
| 2580 | /* For devices with external radios */ |
| 2581 | static struct { |
| 2582 | u16 version; |
| 2583 | const char * name; |
| 2584 | } ath_rf_names[] = { |
| 2585 | { 0, "5133" }, |
| 2586 | { AR_RAD5133_SREV_MAJOR, "5133" }, |
| 2587 | { AR_RAD5122_SREV_MAJOR, "5122" }, |
| 2588 | { AR_RAD2133_SREV_MAJOR, "2133" }, |
| 2589 | { AR_RAD2122_SREV_MAJOR, "2122" } |
| 2590 | }; |
| 2591 | |
| 2592 | /* |
| 2593 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. |
| 2594 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2595 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2596 | { |
| 2597 | int i; |
| 2598 | |
| 2599 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { |
| 2600 | if (ath_mac_bb_names[i].version == mac_bb_version) { |
| 2601 | return ath_mac_bb_names[i].name; |
| 2602 | } |
| 2603 | } |
| 2604 | |
| 2605 | return "????"; |
| 2606 | } |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2607 | |
| 2608 | /* |
| 2609 | * Return the RF name. "????" is returned if the RF is unknown. |
| 2610 | * Used for devices with external radios. |
| 2611 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2612 | static const char *ath9k_hw_rf_name(u16 rf_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2613 | { |
| 2614 | int i; |
| 2615 | |
| 2616 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { |
| 2617 | if (ath_rf_names[i].version == rf_version) { |
| 2618 | return ath_rf_names[i].name; |
| 2619 | } |
| 2620 | } |
| 2621 | |
| 2622 | return "????"; |
| 2623 | } |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2624 | |
| 2625 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) |
| 2626 | { |
| 2627 | int used; |
| 2628 | |
| 2629 | /* chipsets >= AR9280 are single-chip */ |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 2630 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2631 | used = snprintf(hw_name, len, |
| 2632 | "Atheros AR%s Rev:%x", |
| 2633 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 2634 | ah->hw_version.macRev); |
| 2635 | } |
| 2636 | else { |
| 2637 | used = snprintf(hw_name, len, |
| 2638 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", |
| 2639 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 2640 | ah->hw_version.macRev, |
| 2641 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & |
| 2642 | AR_RADIO_SREV_MAJOR)), |
| 2643 | ah->hw_version.phyRev); |
| 2644 | } |
| 2645 | |
| 2646 | hw_name[used] = '\0'; |
| 2647 | } |
| 2648 | EXPORT_SYMBOL(ath9k_hw_name); |