| Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * prcm.h - Access definations for use in OMAP24XX clock and power management |
| 3 | * |
| 4 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | #ifndef __ASM_ARM_ARCH_DPM_PRCM_H |
| 22 | #define __ASM_ARM_ARCH_DPM_PRCM_H |
| 23 | |
| 24 | /* SET_PERFORMANCE_LEVEL PARAMETERS */ |
| 25 | #define PRCM_HALF_SPEED 1 |
| 26 | #define PRCM_FULL_SPEED 2 |
| 27 | |
| 28 | #ifndef __ASSEMBLER__ |
| 29 | |
| 30 | #define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset)) |
| 31 | |
| 32 | #define PRCM_REVISION PRCM_REG32(0x000) |
| 33 | #define PRCM_SYSCONFIG PRCM_REG32(0x010) |
| 34 | #define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018) |
| 35 | #define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C) |
| 36 | #define PRCM_VOLTCTRL PRCM_REG32(0x050) |
| 37 | #define PRCM_VOLTST PRCM_REG32(0x054) |
| 38 | #define PRCM_CLKSRC_CTRL PRCM_REG32(0x060) |
| 39 | #define PRCM_CLKOUT_CTRL PRCM_REG32(0x070) |
| 40 | #define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078) |
| 41 | #define PRCM_CLKCFG_CTRL PRCM_REG32(0x080) |
| 42 | #define PRCM_CLKCFG_STATUS PRCM_REG32(0x084) |
| 43 | #define PRCM_VOLTSETUP PRCM_REG32(0x090) |
| 44 | #define PRCM_CLKSSETUP PRCM_REG32(0x094) |
| 45 | #define PRCM_POLCTRL PRCM_REG32(0x098) |
| 46 | |
| 47 | /* GENERAL PURPOSE */ |
| 48 | #define GENERAL_PURPOSE1 PRCM_REG32(0x0B0) |
| 49 | #define GENERAL_PURPOSE2 PRCM_REG32(0x0B4) |
| 50 | #define GENERAL_PURPOSE3 PRCM_REG32(0x0B8) |
| 51 | #define GENERAL_PURPOSE4 PRCM_REG32(0x0BC) |
| 52 | #define GENERAL_PURPOSE5 PRCM_REG32(0x0C0) |
| 53 | #define GENERAL_PURPOSE6 PRCM_REG32(0x0C4) |
| 54 | #define GENERAL_PURPOSE7 PRCM_REG32(0x0C8) |
| 55 | #define GENERAL_PURPOSE8 PRCM_REG32(0x0CC) |
| 56 | #define GENERAL_PURPOSE9 PRCM_REG32(0x0D0) |
| 57 | #define GENERAL_PURPOSE10 PRCM_REG32(0x0D4) |
| 58 | #define GENERAL_PURPOSE11 PRCM_REG32(0x0D8) |
| 59 | #define GENERAL_PURPOSE12 PRCM_REG32(0x0DC) |
| 60 | #define GENERAL_PURPOSE13 PRCM_REG32(0x0E0) |
| 61 | #define GENERAL_PURPOSE14 PRCM_REG32(0x0E4) |
| 62 | #define GENERAL_PURPOSE15 PRCM_REG32(0x0E8) |
| 63 | #define GENERAL_PURPOSE16 PRCM_REG32(0x0EC) |
| 64 | #define GENERAL_PURPOSE17 PRCM_REG32(0x0F0) |
| 65 | #define GENERAL_PURPOSE18 PRCM_REG32(0x0F4) |
| 66 | #define GENERAL_PURPOSE19 PRCM_REG32(0x0F8) |
| 67 | #define GENERAL_PURPOSE20 PRCM_REG32(0x0FC) |
| 68 | |
| 69 | /* MPU */ |
| 70 | #define CM_CLKSEL_MPU PRCM_REG32(0x140) |
| 71 | #define CM_CLKSTCTRL_MPU PRCM_REG32(0x148) |
| 72 | #define RM_RSTST_MPU PRCM_REG32(0x158) |
| 73 | #define PM_WKDEP_MPU PRCM_REG32(0x1C8) |
| 74 | #define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4) |
| 75 | #define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8) |
| 76 | #define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC) |
| 77 | #define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0) |
| 78 | #define PM_PWSTST_MPU PRCM_REG32(0x1E4) |
| 79 | |
| 80 | /* CORE */ |
| 81 | #define CM_FCLKEN1_CORE PRCM_REG32(0x200) |
| 82 | #define CM_FCLKEN2_CORE PRCM_REG32(0x204) |
| 83 | #define CM_FCLKEN3_CORE PRCM_REG32(0x208) |
| 84 | #define CM_ICLKEN1_CORE PRCM_REG32(0x210) |
| 85 | #define CM_ICLKEN2_CORE PRCM_REG32(0x214) |
| 86 | #define CM_ICLKEN3_CORE PRCM_REG32(0x218) |
| 87 | #define CM_ICLKEN4_CORE PRCM_REG32(0x21C) |
| 88 | #define CM_IDLEST1_CORE PRCM_REG32(0x220) |
| 89 | #define CM_IDLEST2_CORE PRCM_REG32(0x224) |
| 90 | #define CM_IDLEST3_CORE PRCM_REG32(0x228) |
| 91 | #define CM_IDLEST4_CORE PRCM_REG32(0x22C) |
| 92 | #define CM_AUTOIDLE1_CORE PRCM_REG32(0x230) |
| 93 | #define CM_AUTOIDLE2_CORE PRCM_REG32(0x234) |
| 94 | #define CM_AUTOIDLE3_CORE PRCM_REG32(0x238) |
| 95 | #define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C) |
| 96 | #define CM_CLKSEL1_CORE PRCM_REG32(0x240) |
| 97 | #define CM_CLKSEL2_CORE PRCM_REG32(0x244) |
| 98 | #define CM_CLKSTCTRL_CORE PRCM_REG32(0x248) |
| 99 | #define PM_WKEN1_CORE PRCM_REG32(0x2A0) |
| 100 | #define PM_WKEN2_CORE PRCM_REG32(0x2A4) |
| 101 | #define PM_WKST1_CORE PRCM_REG32(0x2B0) |
| 102 | #define PM_WKST2_CORE PRCM_REG32(0x2B4) |
| 103 | #define PM_WKDEP_CORE PRCM_REG32(0x2C8) |
| 104 | #define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0) |
| 105 | #define PM_PWSTST_CORE PRCM_REG32(0x2E4) |
| 106 | |
| 107 | /* GFX */ |
| 108 | #define CM_FCLKEN_GFX PRCM_REG32(0x300) |
| 109 | #define CM_ICLKEN_GFX PRCM_REG32(0x310) |
| 110 | #define CM_IDLEST_GFX PRCM_REG32(0x320) |
| 111 | #define CM_CLKSEL_GFX PRCM_REG32(0x340) |
| 112 | #define CM_CLKSTCTRL_GFX PRCM_REG32(0x348) |
| 113 | #define RM_RSTCTRL_GFX PRCM_REG32(0x350) |
| 114 | #define RM_RSTST_GFX PRCM_REG32(0x358) |
| 115 | #define PM_WKDEP_GFX PRCM_REG32(0x3C8) |
| 116 | #define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0) |
| 117 | #define PM_PWSTST_GFX PRCM_REG32(0x3E4) |
| 118 | |
| 119 | /* WAKE-UP */ |
| 120 | #define CM_FCLKEN_WKUP PRCM_REG32(0x400) |
| 121 | #define CM_ICLKEN_WKUP PRCM_REG32(0x410) |
| 122 | #define CM_IDLEST_WKUP PRCM_REG32(0x420) |
| 123 | #define CM_AUTOIDLE_WKUP PRCM_REG32(0x430) |
| 124 | #define CM_CLKSEL_WKUP PRCM_REG32(0x440) |
| 125 | #define RM_RSTCTRL_WKUP PRCM_REG32(0x450) |
| 126 | #define RM_RSTTIME_WKUP PRCM_REG32(0x454) |
| 127 | #define RM_RSTST_WKUP PRCM_REG32(0x458) |
| 128 | #define PM_WKEN_WKUP PRCM_REG32(0x4A0) |
| 129 | #define PM_WKST_WKUP PRCM_REG32(0x4B0) |
| 130 | |
| 131 | /* CLOCKS */ |
| 132 | #define CM_CLKEN_PLL PRCM_REG32(0x500) |
| 133 | #define CM_IDLEST_CKGEN PRCM_REG32(0x520) |
| 134 | #define CM_AUTOIDLE_PLL PRCM_REG32(0x530) |
| 135 | #define CM_CLKSEL1_PLL PRCM_REG32(0x540) |
| 136 | #define CM_CLKSEL2_PLL PRCM_REG32(0x544) |
| 137 | |
| 138 | /* DSP */ |
| 139 | #define CM_FCLKEN_DSP PRCM_REG32(0x800) |
| 140 | #define CM_ICLKEN_DSP PRCM_REG32(0x810) |
| 141 | #define CM_IDLEST_DSP PRCM_REG32(0x820) |
| 142 | #define CM_AUTOIDLE_DSP PRCM_REG32(0x830) |
| 143 | #define CM_CLKSEL_DSP PRCM_REG32(0x840) |
| 144 | #define CM_CLKSTCTRL_DSP PRCM_REG32(0x848) |
| 145 | #define RM_RSTCTRL_DSP PRCM_REG32(0x850) |
| 146 | #define RM_RSTST_DSP PRCM_REG32(0x858) |
| 147 | #define PM_WKEN_DSP PRCM_REG32(0x8A0) |
| 148 | #define PM_WKDEP_DSP PRCM_REG32(0x8C8) |
| 149 | #define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0) |
| 150 | #define PM_PWSTST_DSP PRCM_REG32(0x8E4) |
| 151 | #define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0) |
| 152 | #define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4) |
| 153 | |
| 154 | /* IVA */ |
| 155 | #define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8) |
| 156 | #define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC) |
| 157 | |
| 158 | /* Modem on 2430 */ |
| 159 | #define CM_FCLKEN_MDM PRCM_REG32(0xC00) |
| 160 | #define CM_ICLKEN_MDM PRCM_REG32(0xC10) |
| 161 | #define CM_IDLEST_MDM PRCM_REG32(0xC20) |
| 162 | #define CM_CLKSEL_MDM PRCM_REG32(0xC40) |
| 163 | |
| 164 | /* FIXME: Move to header for 2430 */ |
| 165 | #define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000) |
| 166 | #define DISP_REG32(offset) __REG32(DISP_BASE + (offset)) |
| 167 | |
| 168 | #define GPMC_BASE (OMAP24XX_GPMC_BASE) |
| 169 | #define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset)) |
| 170 | |
| 171 | #define GPT1_BASE (OMAP24XX_GPT1) |
| 172 | #define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset)) |
| 173 | |
| 174 | /* Misc sysconfig */ |
| 175 | #define DISPC_SYSCONFIG DISP_REG32(0x410) |
| 176 | #define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000) |
| 177 | #define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10) |
| 178 | #define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10) |
| 179 | |
| 180 | //#define DSP_MMU_SYSCONFIG 0x5A000010 |
| 181 | #define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10) |
| 182 | //#define IVA_MMU_SYSCONFIG 0x5D000010 |
| 183 | //#define DSP_DMA_SYSCONFIG 0x00FCC02C |
| 184 | #define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C) |
| 185 | #define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C) |
| 186 | #define GPMC_SYSCONFIG GPMC_REG32(0x010) |
| 187 | #define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010) |
| 188 | #define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054) |
| 189 | #define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054) |
| 190 | #define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054) |
| 191 | //#define IVA_SYSCONFIG 0x5C060010 |
| 192 | #define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10) |
| 193 | #define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10) |
| 194 | #define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010) |
| 195 | //#define VLYNQ_SYSCONFIG 0x67FFFE10 |
| 196 | |
| 197 | /* rkw - good cannidates for PM_ to start what nm was trying */ |
| 198 | #define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) |
| 199 | #define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) |
| 200 | #define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) |
| 201 | #define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) |
| 202 | #define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) |
| 203 | #define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) |
| 204 | #define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) |
| 205 | #define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) |
| 206 | #define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) |
| 207 | #define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) |
| 208 | #define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000) |
| 209 | |
| 210 | #define GPTIMER1_SYSCONFIG GPT1_REG32(0x010) |
| 211 | #define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10) |
| 212 | #define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10) |
| 213 | #define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10) |
| 214 | #define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10) |
| 215 | #define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10) |
| 216 | #define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10) |
| 217 | #define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10) |
| 218 | #define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10) |
| 219 | #define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10) |
| 220 | #define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10) |
| 221 | #define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10) |
| 222 | |
| 223 | #define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1))) |
| 224 | |
| 225 | #define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10)) |
| 226 | #define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10)) |
| 227 | #define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10)) |
| 228 | #define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10)) |
| 229 | |
| 230 | /* GP TIMER 1 */ |
| 231 | #define GPTIMER1_TISTAT GPT1_REG32(0x014) |
| 232 | #define GPTIMER1_TISR GPT1_REG32(0x018) |
| 233 | #define GPTIMER1_TIER GPT1_REG32(0x01C) |
| 234 | #define GPTIMER1_TWER GPT1_REG32(0x020) |
| 235 | #define GPTIMER1_TCLR GPT1_REG32(0x024) |
| 236 | #define GPTIMER1_TCRR GPT1_REG32(0x028) |
| 237 | #define GPTIMER1_TLDR GPT1_REG32(0x02C) |
| 238 | #define GPTIMER1_TTGR GPT1_REG32(0x030) |
| 239 | #define GPTIMER1_TWPS GPT1_REG32(0x034) |
| 240 | #define GPTIMER1_TMAR GPT1_REG32(0x038) |
| 241 | #define GPTIMER1_TCAR1 GPT1_REG32(0x03C) |
| 242 | #define GPTIMER1_TSICR GPT1_REG32(0x040) |
| 243 | #define GPTIMER1_TCAR2 GPT1_REG32(0x044) |
| 244 | |
| 245 | /* rkw -- base fix up please... */ |
| 246 | #define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018) |
| 247 | |
| 248 | /* SDRC */ |
| 249 | #define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060) |
| 250 | #define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064) |
| 251 | #define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068) |
| 252 | #define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C) |
| 253 | #define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070) |
| 254 | #define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084) |
| 255 | |
| 256 | /* GPIO 1 */ |
| 257 | #define GPIO1_BASE GPIOX_BASE(1) |
| 258 | #define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset)) |
| 259 | #define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C) |
| 260 | #define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018) |
| 261 | #define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C) |
| 262 | #define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028) |
| 263 | #define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020) |
| 264 | #define GPIO1_RISINGDETECT GPIO1_REG32(0x048) |
| 265 | #define GPIO1_DATAIN GPIO1_REG32(0x038) |
| 266 | #define GPIO1_OE GPIO1_REG32(0x034) |
| 267 | #define GPIO1_DATAOUT GPIO1_REG32(0x03C) |
| 268 | |
| 269 | /* GPIO2 */ |
| 270 | #define GPIO2_BASE GPIOX_BASE(2) |
| 271 | #define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset)) |
| 272 | #define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C) |
| 273 | #define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018) |
| 274 | #define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C) |
| 275 | #define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028) |
| 276 | #define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020) |
| 277 | #define GPIO2_RISINGDETECT GPIO2_REG32(0x048) |
| 278 | #define GPIO2_DATAIN GPIO2_REG32(0x038) |
| 279 | #define GPIO2_OE GPIO2_REG32(0x034) |
| 280 | #define GPIO2_DATAOUT GPIO2_REG32(0x03C) |
| 281 | |
| 282 | /* GPIO 3 */ |
| 283 | #define GPIO3_BASE GPIOX_BASE(3) |
| 284 | #define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset)) |
| 285 | #define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C) |
| 286 | #define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018) |
| 287 | #define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C) |
| 288 | #define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028) |
| 289 | #define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020) |
| 290 | #define GPIO3_RISINGDETECT GPIO3_REG32(0x048) |
| 291 | #define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C) |
| 292 | #define GPIO3_DATAIN GPIO3_REG32(0x038) |
| 293 | #define GPIO3_OE GPIO3_REG32(0x034) |
| 294 | #define GPIO3_DATAOUT GPIO3_REG32(0x03C) |
| 295 | #define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) |
| 296 | #define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) |
| 297 | |
| 298 | /* GPIO 4 */ |
| 299 | #define GPIO4_BASE GPIOX_BASE(4) |
| 300 | #define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset)) |
| 301 | #define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C) |
| 302 | #define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018) |
| 303 | #define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C) |
| 304 | #define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028) |
| 305 | #define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020) |
| 306 | #define GPIO4_RISINGDETECT GPIO4_REG32(0x048) |
| 307 | #define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C) |
| 308 | #define GPIO4_DATAIN GPIO4_REG32(0x038) |
| 309 | #define GPIO4_OE GPIO4_REG32(0x034) |
| 310 | #define GPIO4_DATAOUT GPIO4_REG32(0x03C) |
| 311 | #define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050) |
| 312 | #define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054) |
| 313 | |
| 314 | |
| 315 | /* IO CONFIG */ |
| 316 | #define CONTROL_BASE (OMAP24XX_CTRL_BASE) |
| 317 | #define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset)) |
| 318 | |
| 319 | #define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104) |
| 320 | #define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134) |
| 321 | #define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8) |
| 322 | #define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C) |
| 323 | #define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090) |
| 324 | #define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8) |
| 325 | #define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) |
| 326 | #define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0) |
| 327 | #define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC) |
| 328 | |
| 329 | /* CONTROL */ |
| 330 | #define CONTROL_DEVCONF CONTROL_REG32(0x274) |
| 331 | |
| 332 | /* INTERRUPT CONTROLLER */ |
| 333 | #define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000) |
| 334 | #define INTC_REG32(offset) __REG32(INTC_BASE + (offset)) |
| 335 | |
| 336 | #define INTC1_U_BASE INTC_REG32(0x000) |
| 337 | #define INTC_MIR0 INTC_REG32(0x084) |
| 338 | #define INTC_MIR_SET0 INTC_REG32(0x08C) |
| 339 | #define INTC_MIR_CLEAR0 INTC_REG32(0x088) |
| 340 | #define INTC_ISR_CLEAR0 INTC_REG32(0x094) |
| 341 | #define INTC_MIR1 INTC_REG32(0x0A4) |
| 342 | #define INTC_MIR_SET1 INTC_REG32(0x0AC) |
| 343 | #define INTC_MIR_CLEAR1 INTC_REG32(0x0A8) |
| 344 | #define INTC_ISR_CLEAR1 INTC_REG32(0x0B4) |
| 345 | #define INTC_MIR2 INTC_REG32(0x0C4) |
| 346 | #define INTC_MIR_SET2 INTC_REG32(0x0CC) |
| 347 | #define INTC_MIR_CLEAR2 INTC_REG32(0x0C8) |
| 348 | #define INTC_ISR_CLEAR2 INTC_REG32(0x0D4) |
| 349 | #define INTC_SIR_IRQ INTC_REG32(0x040) |
| 350 | #define INTC_CONTROL INTC_REG32(0x048) |
| 351 | #define INTC_ILR11 INTC_REG32(0x12C) |
| 352 | #define INTC_ILR32 INTC_REG32(0x180) |
| 353 | #define INTC_ILR37 INTC_REG32(0x194) |
| 354 | #define INTC_SYSCONFIG INTC_REG32(0x010) |
| 355 | |
| 356 | /* RAM FIREWALL */ |
| 357 | #define RAMFW_BASE (0x68005000) |
| 358 | #define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset)) |
| 359 | |
| 360 | #define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048) |
| 361 | #define RAMFW_READPERM0 RAMFW_REG32(0x050) |
| 362 | #define RAMFW_WRITEPERM0 RAMFW_REG32(0x058) |
| 363 | |
| 364 | /* GPMC CS1 FPGA ON USER INTERFACE MODULE */ |
| 365 | //#define DEBUG_BOARD_LED_REGISTER 0x04000014 |
| 366 | |
| 367 | /* GPMC CS0 */ |
| 368 | #define GPMC_CONFIG1_0 GPMC_REG32(0x060) |
| 369 | #define GPMC_CONFIG2_0 GPMC_REG32(0x064) |
| 370 | #define GPMC_CONFIG3_0 GPMC_REG32(0x068) |
| 371 | #define GPMC_CONFIG4_0 GPMC_REG32(0x06C) |
| 372 | #define GPMC_CONFIG5_0 GPMC_REG32(0x070) |
| 373 | #define GPMC_CONFIG6_0 GPMC_REG32(0x074) |
| 374 | #define GPMC_CONFIG7_0 GPMC_REG32(0x078) |
| 375 | |
| 376 | /* DSS */ |
| 377 | #define DSS_CONTROL DISP_REG32(0x040) |
| 378 | #define DISPC_CONTROL DISP_REG32(0x440) |
| 379 | #define DISPC_SYSSTATUS DISP_REG32(0x414) |
| 380 | #define DISPC_IRQSTATUS DISP_REG32(0x418) |
| 381 | #define DISPC_IRQENABLE DISP_REG32(0x41C) |
| 382 | #define DISPC_CONFIG DISP_REG32(0x444) |
| 383 | #define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C) |
| 384 | #define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450) |
| 385 | #define DISPC_TRANS_COLOR0 DISP_REG32(0x454) |
| 386 | #define DISPC_TRANS_COLOR1 DISP_REG32(0x458) |
| 387 | #define DISPC_LINE_NUMBER DISP_REG32(0x460) |
| 388 | #define DISPC_TIMING_H DISP_REG32(0x464) |
| 389 | #define DISPC_TIMING_V DISP_REG32(0x468) |
| 390 | #define DISPC_POL_FREQ DISP_REG32(0x46C) |
| 391 | #define DISPC_DIVISOR DISP_REG32(0x470) |
| 392 | #define DISPC_SIZE_DIG DISP_REG32(0x478) |
| 393 | #define DISPC_SIZE_LCD DISP_REG32(0x47C) |
| 394 | #define DISPC_GFX_BA0 DISP_REG32(0x480) |
| 395 | #define DISPC_GFX_BA1 DISP_REG32(0x484) |
| 396 | #define DISPC_GFX_POSITION DISP_REG32(0x488) |
| 397 | #define DISPC_GFX_SIZE DISP_REG32(0x48C) |
| 398 | #define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0) |
| 399 | #define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4) |
| 400 | #define DISPC_GFX_ROW_INC DISP_REG32(0x4AC) |
| 401 | #define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0) |
| 402 | #define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4) |
| 403 | #define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8) |
| 404 | #define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4) |
| 405 | #define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8) |
| 406 | #define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC) |
| 407 | |
| 408 | /* Wake up define for board */ |
| 409 | #define GPIO97 (1 << 1) |
| 410 | #define GPIO88 (1 << 24) |
| 411 | |
| 412 | #endif /* __ASSEMBLER__ */ |
| 413 | |
| 414 | #endif |
| 415 | |
| 416 | |
| 417 | |
| 418 | |
| 419 | |