Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * BRIEF MODULE DESCRIPTION |
| 4 | * 4G Systems MTX-1 board setup. |
| 5 | * |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 6 | * Copyright 2003, 2008 MontaVista Software Inc. |
| 7 | * Author: MontaVista Software, Inc. <source@mvista.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * Bruno Randolf <bruno.randolf@4g-systems.biz> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License along |
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 29 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
Sergei Shtylyov | ce28f94 | 2008-04-23 22:43:55 +0400 | [diff] [blame] | 31 | #include <linux/init.h> |
| 32 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #include <asm/mach-au1x00/au1000.h> |
| 34 | |
Florian Fainelli | baa545f | 2007-03-02 22:07:48 +0100 | [diff] [blame] | 35 | extern int (*board_pci_idsel)(unsigned int devsel, int assert); |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 36 | int mtx1_pci_idsel(unsigned int devsel, int assert); |
Florian Fainelli | baa545f | 2007-03-02 22:07:48 +0100 | [diff] [blame] | 37 | |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 38 | void board_reset(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | { |
| 40 | /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ |
| 41 | au_writel(0x00000000, 0xAE00001C); |
| 42 | } |
| 43 | |
| 44 | void __init board_setup(void) |
| 45 | { |
Florian Fainelli | f708631 | 2007-09-25 17:07:24 +0200 | [diff] [blame] | 46 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 47 | /* Enable USB power switch */ |
| 48 | au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); |
| 49 | au_writel(0x100000, GPIO2_OUTPUT); |
Florian Fainelli | f708631 | 2007-09-25 17:07:24 +0200 | [diff] [blame] | 50 | #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
| 52 | #ifdef CONFIG_PCI |
| 53 | #if defined(__MIPSEB__) |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 54 | au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | #else |
| 56 | au_writel(0xf, Au1500_PCI_CFG); |
| 57 | #endif |
| 58 | #endif |
| 59 | |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 60 | /* Initialize sys_pinfunc */ |
| 61 | au_writel(SYS_PF_NI2, SYS_PINFUNC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 63 | /* Initialize GPIO */ |
| 64 | au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); |
| 65 | au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */ |
| 66 | au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */ |
| 67 | au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ |
| 68 | au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 70 | /* Enable LED and set it to green */ |
| 71 | au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR); |
| 72 | au_writel(0x18000800, GPIO2_OUTPUT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | |
Florian Fainelli | baa545f | 2007-03-02 22:07:48 +0100 | [diff] [blame] | 74 | board_pci_idsel = mtx1_pci_idsel; |
| 75 | |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 76 | printk(KERN_INFO "4G Systems MTX-1 Board\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | } |
Florian Fainelli | baa545f | 2007-03-02 22:07:48 +0100 | [diff] [blame] | 78 | |
| 79 | int |
| 80 | mtx1_pci_idsel(unsigned int devsel, int assert) |
| 81 | { |
| 82 | #define MTX_IDSEL_ONLY_0_AND_3 0 |
| 83 | #if MTX_IDSEL_ONLY_0_AND_3 |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 84 | if (devsel != 0 && devsel != 3) { |
| 85 | printk(KERN_ERR "*** not 0 or 3\n"); |
| 86 | return 0; |
| 87 | } |
Florian Fainelli | baa545f | 2007-03-02 22:07:48 +0100 | [diff] [blame] | 88 | #endif |
| 89 | |
Sergei Shtylyov | 1ff1a78 | 2008-04-30 23:30:12 +0400 | [diff] [blame^] | 90 | if (assert && devsel != 0) |
| 91 | /* Suppress signal to Cardbus */ |
| 92 | au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */ |
| 93 | else |
| 94 | au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ |
| 95 | au_sync_udelay(1); |
| 96 | return 1; |
Florian Fainelli | baa545f | 2007-03-02 22:07:48 +0100 | [diff] [blame] | 97 | } |
| 98 | |