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Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001/*
2 * include/linux/mfd/asic3.h
3 *
4 * Compaq ASIC3 headers.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
Samuel Ortiz3b26bf12008-06-20 11:09:51 +020011 * Copyright 2007-2008 OpenedHand Ltd.
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080012 */
13
14#ifndef __ASIC3_H__
15#define __ASIC3_H__
16
17#include <linux/types.h>
18
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080019struct asic3_platform_data {
Samuel Ortiz3b26bf12008-06-20 11:09:51 +020020 u16 *gpio_config;
21 unsigned int gpio_config_num;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080022
23 unsigned int bus_shift;
24
25 unsigned int irq_base;
26
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020027 unsigned int gpio_base;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080028};
29
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080030#define ASIC3_NUM_GPIO_BANKS 4
31#define ASIC3_GPIOS_PER_BANK 16
32#define ASIC3_NUM_GPIOS 64
33#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
34
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020035#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
36
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080037#define ASIC3_GPIO_BANK_A 0
38#define ASIC3_GPIO_BANK_B 1
39#define ASIC3_GPIO_BANK_C 2
40#define ASIC3_GPIO_BANK_D 3
41
42#define ASIC3_GPIO(bank, gpio) \
43 ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
44#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
45/* All offsets below are specified with this address bus shift */
46#define ASIC3_DEFAULT_ADDR_SHIFT 2
47
48#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg)
49#define ASIC3_GPIO_OFFSET(base, reg) \
50 (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg)
51
52#define ASIC3_GPIO_A_Base 0x0000
53#define ASIC3_GPIO_B_Base 0x0100
54#define ASIC3_GPIO_C_Base 0x0200
55#define ASIC3_GPIO_D_Base 0x0300
56
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020057#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
58#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
59 (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
60#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
61#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_Base + (((gpio) >> 4) * 0x0100))
62#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_Base + ((bank) * 0x100))
63
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080064#define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */
65#define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */
66#define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */
67#define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */
68#define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */
69#define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */
70#define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */
71#define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */
72#define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */
73#define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */
74#define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */
75#define ASIC3_GPIO_SleepConf 0x2c /*
76 * R/W bit 1: autosleep
77 * 0: disable gposlpout in normal mode,
78 * enable gposlpout in sleep mode.
79 */
80#define ASIC3_GPIO_Status 0x30 /* R Pin status */
81
Samuel Ortiz3b26bf12008-06-20 11:09:51 +020082/*
83 * ASIC3 GPIO config
84 *
85 * Bits 0..6 gpio number
86 * Bits 7..13 Alternate function
87 * Bit 14 Direction
88 * Bit 15 Initial value
89 *
90 */
91#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
92#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
93#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
94#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
95#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
96 | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
97 | (((init) & 0x1) << 15))
98#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
99 ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
100#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
101 ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
102
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800103#define ASIC3_SPI_Base 0x0400
104#define ASIC3_SPI_Control 0x0000
105#define ASIC3_SPI_TxData 0x0004
106#define ASIC3_SPI_RxData 0x0008
107#define ASIC3_SPI_Int 0x000c
108#define ASIC3_SPI_Status 0x0010
109
110#define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */
111
112#define ASIC3_PWM_0_Base 0x0500
113#define ASIC3_PWM_1_Base 0x0600
114#define ASIC3_PWM_TimeBase 0x0000
115#define ASIC3_PWM_PeriodTime 0x0004
116#define ASIC3_PWM_DutyTime 0x0008
117
118#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
119#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
120
121#define ASIC3_LED_0_Base 0x0700
122#define ASIC3_LED_1_Base 0x0800
123#define ASIC3_LED_2_Base 0x0900
124#define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */
125#define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */
126#define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */
127#define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */
128
129/* LED TimeBase bits - match ASIC2 */
130#define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */
131 /* Note: max = 5 on hx4700 */
132 /* 0: maximum time base */
133 /* 1: maximum time base / 2 */
134 /* n: maximum time base / 2^n */
135
136#define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */
137#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
138#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
139
140#define ASIC3_CLOCK_Base 0x0A00
141#define ASIC3_CLOCK_CDEX 0x00
142#define ASIC3_CLOCK_SEL 0x04
143
144#define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */
145#define CLOCK_CDEX_SOURCE0 (1 << 0)
146#define CLOCK_CDEX_SOURCE1 (1 << 1)
147#define CLOCK_CDEX_SPI (1 << 2)
148#define CLOCK_CDEX_OWM (1 << 3)
149#define CLOCK_CDEX_PWM0 (1 << 4)
150#define CLOCK_CDEX_PWM1 (1 << 5)
151#define CLOCK_CDEX_LED0 (1 << 6)
152#define CLOCK_CDEX_LED1 (1 << 7)
153#define CLOCK_CDEX_LED2 (1 << 8)
154
155/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
156#define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */
157#define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */
158#define CLOCK_CDEX_SMBUS (1 << 11)
159#define CLOCK_CDEX_CONTROL_CX (1 << 12)
160
161#define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */
162#define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */
163
164#define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */
165#define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */
166
167/* R/W: INT clock source control (32.768 kHz) */
168#define CLOCK_SEL_CX (1 << 2)
169
170
171#define ASIC3_INTR_Base 0x0B00
172
173#define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */
174#define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */
175#define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */
176#define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */
177
178#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
179#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
180#define ASIC3_INTMASK_MASK0 (1 << 2)
181#define ASIC3_INTMASK_MASK1 (1 << 3)
182#define ASIC3_INTMASK_MASK2 (1 << 4)
183#define ASIC3_INTMASK_MASK3 (1 << 5)
184#define ASIC3_INTMASK_MASK4 (1 << 6)
185#define ASIC3_INTMASK_MASK5 (1 << 7)
186
187#define ASIC3_INTR_PERIPHERAL_A (1 << 0)
188#define ASIC3_INTR_PERIPHERAL_B (1 << 1)
189#define ASIC3_INTR_PERIPHERAL_C (1 << 2)
190#define ASIC3_INTR_PERIPHERAL_D (1 << 3)
191#define ASIC3_INTR_LED0 (1 << 4)
192#define ASIC3_INTR_LED1 (1 << 5)
193#define ASIC3_INTR_LED2 (1 << 6)
194#define ASIC3_INTR_SPI (1 << 7)
195#define ASIC3_INTR_SMBUS (1 << 8)
196#define ASIC3_INTR_OWM (1 << 9)
197
198#define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
199#define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */
200
201
202/* Basic control of the SD ASIC */
203#define ASIC3_SDHWCTRL_Base 0x0E00
204#define ASIC3_SDHWCTRL_SDConf 0x00
205
206#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
207#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
208#define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */
209#define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */
210
211/* SD card write protection: 0=high */
212#define ASIC3_SDHWCTRL_LEVWP (1 << 4)
213#define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */
214
215/* SD card power supply ctrl 1=enable */
216#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
217
218#define ASIC3_EXTCF_Base 0x1100
219
220#define ASIC3_EXTCF_Select 0x00
221#define ASIC3_EXTCF_Reset 0x04
222
223#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
224#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
225#define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */
226#define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */
227#define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */
228#define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */
229#define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */
230#define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */
231#define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */
232#define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */
233#define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */
234#define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */
235#define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14)
236#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
237
238/*********************************************
239 * The Onewire interface registers
240 *
241 * OWM_CMD
242 * OWM_DAT
243 * OWM_INTR
244 * OWM_INTEN
245 * OWM_CLKDIV
246 *
247 *********************************************/
248
249#define ASIC3_OWM_Base 0xC00
250
251#define ASIC3_OWM_CMD 0x00
252#define ASIC3_OWM_DAT 0x04
253#define ASIC3_OWM_INTR 0x08
254#define ASIC3_OWM_INTEN 0x0C
255#define ASIC3_OWM_CLKDIV 0x10
256
257#define ASIC3_OWM_CMD_ONEWR (1 << 0)
258#define ASIC3_OWM_CMD_SRA (1 << 1)
259#define ASIC3_OWM_CMD_DQO (1 << 2)
260#define ASIC3_OWM_CMD_DQI (1 << 3)
261
262#define ASIC3_OWM_INTR_PD (1 << 0)
263#define ASIC3_OWM_INTR_PDR (1 << 1)
264#define ASIC3_OWM_INTR_TBE (1 << 2)
265#define ASIC3_OWM_INTR_TEMP (1 << 3)
266#define ASIC3_OWM_INTR_RBF (1 << 4)
267
268#define ASIC3_OWM_INTEN_EPD (1 << 0)
269#define ASIC3_OWM_INTEN_IAS (1 << 1)
270#define ASIC3_OWM_INTEN_ETBE (1 << 2)
271#define ASIC3_OWM_INTEN_ETMT (1 << 3)
272#define ASIC3_OWM_INTEN_ERBF (1 << 4)
273
274#define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */
275#define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */
276
277
278/*****************************************************************************
279 * The SD configuration registers are at a completely different location
280 * in memory. They are divided into three sets of registers:
281 *
282 * SD_CONFIG Core configuration register
283 * SD_CTRL Control registers for SD operations
284 * SDIO_CTRL Control registers for SDIO operations
285 *
286 *****************************************************************************/
287#define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */
288
289#define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */
290
291/* [0:8] SD Control Register Base Address */
292#define ASIC3_SD_CONFIG_Addr0 0x20
293
294/* [9:31] SD Control Register Base Address */
295#define ASIC3_SD_CONFIG_Addr1 0x24
296
297/* R/O: interrupt assigned to pin */
298#define ASIC3_SD_CONFIG_IntPin 0x78
299
300/*
301 * Set to 0x1f to clock SD controller, 0 otherwise.
302 * At 0x82 - Gated Clock Ctrl
303 */
304#define ASIC3_SD_CONFIG_ClkStop 0x80
305
306/* Control clock of SD controller */
307#define ASIC3_SD_CONFIG_ClockMode 0x84
308#define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */
309#define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */
310
311/* auto power up after card inserted */
312#define ASIC3_SD_CONFIG_SDHC_Power2 0x92
313
314/* auto power down when card removed */
315#define ASIC3_SD_CONFIG_SDHC_Power3 0x94
316#define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98
317#define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */
318#define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */
319#define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/
320
321/* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
322#define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8
323#define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */
324
325/* Bit 1: double buffer/single buffer */
326#define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0
327
328/* Memory access enable (set to 1 to access SD Controller) */
329#define SD_CONFIG_COMMAND_MAE (1<<1)
330
331#define SD_CONFIG_CLK_ENABLE_ALL 0x1f
332
333#define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */
334#define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */
335
336 /* two bits - number of cycles for card detection */
337#define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3)
338
339
340#define ASIC3_SD_CTRL_Base 0x1000
341
342#define ASIC3_SD_CTRL_Cmd 0x00
343#define ASIC3_SD_CTRL_Arg0 0x08
344#define ASIC3_SD_CTRL_Arg1 0x0C
345#define ASIC3_SD_CTRL_StopInternal 0x10
346#define ASIC3_SD_CTRL_TransferSectorCount 0x14
347#define ASIC3_SD_CTRL_Response0 0x18
348#define ASIC3_SD_CTRL_Response1 0x1C
349#define ASIC3_SD_CTRL_Response2 0x20
350#define ASIC3_SD_CTRL_Response3 0x24
351#define ASIC3_SD_CTRL_Response4 0x28
352#define ASIC3_SD_CTRL_Response5 0x2C
353#define ASIC3_SD_CTRL_Response6 0x30
354#define ASIC3_SD_CTRL_Response7 0x34
355#define ASIC3_SD_CTRL_CardStatus 0x38
356#define ASIC3_SD_CTRL_BufferCtrl 0x3C
357#define ASIC3_SD_CTRL_IntMaskCard 0x40
358#define ASIC3_SD_CTRL_IntMaskBuffer 0x44
359#define ASIC3_SD_CTRL_CardClockCtrl 0x48
360#define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C
361#define ASIC3_SD_CTRL_MemCardOptionSetup 0x50
362#define ASIC3_SD_CTRL_ErrorStatus0 0x58
363#define ASIC3_SD_CTRL_ErrorStatus1 0x5C
364#define ASIC3_SD_CTRL_DataPort 0x60
365#define ASIC3_SD_CTRL_TransactionCtrl 0x68
366#define ASIC3_SD_CTRL_SoftwareReset 0x1C0
367
368#define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0)
369
370#define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8)
371
372#define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15)
373#define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8)
374#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7)
375#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6)
376#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5)
377#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4)
378#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3)
379#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2)
380#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1)
381#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0)
382#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0)
383
384#define MEM_CARD_OPTION_REQUIRED 0x000e
385#define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4)
386#define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14)
387#define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15)
388#define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0
389
390#define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f)
391#define SD_CTRL_COMMAND_TYPE_CMD (0 << 6)
392#define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6)
393#define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6)
394#define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8)
395#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8)
396#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8)
397#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8)
398#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8)
399#define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11)
400#define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12)
401#define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12)
402#define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13)
403#define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14)
404
405#define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0)
406#define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8)
407
408#define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0)
409#define SD_CTRL_CARDSTATUS_RW_END (1 << 2)
410#define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3)
411#define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4)
412#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5)
413#define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7)
414#define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8)
415#define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9)
416#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10)
417
418#define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0)
419#define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1)
420#define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2)
421#define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3)
422#define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4)
423#define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5)
424#define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6)
425#define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7)
426#define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8)
427#define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9)
428#define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13)
429#define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14)
430#define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15)
431
432#define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0)
433#define SD_CTRL_INTMASKCARD_RW_END (1 << 2)
434#define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3)
435#define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4)
436#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
437#define SD_CTRL_INTMASKCARD_UNK6 (1 << 6)
438#define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7)
439#define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8)
440#define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9)
441#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
442
443#define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0)
444#define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1)
445#define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2)
446#define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3)
447#define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4)
448#define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5)
449#define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6)
450#define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7)
451#define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8)
452#define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9)
453#define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13)
454#define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14)
455#define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15)
456
457#define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0)
458#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
459#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3)
460#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4)
461#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5)
462#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8)
463#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9)
464#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10)
465#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11)
466
467#define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0)
468#define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4)
469#define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5)
470#define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6)
471
472#define ASIC3_SDIO_CTRL_Base 0x1200
473
474#define ASIC3_SDIO_CTRL_Cmd 0x00
475#define ASIC3_SDIO_CTRL_CardPortSel 0x04
476#define ASIC3_SDIO_CTRL_Arg0 0x08
477#define ASIC3_SDIO_CTRL_Arg1 0x0C
478#define ASIC3_SDIO_CTRL_TransferBlockCount 0x14
479#define ASIC3_SDIO_CTRL_Response0 0x18
480#define ASIC3_SDIO_CTRL_Response1 0x1C
481#define ASIC3_SDIO_CTRL_Response2 0x20
482#define ASIC3_SDIO_CTRL_Response3 0x24
483#define ASIC3_SDIO_CTRL_Response4 0x28
484#define ASIC3_SDIO_CTRL_Response5 0x2C
485#define ASIC3_SDIO_CTRL_Response6 0x30
486#define ASIC3_SDIO_CTRL_Response7 0x34
487#define ASIC3_SDIO_CTRL_CardStatus 0x38
488#define ASIC3_SDIO_CTRL_BufferCtrl 0x3C
489#define ASIC3_SDIO_CTRL_IntMaskCard 0x40
490#define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44
491#define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C
492#define ASIC3_SDIO_CTRL_CardOptionSetup 0x50
493#define ASIC3_SDIO_CTRL_ErrorStatus0 0x54
494#define ASIC3_SDIO_CTRL_ErrorStatus1 0x58
495#define ASIC3_SDIO_CTRL_DataPort 0x60
496#define ASIC3_SDIO_CTRL_TransactionCtrl 0x68
497#define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C
498#define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70
499#define ASIC3_SDIO_CTRL_HostInformation 0x74
500#define ASIC3_SDIO_CTRL_ErrorCtrl 0x78
501#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
502#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
503
504#define ASIC3_MAP_SIZE 0x2000
505
506#endif /* __ASIC3_H__ */