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David Brownellf492ec92009-05-14 13:01:59 -07001/*
2 * <mach/asp.h> - DaVinci Audio Serial Port support
3 */
4#ifndef __ASM_ARCH_DAVINCI_ASP_H
5#define __ASM_ARCH_DAVINCI_ASP_H
6
7#include <mach/irqs.h>
Chaithrika U S25acf552009-06-05 06:28:08 -04008#include <mach/edma.h>
David Brownellf492ec92009-05-14 13:01:59 -07009
Chaithrika U S25acf552009-06-05 06:28:08 -040010/* Bases of dm644x and dm355 register banks */
David Brownellf492ec92009-05-14 13:01:59 -070011#define DAVINCI_ASP0_BASE 0x01E02000
12#define DAVINCI_ASP1_BASE 0x01E04000
13
Chaithrika U S25acf552009-06-05 06:28:08 -040014/* Bases of dm646x register banks */
15#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
16#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
17
18/* EDMA channels of dm644x and dm355 */
David Brownellf492ec92009-05-14 13:01:59 -070019#define DAVINCI_DMA_ASP0_TX 2
20#define DAVINCI_DMA_ASP0_RX 3
21#define DAVINCI_DMA_ASP1_TX 8
22#define DAVINCI_DMA_ASP1_RX 9
23
Chaithrika U S25acf552009-06-05 06:28:08 -040024/* EDMA channels of dm646x */
25#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
26#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
27#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
28
David Brownellf492ec92009-05-14 13:01:59 -070029/* Interrupts */
30#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
31#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
32#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
33#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
34
Chaithrika U S25acf552009-06-05 06:28:08 -040035struct snd_platform_data {
36 char *clk_name;
37 u32 tx_dma_offset;
38 u32 rx_dma_offset;
39 enum dma_event_q eventq_no; /* event queue number */
40 unsigned int codec_fmt;
41
42 /* McASP specific fields */
43 int tdm_slots;
44 u8 op_mode;
45 u8 num_serializer;
46 u8 *serial_dir;
47};
48
49#define INACTIVE_MODE 0
50#define TX_MODE 1
51#define RX_MODE 2
52
53#define DAVINCI_MCASP_IIS_MODE 0
54#define DAVINCI_MCASP_DIT_MODE 1
55
David Brownellf492ec92009-05-14 13:01:59 -070056#endif /* __ASM_ARCH_DAVINCI_ASP_H */