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David Howells108b42b2006-03-31 16:00:29 +01001 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
4
5By: David Howells <dhowells@redhat.com>
6
7Contents:
8
9 (*) Abstract memory access model.
10
11 - Device operations.
12 - Guarantees.
13
14 (*) What are memory barriers?
15
16 - Varieties of memory barrier.
17 - What may not be assumed about memory barriers?
18 - Data dependency barriers.
19 - Control dependencies.
20 - SMP barrier pairing.
21 - Examples of memory barrier sequences.
David Howells670bd952006-06-10 09:54:12 -070022 - Read memory barriers vs load speculation.
David Howells108b42b2006-03-31 16:00:29 +010023
24 (*) Explicit kernel barriers.
25
26 - Compiler barrier.
27 - The CPU memory barriers.
28 - MMIO write barrier.
29
30 (*) Implicit kernel memory barriers.
31
32 - Locking functions.
33 - Interrupt disabling functions.
34 - Miscellaneous functions.
35
36 (*) Inter-CPU locking barrier effects.
37
38 - Locks vs memory accesses.
39 - Locks vs I/O accesses.
40
41 (*) Where are memory barriers needed?
42
43 - Interprocessor interaction.
44 - Atomic operations.
45 - Accessing devices.
46 - Interrupts.
47
48 (*) Kernel I/O barrier effects.
49
50 (*) Assumed minimum execution ordering model.
51
52 (*) The effects of the cpu cache.
53
54 - Cache coherency.
55 - Cache coherency vs DMA.
56 - Cache coherency vs MMIO.
57
58 (*) The things CPUs get up to.
59
60 - And then there's the Alpha.
61
62 (*) References.
63
64
65============================
66ABSTRACT MEMORY ACCESS MODEL
67============================
68
69Consider the following abstract model of the system:
70
71 : :
72 : :
73 : :
74 +-------+ : +--------+ : +-------+
75 | | : | | : | |
76 | | : | | : | |
77 | CPU 1 |<----->| Memory |<----->| CPU 2 |
78 | | : | | : | |
79 | | : | | : | |
80 +-------+ : +--------+ : +-------+
81 ^ : ^ : ^
82 | : | : |
83 | : | : |
84 | : v : |
85 | : +--------+ : |
86 | : | | : |
87 | : | | : |
88 +---------->| Device |<----------+
89 : | | :
90 : | | :
91 : +--------+ :
92 : :
93
94Each CPU executes a program that generates memory access operations. In the
95abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
96perform the memory operations in any order it likes, provided program causality
97appears to be maintained. Similarly, the compiler may also arrange the
98instructions it emits in any order it likes, provided it doesn't affect the
99apparent operation of the program.
100
101So in the above diagram, the effects of the memory operations performed by a
102CPU are perceived by the rest of the system as the operations cross the
103interface between the CPU and rest of the system (the dotted lines).
104
105
106For example, consider the following sequence of events:
107
108 CPU 1 CPU 2
109 =============== ===============
110 { A == 1; B == 2 }
111 A = 3; x = A;
112 B = 4; y = B;
113
114The set of accesses as seen by the memory system in the middle can be arranged
115in 24 different combinations:
116
117 STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
118 STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
119 STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
120 STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
121 STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
122 STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
123 STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
124 STORE B=4, ...
125 ...
126
127and can thus result in four different combinations of values:
128
129 x == 1, y == 2
130 x == 1, y == 4
131 x == 3, y == 2
132 x == 3, y == 4
133
134
135Furthermore, the stores committed by a CPU to the memory system may not be
136perceived by the loads made by another CPU in the same order as the stores were
137committed.
138
139
140As a further example, consider this sequence of events:
141
142 CPU 1 CPU 2
143 =============== ===============
144 { A == 1, B == 2, C = 3, P == &A, Q == &C }
145 B = 4; Q = P;
146 P = &B D = *Q;
147
148There is an obvious data dependency here, as the value loaded into D depends on
149the address retrieved from P by CPU 2. At the end of the sequence, any of the
150following results are possible:
151
152 (Q == &A) and (D == 1)
153 (Q == &B) and (D == 2)
154 (Q == &B) and (D == 4)
155
156Note that CPU 2 will never try and load C into D because the CPU will load P
157into Q before issuing the load of *Q.
158
159
160DEVICE OPERATIONS
161-----------------
162
163Some devices present their control interfaces as collections of memory
164locations, but the order in which the control registers are accessed is very
165important. For instance, imagine an ethernet card with a set of internal
166registers that are accessed through an address port register (A) and a data
167port register (D). To read internal register 5, the following code might then
168be used:
169
170 *A = 5;
171 x = *D;
172
173but this might show up as either of the following two sequences:
174
175 STORE *A = 5, x = LOAD *D
176 x = LOAD *D, STORE *A = 5
177
178the second of which will almost certainly result in a malfunction, since it set
179the address _after_ attempting to read the register.
180
181
182GUARANTEES
183----------
184
185There are some minimal guarantees that may be expected of a CPU:
186
187 (*) On any given CPU, dependent memory accesses will be issued in order, with
188 respect to itself. This means that for:
189
190 Q = P; D = *Q;
191
192 the CPU will issue the following memory operations:
193
194 Q = LOAD P, D = LOAD *Q
195
196 and always in that order.
197
198 (*) Overlapping loads and stores within a particular CPU will appear to be
199 ordered within that CPU. This means that for:
200
201 a = *X; *X = b;
202
203 the CPU will only issue the following sequence of memory operations:
204
205 a = LOAD *X, STORE *X = b
206
207 And for:
208
209 *X = c; d = *X;
210
211 the CPU will only issue:
212
213 STORE *X = c, d = LOAD *X
214
215 (Loads and stores overlap if they are targetted at overlapping pieces of
216 memory).
217
218And there are a number of things that _must_ or _must_not_ be assumed:
219
220 (*) It _must_not_ be assumed that independent loads and stores will be issued
221 in the order given. This means that for:
222
223 X = *A; Y = *B; *D = Z;
224
225 we may get any of the following sequences:
226
227 X = LOAD *A, Y = LOAD *B, STORE *D = Z
228 X = LOAD *A, STORE *D = Z, Y = LOAD *B
229 Y = LOAD *B, X = LOAD *A, STORE *D = Z
230 Y = LOAD *B, STORE *D = Z, X = LOAD *A
231 STORE *D = Z, X = LOAD *A, Y = LOAD *B
232 STORE *D = Z, Y = LOAD *B, X = LOAD *A
233
234 (*) It _must_ be assumed that overlapping memory accesses may be merged or
235 discarded. This means that for:
236
237 X = *A; Y = *(A + 4);
238
239 we may get any one of the following sequences:
240
241 X = LOAD *A; Y = LOAD *(A + 4);
242 Y = LOAD *(A + 4); X = LOAD *A;
243 {X, Y} = LOAD {*A, *(A + 4) };
244
245 And for:
246
247 *A = X; Y = *A;
248
249 we may get either of:
250
251 STORE *A = X; Y = LOAD *A;
David Howells670bd952006-06-10 09:54:12 -0700252 STORE *A = Y = X;
David Howells108b42b2006-03-31 16:00:29 +0100253
254
255=========================
256WHAT ARE MEMORY BARRIERS?
257=========================
258
259As can be seen above, independent memory operations are effectively performed
260in random order, but this can be a problem for CPU-CPU interaction and for I/O.
261What is required is some way of intervening to instruct the compiler and the
262CPU to restrict the order.
263
264Memory barriers are such interventions. They impose a perceived partial
David Howells2b948952006-06-25 05:48:49 -0700265ordering over the memory operations on either side of the barrier.
266
267Such enforcement is important because the CPUs and other devices in a system
268can use a variety of tricks to improve performance - including reordering,
269deferral and combination of memory operations; speculative loads; speculative
270branch prediction and various types of caching. Memory barriers are used to
271override or suppress these tricks, allowing the code to sanely control the
272interaction of multiple CPUs and/or devices.
David Howells108b42b2006-03-31 16:00:29 +0100273
274
275VARIETIES OF MEMORY BARRIER
276---------------------------
277
278Memory barriers come in four basic varieties:
279
280 (1) Write (or store) memory barriers.
281
282 A write memory barrier gives a guarantee that all the STORE operations
283 specified before the barrier will appear to happen before all the STORE
284 operations specified after the barrier with respect to the other
285 components of the system.
286
287 A write barrier is a partial ordering on stores only; it is not required
288 to have any effect on loads.
289
290 A CPU can be viewed as as commiting a sequence of store operations to the
291 memory system as time progresses. All stores before a write barrier will
292 occur in the sequence _before_ all the stores after the write barrier.
293
294 [!] Note that write barriers should normally be paired with read or data
295 dependency barriers; see the "SMP barrier pairing" subsection.
296
297
298 (2) Data dependency barriers.
299
300 A data dependency barrier is a weaker form of read barrier. In the case
301 where two loads are performed such that the second depends on the result
302 of the first (eg: the first load retrieves the address to which the second
303 load will be directed), a data dependency barrier would be required to
304 make sure that the target of the second load is updated before the address
305 obtained by the first load is accessed.
306
307 A data dependency barrier is a partial ordering on interdependent loads
308 only; it is not required to have any effect on stores, independent loads
309 or overlapping loads.
310
311 As mentioned in (1), the other CPUs in the system can be viewed as
312 committing sequences of stores to the memory system that the CPU being
313 considered can then perceive. A data dependency barrier issued by the CPU
314 under consideration guarantees that for any load preceding it, if that
315 load touches one of a sequence of stores from another CPU, then by the
316 time the barrier completes, the effects of all the stores prior to that
317 touched by the load will be perceptible to any loads issued after the data
318 dependency barrier.
319
320 See the "Examples of memory barrier sequences" subsection for diagrams
321 showing the ordering constraints.
322
323 [!] Note that the first load really has to have a _data_ dependency and
324 not a control dependency. If the address for the second load is dependent
325 on the first load, but the dependency is through a conditional rather than
326 actually loading the address itself, then it's a _control_ dependency and
327 a full read barrier or better is required. See the "Control dependencies"
328 subsection for more information.
329
330 [!] Note that data dependency barriers should normally be paired with
331 write barriers; see the "SMP barrier pairing" subsection.
332
333
334 (3) Read (or load) memory barriers.
335
336 A read barrier is a data dependency barrier plus a guarantee that all the
337 LOAD operations specified before the barrier will appear to happen before
338 all the LOAD operations specified after the barrier with respect to the
339 other components of the system.
340
341 A read barrier is a partial ordering on loads only; it is not required to
342 have any effect on stores.
343
344 Read memory barriers imply data dependency barriers, and so can substitute
345 for them.
346
347 [!] Note that read barriers should normally be paired with write barriers;
348 see the "SMP barrier pairing" subsection.
349
350
351 (4) General memory barriers.
352
David Howells670bd952006-06-10 09:54:12 -0700353 A general memory barrier gives a guarantee that all the LOAD and STORE
354 operations specified before the barrier will appear to happen before all
355 the LOAD and STORE operations specified after the barrier with respect to
356 the other components of the system.
357
358 A general memory barrier is a partial ordering over both loads and stores.
David Howells108b42b2006-03-31 16:00:29 +0100359
360 General memory barriers imply both read and write memory barriers, and so
361 can substitute for either.
362
363
364And a couple of implicit varieties:
365
366 (5) LOCK operations.
367
368 This acts as a one-way permeable barrier. It guarantees that all memory
369 operations after the LOCK operation will appear to happen after the LOCK
370 operation with respect to the other components of the system.
371
372 Memory operations that occur before a LOCK operation may appear to happen
373 after it completes.
374
375 A LOCK operation should almost always be paired with an UNLOCK operation.
376
377
378 (6) UNLOCK operations.
379
380 This also acts as a one-way permeable barrier. It guarantees that all
381 memory operations before the UNLOCK operation will appear to happen before
382 the UNLOCK operation with respect to the other components of the system.
383
384 Memory operations that occur after an UNLOCK operation may appear to
385 happen before it completes.
386
387 LOCK and UNLOCK operations are guaranteed to appear with respect to each
388 other strictly in the order specified.
389
390 The use of LOCK and UNLOCK operations generally precludes the need for
391 other sorts of memory barrier (but note the exceptions mentioned in the
392 subsection "MMIO write barrier").
393
394
395Memory barriers are only required where there's a possibility of interaction
396between two CPUs or between a CPU and a device. If it can be guaranteed that
397there won't be any such interaction in any particular piece of code, then
398memory barriers are unnecessary in that piece of code.
399
400
401Note that these are the _minimum_ guarantees. Different architectures may give
402more substantial guarantees, but they may _not_ be relied upon outside of arch
403specific code.
404
405
406WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
407----------------------------------------------
408
409There are certain things that the Linux kernel memory barriers do not guarantee:
410
411 (*) There is no guarantee that any of the memory accesses specified before a
412 memory barrier will be _complete_ by the completion of a memory barrier
413 instruction; the barrier can be considered to draw a line in that CPU's
414 access queue that accesses of the appropriate type may not cross.
415
416 (*) There is no guarantee that issuing a memory barrier on one CPU will have
417 any direct effect on another CPU or any other hardware in the system. The
418 indirect effect will be the order in which the second CPU sees the effects
419 of the first CPU's accesses occur, but see the next point:
420
421 (*) There is no guarantee that the a CPU will see the correct order of effects
422 from a second CPU's accesses, even _if_ the second CPU uses a memory
423 barrier, unless the first CPU _also_ uses a matching memory barrier (see
424 the subsection on "SMP Barrier Pairing").
425
426 (*) There is no guarantee that some intervening piece of off-the-CPU
427 hardware[*] will not reorder the memory accesses. CPU cache coherency
428 mechanisms should propagate the indirect effects of a memory barrier
429 between CPUs, but might not do so in order.
430
431 [*] For information on bus mastering DMA and coherency please read:
432
433 Documentation/pci.txt
434 Documentation/DMA-mapping.txt
435 Documentation/DMA-API.txt
436
437
438DATA DEPENDENCY BARRIERS
439------------------------
440
441The usage requirements of data dependency barriers are a little subtle, and
442it's not always obvious that they're needed. To illustrate, consider the
443following sequence of events:
444
445 CPU 1 CPU 2
446 =============== ===============
447 { A == 1, B == 2, C = 3, P == &A, Q == &C }
448 B = 4;
449 <write barrier>
450 P = &B
451 Q = P;
452 D = *Q;
453
454There's a clear data dependency here, and it would seem that by the end of the
455sequence, Q must be either &A or &B, and that:
456
457 (Q == &A) implies (D == 1)
458 (Q == &B) implies (D == 4)
459
460But! CPU 2's perception of P may be updated _before_ its perception of B, thus
461leading to the following situation:
462
463 (Q == &B) and (D == 2) ????
464
465Whilst this may seem like a failure of coherency or causality maintenance, it
466isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
467Alpha).
468
David Howells2b948952006-06-25 05:48:49 -0700469To deal with this, a data dependency barrier or better must be inserted
470between the address load and the data load:
David Howells108b42b2006-03-31 16:00:29 +0100471
472 CPU 1 CPU 2
473 =============== ===============
474 { A == 1, B == 2, C = 3, P == &A, Q == &C }
475 B = 4;
476 <write barrier>
477 P = &B
478 Q = P;
479 <data dependency barrier>
480 D = *Q;
481
482This enforces the occurrence of one of the two implications, and prevents the
483third possibility from arising.
484
485[!] Note that this extremely counterintuitive situation arises most easily on
486machines with split caches, so that, for example, one cache bank processes
487even-numbered cache lines and the other bank processes odd-numbered cache
488lines. The pointer P might be stored in an odd-numbered cache line, and the
489variable B might be stored in an even-numbered cache line. Then, if the
490even-numbered bank of the reading CPU's cache is extremely busy while the
491odd-numbered bank is idle, one can see the new value of the pointer P (&B),
492but the old value of the variable B (1).
493
494
495Another example of where data dependency barriers might by required is where a
496number is read from memory and then used to calculate the index for an array
497access:
498
499 CPU 1 CPU 2
500 =============== ===============
501 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
502 M[1] = 4;
503 <write barrier>
504 P = 1
505 Q = P;
506 <data dependency barrier>
507 D = M[Q];
508
509
510The data dependency barrier is very important to the RCU system, for example.
511See rcu_dereference() in include/linux/rcupdate.h. This permits the current
512target of an RCU'd pointer to be replaced with a new modified target, without
513the replacement target appearing to be incompletely initialised.
514
515See also the subsection on "Cache Coherency" for a more thorough example.
516
517
518CONTROL DEPENDENCIES
519--------------------
520
521A control dependency requires a full read memory barrier, not simply a data
522dependency barrier to make it work correctly. Consider the following bit of
523code:
524
525 q = &a;
526 if (p)
527 q = &b;
528 <data dependency barrier>
529 x = *q;
530
531This will not have the desired effect because there is no actual data
532dependency, but rather a control dependency that the CPU may short-circuit by
533attempting to predict the outcome in advance. In such a case what's actually
534required is:
535
536 q = &a;
537 if (p)
538 q = &b;
539 <read barrier>
540 x = *q;
541
542
543SMP BARRIER PAIRING
544-------------------
545
546When dealing with CPU-CPU interactions, certain types of memory barrier should
547always be paired. A lack of appropriate pairing is almost certainly an error.
548
549A write barrier should always be paired with a data dependency barrier or read
550barrier, though a general barrier would also be viable. Similarly a read
551barrier or a data dependency barrier should always be paired with at least an
552write barrier, though, again, a general barrier is viable:
553
554 CPU 1 CPU 2
555 =============== ===============
556 a = 1;
557 <write barrier>
David Howells670bd952006-06-10 09:54:12 -0700558 b = 2; x = b;
David Howells108b42b2006-03-31 16:00:29 +0100559 <read barrier>
David Howells670bd952006-06-10 09:54:12 -0700560 y = a;
David Howells108b42b2006-03-31 16:00:29 +0100561
562Or:
563
564 CPU 1 CPU 2
565 =============== ===============================
566 a = 1;
567 <write barrier>
568 b = &a; x = b;
569 <data dependency barrier>
570 y = *x;
571
572Basically, the read barrier always has to be there, even though it can be of
573the "weaker" type.
574
David Howells670bd952006-06-10 09:54:12 -0700575[!] Note that the stores before the write barrier would normally be expected to
576match the loads after the read barrier or data dependency barrier, and vice
577versa:
578
579 CPU 1 CPU 2
580 =============== ===============
581 a = 1; }---- --->{ v = c
582 b = 2; } \ / { w = d
583 <write barrier> \ <read barrier>
584 c = 3; } / \ { x = a;
585 d = 4; }---- --->{ y = b;
586
David Howells108b42b2006-03-31 16:00:29 +0100587
588EXAMPLES OF MEMORY BARRIER SEQUENCES
589------------------------------------
590
591Firstly, write barriers act as a partial orderings on store operations.
592Consider the following sequence of events:
593
594 CPU 1
595 =======================
596 STORE A = 1
597 STORE B = 2
598 STORE C = 3
599 <write barrier>
600 STORE D = 4
601 STORE E = 5
602
603This sequence of events is committed to the memory coherence system in an order
604that the rest of the system might perceive as the unordered set of { STORE A,
605STORE B, STORE C } all occuring before the unordered set of { STORE D, STORE E
606}:
607
608 +-------+ : :
609 | | +------+
610 | |------>| C=3 | } /\
611 | | : +------+ }----- \ -----> Events perceptible
612 | | : | A=1 | } \/ to rest of system
613 | | : +------+ }
614 | CPU 1 | : | B=2 | }
615 | | +------+ }
616 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
617 | | +------+ } requires all stores prior to the
618 | | : | E=5 | } barrier to be committed before
619 | | : +------+ } further stores may be take place.
620 | |------>| D=4 | }
621 | | +------+
622 +-------+ : :
623 |
David Howells670bd952006-06-10 09:54:12 -0700624 | Sequence in which stores are committed to the
625 | memory system by CPU 1
David Howells108b42b2006-03-31 16:00:29 +0100626 V
627
628
629Secondly, data dependency barriers act as a partial orderings on data-dependent
630loads. Consider the following sequence of events:
631
632 CPU 1 CPU 2
633 ======================= =======================
David Howellsc14038c2006-04-10 22:54:24 -0700634 { B = 7; X = 9; Y = 8; C = &Y }
David Howells108b42b2006-03-31 16:00:29 +0100635 STORE A = 1
636 STORE B = 2
637 <write barrier>
638 STORE C = &B LOAD X
639 STORE D = 4 LOAD C (gets &B)
640 LOAD *C (reads B)
641
642Without intervention, CPU 2 may perceive the events on CPU 1 in some
643effectively random order, despite the write barrier issued by CPU 1:
644
645 +-------+ : : : :
646 | | +------+ +-------+ | Sequence of update
647 | |------>| B=2 |----- --->| Y->8 | | of perception on
648 | | : +------+ \ +-------+ | CPU 2
649 | CPU 1 | : | A=1 | \ --->| C->&Y | V
650 | | +------+ | +-------+
651 | | wwwwwwwwwwwwwwww | : :
652 | | +------+ | : :
653 | | : | C=&B |--- | : : +-------+
654 | | : +------+ \ | +-------+ | |
655 | |------>| D=4 | ----------->| C->&B |------>| |
656 | | +------+ | +-------+ | |
657 +-------+ : : | : : | |
658 | : : | |
659 | : : | CPU 2 |
660 | +-------+ | |
661 Apparently incorrect ---> | | B->7 |------>| |
662 perception of B (!) | +-------+ | |
663 | : : | |
664 | +-------+ | |
665 The load of X holds ---> \ | X->9 |------>| |
666 up the maintenance \ +-------+ | |
667 of coherence of B ----->| B->2 | +-------+
668 +-------+
669 : :
670
671
672In the above example, CPU 2 perceives that B is 7, despite the load of *C
673(which would be B) coming after the the LOAD of C.
674
675If, however, a data dependency barrier were to be placed between the load of C
David Howellsc14038c2006-04-10 22:54:24 -0700676and the load of *C (ie: B) on CPU 2:
677
678 CPU 1 CPU 2
679 ======================= =======================
680 { B = 7; X = 9; Y = 8; C = &Y }
681 STORE A = 1
682 STORE B = 2
683 <write barrier>
684 STORE C = &B LOAD X
685 STORE D = 4 LOAD C (gets &B)
686 <data dependency barrier>
687 LOAD *C (reads B)
688
689then the following will occur:
David Howells108b42b2006-03-31 16:00:29 +0100690
691 +-------+ : : : :
692 | | +------+ +-------+
693 | |------>| B=2 |----- --->| Y->8 |
694 | | : +------+ \ +-------+
695 | CPU 1 | : | A=1 | \ --->| C->&Y |
696 | | +------+ | +-------+
697 | | wwwwwwwwwwwwwwww | : :
698 | | +------+ | : :
699 | | : | C=&B |--- | : : +-------+
700 | | : +------+ \ | +-------+ | |
701 | |------>| D=4 | ----------->| C->&B |------>| |
702 | | +------+ | +-------+ | |
703 +-------+ : : | : : | |
704 | : : | |
705 | : : | CPU 2 |
706 | +-------+ | |
David Howells670bd952006-06-10 09:54:12 -0700707 | | X->9 |------>| |
708 | +-------+ | |
709 Makes sure all effects ---> \ ddddddddddddddddd | |
710 prior to the store of C \ +-------+ | |
711 are perceptible to ----->| B->2 |------>| |
712 subsequent loads +-------+ | |
David Howells108b42b2006-03-31 16:00:29 +0100713 : : +-------+
714
715
716And thirdly, a read barrier acts as a partial order on loads. Consider the
717following sequence of events:
718
719 CPU 1 CPU 2
720 ======================= =======================
David Howells670bd952006-06-10 09:54:12 -0700721 { A = 0, B = 9 }
David Howells108b42b2006-03-31 16:00:29 +0100722 STORE A=1
David Howells108b42b2006-03-31 16:00:29 +0100723 <write barrier>
David Howells670bd952006-06-10 09:54:12 -0700724 STORE B=2
David Howells108b42b2006-03-31 16:00:29 +0100725 LOAD B
David Howells670bd952006-06-10 09:54:12 -0700726 LOAD A
David Howells108b42b2006-03-31 16:00:29 +0100727
728Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
729some effectively random order, despite the write barrier issued by CPU 1:
730
David Howells670bd952006-06-10 09:54:12 -0700731 +-------+ : : : :
732 | | +------+ +-------+
733 | |------>| A=1 |------ --->| A->0 |
734 | | +------+ \ +-------+
735 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
736 | | +------+ | +-------+
737 | |------>| B=2 |--- | : :
738 | | +------+ \ | : : +-------+
739 +-------+ : : \ | +-------+ | |
740 ---------->| B->2 |------>| |
741 | +-------+ | CPU 2 |
742 | | A->0 |------>| |
743 | +-------+ | |
744 | : : +-------+
745 \ : :
746 \ +-------+
747 ---->| A->1 |
748 +-------+
749 : :
David Howells108b42b2006-03-31 16:00:29 +0100750
751
David Howells670bd952006-06-10 09:54:12 -0700752If, however, a read barrier were to be placed between the load of E and the
753load of A on CPU 2:
David Howells108b42b2006-03-31 16:00:29 +0100754
David Howells670bd952006-06-10 09:54:12 -0700755 CPU 1 CPU 2
756 ======================= =======================
757 { A = 0, B = 9 }
758 STORE A=1
759 <write barrier>
760 STORE B=2
761 LOAD B
762 <read barrier>
763 LOAD A
764
765then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
7662:
767
768 +-------+ : : : :
769 | | +------+ +-------+
770 | |------>| A=1 |------ --->| A->0 |
771 | | +------+ \ +-------+
772 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
773 | | +------+ | +-------+
774 | |------>| B=2 |--- | : :
775 | | +------+ \ | : : +-------+
776 +-------+ : : \ | +-------+ | |
777 ---------->| B->2 |------>| |
778 | +-------+ | CPU 2 |
779 | : : | |
780 | : : | |
781 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
782 barrier causes all effects \ +-------+ | |
783 prior to the storage of B ---->| A->1 |------>| |
784 to be perceptible to CPU 2 +-------+ | |
785 : : +-------+
786
787
788To illustrate this more completely, consider what could happen if the code
789contained a load of A either side of the read barrier:
790
791 CPU 1 CPU 2
792 ======================= =======================
793 { A = 0, B = 9 }
794 STORE A=1
795 <write barrier>
796 STORE B=2
797 LOAD B
798 LOAD A [first load of A]
799 <read barrier>
800 LOAD A [second load of A]
801
802Even though the two loads of A both occur after the load of B, they may both
803come up with different values:
804
805 +-------+ : : : :
806 | | +------+ +-------+
807 | |------>| A=1 |------ --->| A->0 |
808 | | +------+ \ +-------+
809 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
810 | | +------+ | +-------+
811 | |------>| B=2 |--- | : :
812 | | +------+ \ | : : +-------+
813 +-------+ : : \ | +-------+ | |
814 ---------->| B->2 |------>| |
815 | +-------+ | CPU 2 |
816 | : : | |
817 | : : | |
818 | +-------+ | |
819 | | A->0 |------>| 1st |
820 | +-------+ | |
821 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
822 barrier causes all effects \ +-------+ | |
823 prior to the storage of B ---->| A->1 |------>| 2nd |
824 to be perceptible to CPU 2 +-------+ | |
825 : : +-------+
826
827
828But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
829before the read barrier completes anyway:
830
831 +-------+ : : : :
832 | | +------+ +-------+
833 | |------>| A=1 |------ --->| A->0 |
834 | | +------+ \ +-------+
835 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
836 | | +------+ | +-------+
837 | |------>| B=2 |--- | : :
838 | | +------+ \ | : : +-------+
839 +-------+ : : \ | +-------+ | |
840 ---------->| B->2 |------>| |
841 | +-------+ | CPU 2 |
842 | : : | |
843 \ : : | |
844 \ +-------+ | |
845 ---->| A->1 |------>| 1st |
846 +-------+ | |
847 rrrrrrrrrrrrrrrrr | |
848 +-------+ | |
849 | A->1 |------>| 2nd |
850 +-------+ | |
851 : : +-------+
852
853
854The guarantee is that the second load will always come up with A == 1 if the
855load of B came up with B == 2. No such guarantee exists for the first load of
856A; that may come up with either A == 0 or A == 1.
857
858
859READ MEMORY BARRIERS VS LOAD SPECULATION
860----------------------------------------
861
862Many CPUs speculate with loads: that is they see that they will need to load an
863item from memory, and they find a time where they're not using the bus for any
864other loads, and so do the load in advance - even though they haven't actually
865got to that point in the instruction execution flow yet. This permits the
866actual load instruction to potentially complete immediately because the CPU
867already has the value to hand.
868
869It may turn out that the CPU didn't actually need the value - perhaps because a
870branch circumvented the load - in which case it can discard the value or just
871cache it for later use.
872
873Consider:
874
875 CPU 1 CPU 2
876 ======================= =======================
877 LOAD B
878 DIVIDE } Divide instructions generally
879 DIVIDE } take a long time to perform
880 LOAD A
881
882Which might appear as this:
883
884 : : +-------+
885 +-------+ | |
886 --->| B->2 |------>| |
887 +-------+ | CPU 2 |
888 : :DIVIDE | |
889 +-------+ | |
890 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
891 division speculates on the +-------+ ~ | |
892 LOAD of A : : ~ | |
893 : :DIVIDE | |
894 : : ~ | |
895 Once the divisions are complete --> : : ~-->| |
896 the CPU can then perform the : : | |
897 LOAD with immediate effect : : +-------+
898
899
900Placing a read barrier or a data dependency barrier just before the second
901load:
902
903 CPU 1 CPU 2
904 ======================= =======================
905 LOAD B
906 DIVIDE
907 DIVIDE
908 <read barrier>
909 LOAD A
910
911will force any value speculatively obtained to be reconsidered to an extent
912dependent on the type of barrier used. If there was no change made to the
913speculated memory location, then the speculated value will just be used:
914
915 : : +-------+
916 +-------+ | |
917 --->| B->2 |------>| |
918 +-------+ | CPU 2 |
919 : :DIVIDE | |
920 +-------+ | |
921 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
922 division speculates on the +-------+ ~ | |
923 LOAD of A : : ~ | |
924 : :DIVIDE | |
925 : : ~ | |
926 : : ~ | |
927 rrrrrrrrrrrrrrrr~ | |
928 : : ~ | |
929 : : ~-->| |
930 : : | |
931 : : +-------+
932
933
934but if there was an update or an invalidation from another CPU pending, then
935the speculation will be cancelled and the value reloaded:
936
937 : : +-------+
938 +-------+ | |
939 --->| B->2 |------>| |
940 +-------+ | CPU 2 |
941 : :DIVIDE | |
942 +-------+ | |
943 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
944 division speculates on the +-------+ ~ | |
945 LOAD of A : : ~ | |
946 : :DIVIDE | |
947 : : ~ | |
948 : : ~ | |
949 rrrrrrrrrrrrrrrrr | |
950 +-------+ | |
951 The speculation is discarded ---> --->| A->1 |------>| |
952 and an updated value is +-------+ | |
953 retrieved : : +-------+
David Howells108b42b2006-03-31 16:00:29 +0100954
955
956========================
957EXPLICIT KERNEL BARRIERS
958========================
959
960The Linux kernel has a variety of different barriers that act at different
961levels:
962
963 (*) Compiler barrier.
964
965 (*) CPU memory barriers.
966
967 (*) MMIO write barrier.
968
969
970COMPILER BARRIER
971----------------
972
973The Linux kernel has an explicit compiler barrier function that prevents the
974compiler from moving the memory accesses either side of it to the other side:
975
976 barrier();
977
978This a general barrier - lesser varieties of compiler barrier do not exist.
979
980The compiler barrier has no direct effect on the CPU, which may then reorder
981things however it wishes.
982
983
984CPU MEMORY BARRIERS
985-------------------
986
987The Linux kernel has eight basic CPU memory barriers:
988
989 TYPE MANDATORY SMP CONDITIONAL
990 =============== ======================= ===========================
991 GENERAL mb() smp_mb()
992 WRITE wmb() smp_wmb()
993 READ rmb() smp_rmb()
994 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
995
996
997All CPU memory barriers unconditionally imply compiler barriers.
998
999SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1000systems because it is assumed that a CPU will be appear to be self-consistent,
1001and will order overlapping accesses correctly with respect to itself.
1002
1003[!] Note that SMP memory barriers _must_ be used to control the ordering of
1004references to shared memory on SMP systems, though the use of locking instead
1005is sufficient.
1006
1007Mandatory barriers should not be used to control SMP effects, since mandatory
1008barriers unnecessarily impose overhead on UP systems. They may, however, be
1009used to control MMIO effects on accesses through relaxed memory I/O windows.
1010These are required even on non-SMP systems as they affect the order in which
1011memory operations appear to a device by prohibiting both the compiler and the
1012CPU from reordering them.
1013
1014
1015There are some more advanced barrier functions:
1016
1017 (*) set_mb(var, value)
1018 (*) set_wmb(var, value)
1019
1020 These assign the value to the variable and then insert at least a write
1021 barrier after it, depending on the function. They aren't guaranteed to
1022 insert anything more than a compiler barrier in a UP compilation.
1023
1024
1025 (*) smp_mb__before_atomic_dec();
1026 (*) smp_mb__after_atomic_dec();
1027 (*) smp_mb__before_atomic_inc();
1028 (*) smp_mb__after_atomic_inc();
1029
1030 These are for use with atomic add, subtract, increment and decrement
David Howellsdbc87002006-04-10 22:54:23 -07001031 functions that don't return a value, especially when used for reference
1032 counting. These functions do not imply memory barriers.
David Howells108b42b2006-03-31 16:00:29 +01001033
1034 As an example, consider a piece of code that marks an object as being dead
1035 and then decrements the object's reference count:
1036
1037 obj->dead = 1;
1038 smp_mb__before_atomic_dec();
1039 atomic_dec(&obj->ref_count);
1040
1041 This makes sure that the death mark on the object is perceived to be set
1042 *before* the reference counter is decremented.
1043
1044 See Documentation/atomic_ops.txt for more information. See the "Atomic
1045 operations" subsection for information on where to use these.
1046
1047
1048 (*) smp_mb__before_clear_bit(void);
1049 (*) smp_mb__after_clear_bit(void);
1050
1051 These are for use similar to the atomic inc/dec barriers. These are
1052 typically used for bitwise unlocking operations, so care must be taken as
1053 there are no implicit memory barriers here either.
1054
1055 Consider implementing an unlock operation of some nature by clearing a
1056 locking bit. The clear_bit() would then need to be barriered like this:
1057
1058 smp_mb__before_clear_bit();
1059 clear_bit( ... );
1060
1061 This prevents memory operations before the clear leaking to after it. See
1062 the subsection on "Locking Functions" with reference to UNLOCK operation
1063 implications.
1064
1065 See Documentation/atomic_ops.txt for more information. See the "Atomic
1066 operations" subsection for information on where to use these.
1067
1068
1069MMIO WRITE BARRIER
1070------------------
1071
1072The Linux kernel also has a special barrier for use with memory-mapped I/O
1073writes:
1074
1075 mmiowb();
1076
1077This is a variation on the mandatory write barrier that causes writes to weakly
1078ordered I/O regions to be partially ordered. Its effects may go beyond the
1079CPU->Hardware interface and actually affect the hardware at some level.
1080
1081See the subsection "Locks vs I/O accesses" for more information.
1082
1083
1084===============================
1085IMPLICIT KERNEL MEMORY BARRIERS
1086===============================
1087
1088Some of the other functions in the linux kernel imply memory barriers, amongst
David Howells670bd952006-06-10 09:54:12 -07001089which are locking and scheduling functions.
David Howells108b42b2006-03-31 16:00:29 +01001090
1091This specification is a _minimum_ guarantee; any particular architecture may
1092provide more substantial guarantees, but these may not be relied upon outside
1093of arch specific code.
1094
1095
1096LOCKING FUNCTIONS
1097-----------------
1098
1099The Linux kernel has a number of locking constructs:
1100
1101 (*) spin locks
1102 (*) R/W spin locks
1103 (*) mutexes
1104 (*) semaphores
1105 (*) R/W semaphores
1106 (*) RCU
1107
1108In all cases there are variants on "LOCK" operations and "UNLOCK" operations
1109for each construct. These operations all imply certain barriers:
1110
1111 (1) LOCK operation implication:
1112
1113 Memory operations issued after the LOCK will be completed after the LOCK
1114 operation has completed.
1115
1116 Memory operations issued before the LOCK may be completed after the LOCK
1117 operation has completed.
1118
1119 (2) UNLOCK operation implication:
1120
1121 Memory operations issued before the UNLOCK will be completed before the
1122 UNLOCK operation has completed.
1123
1124 Memory operations issued after the UNLOCK may be completed before the
1125 UNLOCK operation has completed.
1126
1127 (3) LOCK vs LOCK implication:
1128
1129 All LOCK operations issued before another LOCK operation will be completed
1130 before that LOCK operation.
1131
1132 (4) LOCK vs UNLOCK implication:
1133
1134 All LOCK operations issued before an UNLOCK operation will be completed
1135 before the UNLOCK operation.
1136
1137 All UNLOCK operations issued before a LOCK operation will be completed
1138 before the LOCK operation.
1139
1140 (5) Failed conditional LOCK implication:
1141
1142 Certain variants of the LOCK operation may fail, either due to being
1143 unable to get the lock immediately, or due to receiving an unblocked
1144 signal whilst asleep waiting for the lock to become available. Failed
1145 locks do not imply any sort of barrier.
1146
1147Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
1148equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
1149
1150[!] Note: one of the consequence of LOCKs and UNLOCKs being only one-way
1151 barriers is that the effects instructions outside of a critical section may
1152 seep into the inside of the critical section.
1153
David Howells670bd952006-06-10 09:54:12 -07001154A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
1155because it is possible for an access preceding the LOCK to happen after the
1156LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the
1157two accesses can themselves then cross:
1158
1159 *A = a;
1160 LOCK
1161 UNLOCK
1162 *B = b;
1163
1164may occur as:
1165
1166 LOCK, STORE *B, STORE *A, UNLOCK
1167
David Howells108b42b2006-03-31 16:00:29 +01001168Locks and semaphores may not provide any guarantee of ordering on UP compiled
1169systems, and so cannot be counted on in such a situation to actually achieve
1170anything at all - especially with respect to I/O accesses - unless combined
1171with interrupt disabling operations.
1172
1173See also the section on "Inter-CPU locking barrier effects".
1174
1175
1176As an example, consider the following:
1177
1178 *A = a;
1179 *B = b;
1180 LOCK
1181 *C = c;
1182 *D = d;
1183 UNLOCK
1184 *E = e;
1185 *F = f;
1186
1187The following sequence of events is acceptable:
1188
1189 LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK
1190
1191 [+] Note that {*F,*A} indicates a combined access.
1192
1193But none of the following are:
1194
1195 {*F,*A}, *B, LOCK, *C, *D, UNLOCK, *E
1196 *A, *B, *C, LOCK, *D, UNLOCK, *E, *F
1197 *A, *B, LOCK, *C, UNLOCK, *D, *E, *F
1198 *B, LOCK, *C, *D, UNLOCK, {*F,*A}, *E
1199
1200
1201
1202INTERRUPT DISABLING FUNCTIONS
1203-----------------------------
1204
1205Functions that disable interrupts (LOCK equivalent) and enable interrupts
1206(UNLOCK equivalent) will act as compiler barriers only. So if memory or I/O
1207barriers are required in such a situation, they must be provided from some
1208other means.
1209
1210
1211MISCELLANEOUS FUNCTIONS
1212-----------------------
1213
1214Other functions that imply barriers:
1215
1216 (*) schedule() and similar imply full memory barriers.
1217
David Howells108b42b2006-03-31 16:00:29 +01001218
1219=================================
1220INTER-CPU LOCKING BARRIER EFFECTS
1221=================================
1222
1223On SMP systems locking primitives give a more substantial form of barrier: one
1224that does affect memory access ordering on other CPUs, within the context of
1225conflict on any particular lock.
1226
1227
1228LOCKS VS MEMORY ACCESSES
1229------------------------
1230
Aneesh Kumar79afecf2006-05-15 09:44:36 -07001231Consider the following: the system has a pair of spinlocks (M) and (Q), and
David Howells108b42b2006-03-31 16:00:29 +01001232three CPUs; then should the following sequence of events occur:
1233
1234 CPU 1 CPU 2
1235 =============================== ===============================
1236 *A = a; *E = e;
1237 LOCK M LOCK Q
1238 *B = b; *F = f;
1239 *C = c; *G = g;
1240 UNLOCK M UNLOCK Q
1241 *D = d; *H = h;
1242
1243Then there is no guarantee as to what order CPU #3 will see the accesses to *A
1244through *H occur in, other than the constraints imposed by the separate locks
1245on the separate CPUs. It might, for example, see:
1246
1247 *E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M
1248
1249But it won't see any of:
1250
1251 *B, *C or *D preceding LOCK M
1252 *A, *B or *C following UNLOCK M
1253 *F, *G or *H preceding LOCK Q
1254 *E, *F or *G following UNLOCK Q
1255
1256
1257However, if the following occurs:
1258
1259 CPU 1 CPU 2
1260 =============================== ===============================
1261 *A = a;
1262 LOCK M [1]
1263 *B = b;
1264 *C = c;
1265 UNLOCK M [1]
1266 *D = d; *E = e;
1267 LOCK M [2]
1268 *F = f;
1269 *G = g;
1270 UNLOCK M [2]
1271 *H = h;
1272
1273CPU #3 might see:
1274
1275 *E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
1276 LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
1277
1278But assuming CPU #1 gets the lock first, it won't see any of:
1279
1280 *B, *C, *D, *F, *G or *H preceding LOCK M [1]
1281 *A, *B or *C following UNLOCK M [1]
1282 *F, *G or *H preceding LOCK M [2]
1283 *A, *B, *C, *E, *F or *G following UNLOCK M [2]
1284
1285
1286LOCKS VS I/O ACCESSES
1287---------------------
1288
1289Under certain circumstances (especially involving NUMA), I/O accesses within
1290two spinlocked sections on two different CPUs may be seen as interleaved by the
1291PCI bridge, because the PCI bridge does not necessarily participate in the
1292cache-coherence protocol, and is therefore incapable of issuing the required
1293read memory barriers.
1294
1295For example:
1296
1297 CPU 1 CPU 2
1298 =============================== ===============================
1299 spin_lock(Q)
1300 writel(0, ADDR)
1301 writel(1, DATA);
1302 spin_unlock(Q);
1303 spin_lock(Q);
1304 writel(4, ADDR);
1305 writel(5, DATA);
1306 spin_unlock(Q);
1307
1308may be seen by the PCI bridge as follows:
1309
1310 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
1311
1312which would probably cause the hardware to malfunction.
1313
1314
1315What is necessary here is to intervene with an mmiowb() before dropping the
1316spinlock, for example:
1317
1318 CPU 1 CPU 2
1319 =============================== ===============================
1320 spin_lock(Q)
1321 writel(0, ADDR)
1322 writel(1, DATA);
1323 mmiowb();
1324 spin_unlock(Q);
1325 spin_lock(Q);
1326 writel(4, ADDR);
1327 writel(5, DATA);
1328 mmiowb();
1329 spin_unlock(Q);
1330
1331this will ensure that the two stores issued on CPU #1 appear at the PCI bridge
1332before either of the stores issued on CPU #2.
1333
1334
1335Furthermore, following a store by a load to the same device obviates the need
1336for an mmiowb(), because the load forces the store to complete before the load
1337is performed:
1338
1339 CPU 1 CPU 2
1340 =============================== ===============================
1341 spin_lock(Q)
1342 writel(0, ADDR)
1343 a = readl(DATA);
1344 spin_unlock(Q);
1345 spin_lock(Q);
1346 writel(4, ADDR);
1347 b = readl(DATA);
1348 spin_unlock(Q);
1349
1350
1351See Documentation/DocBook/deviceiobook.tmpl for more information.
1352
1353
1354=================================
1355WHERE ARE MEMORY BARRIERS NEEDED?
1356=================================
1357
1358Under normal operation, memory operation reordering is generally not going to
1359be a problem as a single-threaded linear piece of code will still appear to
1360work correctly, even if it's in an SMP kernel. There are, however, three
1361circumstances in which reordering definitely _could_ be a problem:
1362
1363 (*) Interprocessor interaction.
1364
1365 (*) Atomic operations.
1366
1367 (*) Accessing devices (I/O).
1368
1369 (*) Interrupts.
1370
1371
1372INTERPROCESSOR INTERACTION
1373--------------------------
1374
1375When there's a system with more than one processor, more than one CPU in the
1376system may be working on the same data set at the same time. This can cause
1377synchronisation problems, and the usual way of dealing with them is to use
1378locks. Locks, however, are quite expensive, and so it may be preferable to
1379operate without the use of a lock if at all possible. In such a case
1380operations that affect both CPUs may have to be carefully ordered to prevent
1381a malfunction.
1382
1383Consider, for example, the R/W semaphore slow path. Here a waiting process is
1384queued on the semaphore, by virtue of it having a piece of its stack linked to
1385the semaphore's list of waiting processes:
1386
1387 struct rw_semaphore {
1388 ...
1389 spinlock_t lock;
1390 struct list_head waiters;
1391 };
1392
1393 struct rwsem_waiter {
1394 struct list_head list;
1395 struct task_struct *task;
1396 };
1397
1398To wake up a particular waiter, the up_read() or up_write() functions have to:
1399
1400 (1) read the next pointer from this waiter's record to know as to where the
1401 next waiter record is;
1402
1403 (4) read the pointer to the waiter's task structure;
1404
1405 (3) clear the task pointer to tell the waiter it has been given the semaphore;
1406
1407 (4) call wake_up_process() on the task; and
1408
1409 (5) release the reference held on the waiter's task struct.
1410
1411In otherwords, it has to perform this sequence of events:
1412
1413 LOAD waiter->list.next;
1414 LOAD waiter->task;
1415 STORE waiter->task;
1416 CALL wakeup
1417 RELEASE task
1418
1419and if any of these steps occur out of order, then the whole thing may
1420malfunction.
1421
1422Once it has queued itself and dropped the semaphore lock, the waiter does not
1423get the lock again; it instead just waits for its task pointer to be cleared
1424before proceeding. Since the record is on the waiter's stack, this means that
1425if the task pointer is cleared _before_ the next pointer in the list is read,
1426another CPU might start processing the waiter and might clobber the waiter's
1427stack before the up*() function has a chance to read the next pointer.
1428
1429Consider then what might happen to the above sequence of events:
1430
1431 CPU 1 CPU 2
1432 =============================== ===============================
1433 down_xxx()
1434 Queue waiter
1435 Sleep
1436 up_yyy()
1437 LOAD waiter->task;
1438 STORE waiter->task;
1439 Woken up by other event
1440 <preempt>
1441 Resume processing
1442 down_xxx() returns
1443 call foo()
1444 foo() clobbers *waiter
1445 </preempt>
1446 LOAD waiter->list.next;
1447 --- OOPS ---
1448
1449This could be dealt with using the semaphore lock, but then the down_xxx()
1450function has to needlessly get the spinlock again after being woken up.
1451
1452The way to deal with this is to insert a general SMP memory barrier:
1453
1454 LOAD waiter->list.next;
1455 LOAD waiter->task;
1456 smp_mb();
1457 STORE waiter->task;
1458 CALL wakeup
1459 RELEASE task
1460
1461In this case, the barrier makes a guarantee that all memory accesses before the
1462barrier will appear to happen before all the memory accesses after the barrier
1463with respect to the other CPUs on the system. It does _not_ guarantee that all
1464the memory accesses before the barrier will be complete by the time the barrier
1465instruction itself is complete.
1466
1467On a UP system - where this wouldn't be a problem - the smp_mb() is just a
1468compiler barrier, thus making sure the compiler emits the instructions in the
1469right order without actually intervening in the CPU. Since there there's only
1470one CPU, that CPU's dependency ordering logic will take care of everything
1471else.
1472
1473
1474ATOMIC OPERATIONS
1475-----------------
1476
David Howellsdbc87002006-04-10 22:54:23 -07001477Whilst they are technically interprocessor interaction considerations, atomic
1478operations are noted specially as some of them imply full memory barriers and
1479some don't, but they're very heavily relied on as a group throughout the
1480kernel.
1481
1482Any atomic operation that modifies some state in memory and returns information
1483about the state (old or new) implies an SMP-conditional general memory barrier
1484(smp_mb()) on each side of the actual operation. These include:
David Howells108b42b2006-03-31 16:00:29 +01001485
1486 xchg();
1487 cmpxchg();
David Howells108b42b2006-03-31 16:00:29 +01001488 atomic_cmpxchg();
1489 atomic_inc_return();
1490 atomic_dec_return();
1491 atomic_add_return();
1492 atomic_sub_return();
1493 atomic_inc_and_test();
1494 atomic_dec_and_test();
1495 atomic_sub_and_test();
1496 atomic_add_negative();
1497 atomic_add_unless();
David Howellsdbc87002006-04-10 22:54:23 -07001498 test_and_set_bit();
1499 test_and_clear_bit();
1500 test_and_change_bit();
David Howells108b42b2006-03-31 16:00:29 +01001501
David Howellsdbc87002006-04-10 22:54:23 -07001502These are used for such things as implementing LOCK-class and UNLOCK-class
1503operations and adjusting reference counters towards object destruction, and as
1504such the implicit memory barrier effects are necessary.
David Howells108b42b2006-03-31 16:00:29 +01001505
David Howells108b42b2006-03-31 16:00:29 +01001506
David Howellsdbc87002006-04-10 22:54:23 -07001507The following operation are potential problems as they do _not_ imply memory
1508barriers, but might be used for implementing such things as UNLOCK-class
1509operations:
1510
1511 atomic_set();
David Howells108b42b2006-03-31 16:00:29 +01001512 set_bit();
1513 clear_bit();
1514 change_bit();
David Howellsdbc87002006-04-10 22:54:23 -07001515
1516With these the appropriate explicit memory barrier should be used if necessary
1517(smp_mb__before_clear_bit() for instance).
David Howells108b42b2006-03-31 16:00:29 +01001518
1519
David Howellsdbc87002006-04-10 22:54:23 -07001520The following also do _not_ imply memory barriers, and so may require explicit
1521memory barriers under some circumstances (smp_mb__before_atomic_dec() for
1522instance)):
David Howells108b42b2006-03-31 16:00:29 +01001523
1524 atomic_add();
1525 atomic_sub();
1526 atomic_inc();
1527 atomic_dec();
1528
1529If they're used for statistics generation, then they probably don't need memory
1530barriers, unless there's a coupling between statistical data.
1531
1532If they're used for reference counting on an object to control its lifetime,
1533they probably don't need memory barriers because either the reference count
1534will be adjusted inside a locked section, or the caller will already hold
1535sufficient references to make the lock, and thus a memory barrier unnecessary.
1536
1537If they're used for constructing a lock of some description, then they probably
1538do need memory barriers as a lock primitive generally has to do things in a
1539specific order.
1540
1541
1542Basically, each usage case has to be carefully considered as to whether memory
David Howellsdbc87002006-04-10 22:54:23 -07001543barriers are needed or not.
1544
1545[!] Note that special memory barrier primitives are available for these
1546situations because on some CPUs the atomic instructions used imply full memory
1547barriers, and so barrier instructions are superfluous in conjunction with them,
1548and in such cases the special barrier primitives will be no-ops.
David Howells108b42b2006-03-31 16:00:29 +01001549
1550See Documentation/atomic_ops.txt for more information.
1551
1552
1553ACCESSING DEVICES
1554-----------------
1555
1556Many devices can be memory mapped, and so appear to the CPU as if they're just
1557a set of memory locations. To control such a device, the driver usually has to
1558make the right memory accesses in exactly the right order.
1559
1560However, having a clever CPU or a clever compiler creates a potential problem
1561in that the carefully sequenced accesses in the driver code won't reach the
1562device in the requisite order if the CPU or the compiler thinks it is more
1563efficient to reorder, combine or merge accesses - something that would cause
1564the device to malfunction.
1565
1566Inside of the Linux kernel, I/O should be done through the appropriate accessor
1567routines - such as inb() or writel() - which know how to make such accesses
1568appropriately sequential. Whilst this, for the most part, renders the explicit
1569use of memory barriers unnecessary, there are a couple of situations where they
1570might be needed:
1571
1572 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
1573 so for _all_ general drivers locks should be used and mmiowb() must be
1574 issued prior to unlocking the critical section.
1575
1576 (2) If the accessor functions are used to refer to an I/O memory window with
1577 relaxed memory access properties, then _mandatory_ memory barriers are
1578 required to enforce ordering.
1579
1580See Documentation/DocBook/deviceiobook.tmpl for more information.
1581
1582
1583INTERRUPTS
1584----------
1585
1586A driver may be interrupted by its own interrupt service routine, and thus the
1587two parts of the driver may interfere with each other's attempts to control or
1588access the device.
1589
1590This may be alleviated - at least in part - by disabling local interrupts (a
1591form of locking), such that the critical operations are all contained within
1592the interrupt-disabled section in the driver. Whilst the driver's interrupt
1593routine is executing, the driver's core may not run on the same CPU, and its
1594interrupt is not permitted to happen again until the current interrupt has been
1595handled, thus the interrupt handler does not need to lock against that.
1596
1597However, consider a driver that was talking to an ethernet card that sports an
1598address register and a data register. If that driver's core talks to the card
1599under interrupt-disablement and then the driver's interrupt handler is invoked:
1600
1601 LOCAL IRQ DISABLE
1602 writew(ADDR, 3);
1603 writew(DATA, y);
1604 LOCAL IRQ ENABLE
1605 <interrupt>
1606 writew(ADDR, 4);
1607 q = readw(DATA);
1608 </interrupt>
1609
1610The store to the data register might happen after the second store to the
1611address register if ordering rules are sufficiently relaxed:
1612
1613 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
1614
1615
1616If ordering rules are relaxed, it must be assumed that accesses done inside an
1617interrupt disabled section may leak outside of it and may interleave with
1618accesses performed in an interrupt - and vice versa - unless implicit or
1619explicit barriers are used.
1620
1621Normally this won't be a problem because the I/O accesses done inside such
1622sections will include synchronous load operations on strictly ordered I/O
1623registers that form implicit I/O barriers. If this isn't sufficient then an
1624mmiowb() may need to be used explicitly.
1625
1626
1627A similar situation may occur between an interrupt routine and two routines
1628running on separate CPUs that communicate with each other. If such a case is
1629likely, then interrupt-disabling locks should be used to guarantee ordering.
1630
1631
1632==========================
1633KERNEL I/O BARRIER EFFECTS
1634==========================
1635
1636When accessing I/O memory, drivers should use the appropriate accessor
1637functions:
1638
1639 (*) inX(), outX():
1640
1641 These are intended to talk to I/O space rather than memory space, but
1642 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
1643 indeed have special I/O space access cycles and instructions, but many
1644 CPUs don't have such a concept.
1645
1646 The PCI bus, amongst others, defines an I/O space concept - which on such
1647 CPUs as i386 and x86_64 cpus readily maps to the CPU's concept of I/O
1648 space. However, it may also mapped as a virtual I/O space in the CPU's
1649 memory map, particularly on those CPUs that don't support alternate
1650 I/O spaces.
1651
1652 Accesses to this space may be fully synchronous (as on i386), but
1653 intermediary bridges (such as the PCI host bridge) may not fully honour
1654 that.
1655
1656 They are guaranteed to be fully ordered with respect to each other.
1657
1658 They are not guaranteed to be fully ordered with respect to other types of
1659 memory and I/O operation.
1660
1661 (*) readX(), writeX():
1662
1663 Whether these are guaranteed to be fully ordered and uncombined with
1664 respect to each other on the issuing CPU depends on the characteristics
1665 defined for the memory window through which they're accessing. On later
1666 i386 architecture machines, for example, this is controlled by way of the
1667 MTRR registers.
1668
1669 Ordinarily, these will be guaranteed to be fully ordered and uncombined,,
1670 provided they're not accessing a prefetchable device.
1671
1672 However, intermediary hardware (such as a PCI bridge) may indulge in
1673 deferral if it so wishes; to flush a store, a load from the same location
1674 is preferred[*], but a load from the same device or from configuration
1675 space should suffice for PCI.
1676
1677 [*] NOTE! attempting to load from the same location as was written to may
1678 cause a malfunction - consider the 16550 Rx/Tx serial registers for
1679 example.
1680
1681 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
1682 force stores to be ordered.
1683
1684 Please refer to the PCI specification for more information on interactions
1685 between PCI transactions.
1686
1687 (*) readX_relaxed()
1688
1689 These are similar to readX(), but are not guaranteed to be ordered in any
1690 way. Be aware that there is no I/O read barrier available.
1691
1692 (*) ioreadX(), iowriteX()
1693
1694 These will perform as appropriate for the type of access they're actually
1695 doing, be it inX()/outX() or readX()/writeX().
1696
1697
1698========================================
1699ASSUMED MINIMUM EXECUTION ORDERING MODEL
1700========================================
1701
1702It has to be assumed that the conceptual CPU is weakly-ordered but that it will
1703maintain the appearance of program causality with respect to itself. Some CPUs
1704(such as i386 or x86_64) are more constrained than others (such as powerpc or
1705frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
1706of arch-specific code.
1707
1708This means that it must be considered that the CPU will execute its instruction
1709stream in any order it feels like - or even in parallel - provided that if an
1710instruction in the stream depends on the an earlier instruction, then that
1711earlier instruction must be sufficiently complete[*] before the later
1712instruction may proceed; in other words: provided that the appearance of
1713causality is maintained.
1714
1715 [*] Some instructions have more than one effect - such as changing the
1716 condition codes, changing registers or changing memory - and different
1717 instructions may depend on different effects.
1718
1719A CPU may also discard any instruction sequence that winds up having no
1720ultimate effect. For example, if two adjacent instructions both load an
1721immediate value into the same register, the first may be discarded.
1722
1723
1724Similarly, it has to be assumed that compiler might reorder the instruction
1725stream in any way it sees fit, again provided the appearance of causality is
1726maintained.
1727
1728
1729============================
1730THE EFFECTS OF THE CPU CACHE
1731============================
1732
1733The way cached memory operations are perceived across the system is affected to
1734a certain extent by the caches that lie between CPUs and memory, and by the
1735memory coherence system that maintains the consistency of state in the system.
1736
1737As far as the way a CPU interacts with another part of the system through the
1738caches goes, the memory system has to include the CPU's caches, and memory
1739barriers for the most part act at the interface between the CPU and its cache
1740(memory barriers logically act on the dotted line in the following diagram):
1741
1742 <--- CPU ---> : <----------- Memory ----------->
1743 :
1744 +--------+ +--------+ : +--------+ +-----------+
1745 | | | | : | | | | +--------+
1746 | CPU | | Memory | : | CPU | | | | |
1747 | Core |--->| Access |----->| Cache |<-->| | | |
1748 | | | Queue | : | | | |--->| Memory |
1749 | | | | : | | | | | |
1750 +--------+ +--------+ : +--------+ | | | |
1751 : | Cache | +--------+
1752 : | Coherency |
1753 : | Mechanism | +--------+
1754 +--------+ +--------+ : +--------+ | | | |
1755 | | | | : | | | | | |
1756 | CPU | | Memory | : | CPU | | |--->| Device |
1757 | Core |--->| Access |----->| Cache |<-->| | | |
1758 | | | Queue | : | | | | | |
1759 | | | | : | | | | +--------+
1760 +--------+ +--------+ : +--------+ +-----------+
1761 :
1762 :
1763
1764Although any particular load or store may not actually appear outside of the
1765CPU that issued it since it may have been satisfied within the CPU's own cache,
1766it will still appear as if the full memory access had taken place as far as the
1767other CPUs are concerned since the cache coherency mechanisms will migrate the
1768cacheline over to the accessing CPU and propagate the effects upon conflict.
1769
1770The CPU core may execute instructions in any order it deems fit, provided the
1771expected program causality appears to be maintained. Some of the instructions
1772generate load and store operations which then go into the queue of memory
1773accesses to be performed. The core may place these in the queue in any order
1774it wishes, and continue execution until it is forced to wait for an instruction
1775to complete.
1776
1777What memory barriers are concerned with is controlling the order in which
1778accesses cross from the CPU side of things to the memory side of things, and
1779the order in which the effects are perceived to happen by the other observers
1780in the system.
1781
1782[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
1783their own loads and stores as if they had happened in program order.
1784
1785[!] MMIO or other device accesses may bypass the cache system. This depends on
1786the properties of the memory window through which devices are accessed and/or
1787the use of any special device communication instructions the CPU may have.
1788
1789
1790CACHE COHERENCY
1791---------------
1792
1793Life isn't quite as simple as it may appear above, however: for while the
1794caches are expected to be coherent, there's no guarantee that that coherency
1795will be ordered. This means that whilst changes made on one CPU will
1796eventually become visible on all CPUs, there's no guarantee that they will
1797become apparent in the same order on those other CPUs.
1798
1799
1800Consider dealing with a system that has pair of CPUs (1 & 2), each of which has
1801a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
1802
1803 :
1804 : +--------+
1805 : +---------+ | |
1806 +--------+ : +--->| Cache A |<------->| |
1807 | | : | +---------+ | |
1808 | CPU 1 |<---+ | |
1809 | | : | +---------+ | |
1810 +--------+ : +--->| Cache B |<------->| |
1811 : +---------+ | |
1812 : | Memory |
1813 : +---------+ | System |
1814 +--------+ : +--->| Cache C |<------->| |
1815 | | : | +---------+ | |
1816 | CPU 2 |<---+ | |
1817 | | : | +---------+ | |
1818 +--------+ : +--->| Cache D |<------->| |
1819 : +---------+ | |
1820 : +--------+
1821 :
1822
1823Imagine the system has the following properties:
1824
1825 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
1826 resident in memory;
1827
1828 (*) an even-numbered cache line may be in cache B, cache D or it may still be
1829 resident in memory;
1830
1831 (*) whilst the CPU core is interrogating one cache, the other cache may be
1832 making use of the bus to access the rest of the system - perhaps to
1833 displace a dirty cacheline or to do a speculative load;
1834
1835 (*) each cache has a queue of operations that need to be applied to that cache
1836 to maintain coherency with the rest of the system;
1837
1838 (*) the coherency queue is not flushed by normal loads to lines already
1839 present in the cache, even though the contents of the queue may
1840 potentially effect those loads.
1841
1842Imagine, then, that two writes are made on the first CPU, with a write barrier
1843between them to guarantee that they will appear to reach that CPU's caches in
1844the requisite order:
1845
1846 CPU 1 CPU 2 COMMENT
1847 =============== =============== =======================================
1848 u == 0, v == 1 and p == &u, q == &u
1849 v = 2;
1850 smp_wmb(); Make sure change to v visible before
1851 change to p
1852 <A:modify v=2> v is now in cache A exclusively
1853 p = &v;
1854 <B:modify p=&v> p is now in cache B exclusively
1855
1856The write memory barrier forces the other CPUs in the system to perceive that
1857the local CPU's caches have apparently been updated in the correct order. But
1858now imagine that the second CPU that wants to read those values:
1859
1860 CPU 1 CPU 2 COMMENT
1861 =============== =============== =======================================
1862 ...
1863 q = p;
1864 x = *q;
1865
1866The above pair of reads may then fail to happen in expected order, as the
1867cacheline holding p may get updated in one of the second CPU's caches whilst
1868the update to the cacheline holding v is delayed in the other of the second
1869CPU's caches by some other cache event:
1870
1871 CPU 1 CPU 2 COMMENT
1872 =============== =============== =======================================
1873 u == 0, v == 1 and p == &u, q == &u
1874 v = 2;
1875 smp_wmb();
1876 <A:modify v=2> <C:busy>
1877 <C:queue v=2>
Aneesh Kumar79afecf2006-05-15 09:44:36 -07001878 p = &v; q = p;
David Howells108b42b2006-03-31 16:00:29 +01001879 <D:request p>
1880 <B:modify p=&v> <D:commit p=&v>
1881 <D:read p>
1882 x = *q;
1883 <C:read *q> Reads from v before v updated in cache
1884 <C:unbusy>
1885 <C:commit v=2>
1886
1887Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
1888no guarantee that, without intervention, the order of update will be the same
1889as that committed on CPU 1.
1890
1891
1892To intervene, we need to interpolate a data dependency barrier or a read
1893barrier between the loads. This will force the cache to commit its coherency
1894queue before processing any further requests:
1895
1896 CPU 1 CPU 2 COMMENT
1897 =============== =============== =======================================
1898 u == 0, v == 1 and p == &u, q == &u
1899 v = 2;
1900 smp_wmb();
1901 <A:modify v=2> <C:busy>
1902 <C:queue v=2>
1903 p = &b; q = p;
1904 <D:request p>
1905 <B:modify p=&v> <D:commit p=&v>
1906 <D:read p>
1907 smp_read_barrier_depends()
1908 <C:unbusy>
1909 <C:commit v=2>
1910 x = *q;
1911 <C:read *q> Reads from v after v updated in cache
1912
1913
1914This sort of problem can be encountered on DEC Alpha processors as they have a
1915split cache that improves performance by making better use of the data bus.
1916Whilst most CPUs do imply a data dependency barrier on the read when a memory
1917access depends on a read, not all do, so it may not be relied on.
1918
1919Other CPUs may also have split caches, but must coordinate between the various
1920cachelets for normal memory accesss. The semantics of the Alpha removes the
1921need for coordination in absence of memory barriers.
1922
1923
1924CACHE COHERENCY VS DMA
1925----------------------
1926
1927Not all systems maintain cache coherency with respect to devices doing DMA. In
1928such cases, a device attempting DMA may obtain stale data from RAM because
1929dirty cache lines may be resident in the caches of various CPUs, and may not
1930have been written back to RAM yet. To deal with this, the appropriate part of
1931the kernel must flush the overlapping bits of cache on each CPU (and maybe
1932invalidate them as well).
1933
1934In addition, the data DMA'd to RAM by a device may be overwritten by dirty
1935cache lines being written back to RAM from a CPU's cache after the device has
1936installed its own data, or cache lines simply present in a CPUs cache may
1937simply obscure the fact that RAM has been updated, until at such time as the
1938cacheline is discarded from the CPU's cache and reloaded. To deal with this,
1939the appropriate part of the kernel must invalidate the overlapping bits of the
1940cache on each CPU.
1941
1942See Documentation/cachetlb.txt for more information on cache management.
1943
1944
1945CACHE COHERENCY VS MMIO
1946-----------------------
1947
1948Memory mapped I/O usually takes place through memory locations that are part of
1949a window in the CPU's memory space that have different properties assigned than
1950the usual RAM directed window.
1951
1952Amongst these properties is usually the fact that such accesses bypass the
1953caching entirely and go directly to the device buses. This means MMIO accesses
1954may, in effect, overtake accesses to cached memory that were emitted earlier.
1955A memory barrier isn't sufficient in such a case, but rather the cache must be
1956flushed between the cached memory write and the MMIO access if the two are in
1957any way dependent.
1958
1959
1960=========================
1961THE THINGS CPUS GET UP TO
1962=========================
1963
1964A programmer might take it for granted that the CPU will perform memory
1965operations in exactly the order specified, so that if a CPU is, for example,
1966given the following piece of code to execute:
1967
1968 a = *A;
1969 *B = b;
1970 c = *C;
1971 d = *D;
1972 *E = e;
1973
1974They would then expect that the CPU will complete the memory operation for each
1975instruction before moving on to the next one, leading to a definite sequence of
1976operations as seen by external observers in the system:
1977
1978 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
1979
1980
1981Reality is, of course, much messier. With many CPUs and compilers, the above
1982assumption doesn't hold because:
1983
1984 (*) loads are more likely to need to be completed immediately to permit
1985 execution progress, whereas stores can often be deferred without a
1986 problem;
1987
1988 (*) loads may be done speculatively, and the result discarded should it prove
1989 to have been unnecessary;
1990
1991 (*) loads may be done speculatively, leading to the result having being
1992 fetched at the wrong time in the expected sequence of events;
1993
1994 (*) the order of the memory accesses may be rearranged to promote better use
1995 of the CPU buses and caches;
1996
1997 (*) loads and stores may be combined to improve performance when talking to
1998 memory or I/O hardware that can do batched accesses of adjacent locations,
1999 thus cutting down on transaction setup costs (memory and PCI devices may
2000 both be able to do this); and
2001
2002 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2003 mechanisms may alleviate this - once the store has actually hit the cache
2004 - there's no guarantee that the coherency management will be propagated in
2005 order to other CPUs.
2006
2007So what another CPU, say, might actually observe from the above piece of code
2008is:
2009
2010 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2011
2012 (Where "LOAD {*C,*D}" is a combined load)
2013
2014
2015However, it is guaranteed that a CPU will be self-consistent: it will see its
2016_own_ accesses appear to be correctly ordered, without the need for a memory
2017barrier. For instance with the following code:
2018
2019 U = *A;
2020 *A = V;
2021 *A = W;
2022 X = *A;
2023 *A = Y;
2024 Z = *A;
2025
2026and assuming no intervention by an external influence, it can be assumed that
2027the final result will appear to be:
2028
2029 U == the original value of *A
2030 X == W
2031 Z == Y
2032 *A == Y
2033
2034The code above may cause the CPU to generate the full sequence of memory
2035accesses:
2036
2037 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2038
2039in that order, but, without intervention, the sequence may have almost any
2040combination of elements combined or discarded, provided the program's view of
2041the world remains consistent.
2042
2043The compiler may also combine, discard or defer elements of the sequence before
2044the CPU even sees them.
2045
2046For instance:
2047
2048 *A = V;
2049 *A = W;
2050
2051may be reduced to:
2052
2053 *A = W;
2054
2055since, without a write barrier, it can be assumed that the effect of the
2056storage of V to *A is lost. Similarly:
2057
2058 *A = Y;
2059 Z = *A;
2060
2061may, without a memory barrier, be reduced to:
2062
2063 *A = Y;
2064 Z = Y;
2065
2066and the LOAD operation never appear outside of the CPU.
2067
2068
2069AND THEN THERE'S THE ALPHA
2070--------------------------
2071
2072The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2073some versions of the Alpha CPU have a split data cache, permitting them to have
2074two semantically related cache lines updating at separate times. This is where
2075the data dependency barrier really becomes necessary as this synchronises both
2076caches with the memory coherence system, thus making it seem like pointer
2077changes vs new data occur in the right order.
2078
2079The Alpha defines the Linux's kernel's memory barrier model.
2080
2081See the subsection on "Cache Coherency" above.
2082
2083
2084==========
2085REFERENCES
2086==========
2087
2088Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2089Digital Press)
2090 Chapter 5.2: Physical Address Space Characteristics
2091 Chapter 5.4: Caches and Write Buffers
2092 Chapter 5.5: Data Sharing
2093 Chapter 5.6: Read/Write Ordering
2094
2095AMD64 Architecture Programmer's Manual Volume 2: System Programming
2096 Chapter 7.1: Memory-Access Ordering
2097 Chapter 7.4: Buffering and Combining Memory Writes
2098
2099IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2100System Programming Guide
2101 Chapter 7.1: Locked Atomic Operations
2102 Chapter 7.2: Memory Ordering
2103 Chapter 7.4: Serializing Instructions
2104
2105The SPARC Architecture Manual, Version 9
2106 Chapter 8: Memory Models
2107 Appendix D: Formal Specification of the Memory Models
2108 Appendix J: Programming with the Memory Models
2109
2110UltraSPARC Programmer Reference Manual
2111 Chapter 5: Memory Accesses and Cacheability
2112 Chapter 15: Sparc-V9 Memory Models
2113
2114UltraSPARC III Cu User's Manual
2115 Chapter 9: Memory Models
2116
2117UltraSPARC IIIi Processor User's Manual
2118 Chapter 8: Memory Models
2119
2120UltraSPARC Architecture 2005
2121 Chapter 9: Memory
2122 Appendix D: Formal Specifications of the Memory Models
2123
2124UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2125 Chapter 8: Memory Models
2126 Appendix F: Caches and Cache Coherency
2127
2128Solaris Internals, Core Kernel Architecture, p63-68:
2129 Chapter 3.3: Hardware Considerations for Locks and
2130 Synchronization
2131
2132Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2133for Kernel Programmers:
2134 Chapter 13: Other Memory Models
2135
2136Intel Itanium Architecture Software Developer's Manual: Volume 1:
2137 Section 2.6: Speculation
2138 Section 4.4: Memory Access