blob: 795adfad18bf60694cb32b8ae918b47ab41bc816 [file] [log] [blame]
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Stephen Hemminger793b8832005-09-14 16:06:14 -070018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070026#include <linux/config.h>
Stephen Hemminger793b8832005-09-14 16:06:14 -070027#include <linux/crc32.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070028#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
Andrew Mortond0bbccf2005-11-10 15:29:27 -080032#include <linux/dma-mapping.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070033#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
Stephen Hemminger91c86df2005-12-09 11:34:57 -080040#include <linux/workqueue.h>
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -070041#include <linux/if_vlan.h>
Stephen Hemmingerd70cd512005-12-09 11:35:09 -080042#include <linux/prefetch.h>
shemminger@osdl.orgef743d32005-11-30 11:45:12 -080043#include <linux/mii.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070044
45#include <asm/irq.h>
46
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -070047#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070051#include "sky2.h"
52
53#define DRV_NAME "sky2"
Stephen Hemminger6d4b0f62006-05-08 15:11:34 -070054#define DRV_VERSION "1.3"
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070055#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
shemminger@osdl.org13210ce2005-11-30 11:45:14 -080064#define RX_LE_SIZE 512
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070065#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
shemminger@osdl.orgbea86102005-10-26 12:16:10 -070066#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
shemminger@osdl.org13210ce2005-11-30 11:45:14 -080067#define RX_DEF_PENDING RX_MAX_PENDING
Stephen Hemminger82788c72006-01-17 13:43:10 -080068#define RX_SKB_ALIGN 8
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070069
Stephen Hemminger793b8832005-09-14 16:06:14 -070070#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
Stephen Hemmingerb19666d2006-03-07 11:06:36 -080073#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
Stephen Hemminger793b8832005-09-14 16:06:14 -070074
75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070076#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
Stephen Hemmingercb5d9542006-05-08 15:11:29 -070082#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070084static const u32 default_msg =
Stephen Hemminger793b8832005-09-14 16:06:14 -070085 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
Stephen Hemminger3be92a72006-01-17 13:43:17 -080087 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070088
Stephen Hemminger793b8832005-09-14 16:06:14 -070089static int debug = -1; /* defaults above */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070090module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
Stephen Hemmingerbdb5c582005-12-09 11:34:55 -080093static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -080097static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
Stephen Hemminger01bd7562006-05-08 15:11:30 -0700101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700105static const struct pci_device_id sky2_id_table[] = {
Stephen Hemminger793b8832005-09-14 16:06:14 -0700106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
Stephen Hemminger2d2a3872006-05-17 14:37:04 -0700108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700124 { 0 }
125};
Stephen Hemminger793b8832005-09-14 16:06:14 -0700126
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700127MODULE_DEVICE_TABLE(pci, sky2_id_table);
128
129/* Avoid conditionals by using array */
130static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -0700132static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700133
Stephen Hemminger92f965e2005-12-09 11:34:53 -0800134/* This driver supports yukon2 chipset only */
135static const char *yukon2_name[] = {
136 "XL", /* 0xb3 */
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
139 "EC", /* 0xb6 */
140 "FE", /* 0xb7 */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700141};
142
Stephen Hemminger793b8832005-09-14 16:06:14 -0700143/* Access to external PHY */
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800144static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700145{
146 int i;
147
148 gma_write16(hw, port, GM_SMI_DATA, val);
149 gma_write16(hw, port, GM_SMI_CTRL,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151
152 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700153 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800154 return 0;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700155 udelay(1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700156 }
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800157
Stephen Hemminger793b8832005-09-14 16:06:14 -0700158 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800159 return -ETIMEDOUT;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700160}
161
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800162static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700163{
164 int i;
165
Stephen Hemminger793b8832005-09-14 16:06:14 -0700166 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700167 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168
169 for (i = 0; i < PHY_RETRIES; i++) {
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800170 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
171 *val = gma_read16(hw, port, GM_SMI_DATA);
172 return 0;
173 }
174
Stephen Hemminger793b8832005-09-14 16:06:14 -0700175 udelay(1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700176 }
177
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800178 return -ETIMEDOUT;
179}
180
181static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
182{
183 u16 v;
184
185 if (__gm_phy_read(hw, port, reg, &v) != 0)
186 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
187 return v;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700188}
189
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700190static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
191{
192 u16 power_control;
193 u32 reg1;
194 int vaux;
195 int ret = 0;
196
197 pr_debug("sky2_set_power_state %d\n", state);
198 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
199
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800200 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
Stephen Hemminger08c06d82006-01-30 11:37:54 -0800201 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700202 (power_control & PCI_PM_CAP_PME_D3cold);
203
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700205
206 power_control |= PCI_PM_CTRL_PME_STATUS;
207 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
208
209 switch (state) {
210 case PCI_D0:
211 /* switch power to VCC (WA for VAUX problem) */
212 sky2_write8(hw, B0_POWER_CTRL,
213 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
214
215 /* disable Core Clock Division, */
216 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
217
218 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
219 /* enable bits are inverted */
220 sky2_write8(hw, B2_Y2_CLK_GATE,
221 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
222 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
223 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
224 else
225 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
226
227 /* Turn off phy power saving */
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800228 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700229 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700231 /* looks like this XL is back asswards .. */
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
233 reg1 |= PCI_Y2_PHY1_COMA;
234 if (hw->ports > 1)
235 reg1 |= PCI_Y2_PHY2_COMA;
236 }
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800237
238 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
240 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800241 reg1 &= P_ASPM_CONTROL_MSK;
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800242 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
243 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800244 }
245
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800246 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800247
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700248 break;
249
250 case PCI_D3hot:
251 case PCI_D3cold:
252 /* Turn on phy power saving */
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800253 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700254 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
255 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
256 else
257 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800258 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700259
260 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
261 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
262 else
263 /* enable bits are inverted */
264 sky2_write8(hw, B2_Y2_CLK_GATE,
265 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
266 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
267 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
268
269 /* switch power to VAUX */
270 if (vaux && state != PCI_D3cold)
271 sky2_write8(hw, B0_POWER_CTRL,
272 (PC_VAUX_ENA | PC_VCC_ENA |
273 PC_VAUX_ON | PC_VCC_OFF));
274 break;
275 default:
276 printk(KERN_ERR PFX "Unknown power state %d\n", state);
277 ret = -1;
278 }
279
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800280 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700281 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
282 return ret;
283}
284
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700285static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
286{
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
291 /* disable PHY IRQs */
292 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700293
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302}
303
304static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
305{
306 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700307 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700308
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700309 if (sky2->autoneg == AUTONEG_ENABLE &&
310 (hw->chip_id != CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700311 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
312
313 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
Stephen Hemminger793b8832005-09-14 16:06:14 -0700314 PHY_M_EC_MAC_S_MSK);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700315 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
316
317 if (hw->chip_id == CHIP_ID_YUKON_EC)
318 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
319 else
320 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
321
322 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
323 }
324
325 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
326 if (hw->copper) {
327 if (hw->chip_id == CHIP_ID_YUKON_FE) {
328 /* enable automatic crossover */
329 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
330 } else {
331 /* disable energy detect */
332 ctrl &= ~PHY_M_PC_EN_DET_MSK;
333
334 /* enable automatic crossover */
335 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
336
337 if (sky2->autoneg == AUTONEG_ENABLE &&
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700338 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700339 ctrl &= ~PHY_M_PC_DSC_MSK;
340 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
341 }
342 }
343 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
344 } else {
345 /* workaround for deviation #4.88 (CRC errors) */
346 /* disable Automatic Crossover */
347
348 ctrl &= ~PHY_M_PC_MDIX_MSK;
349 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
350
351 if (hw->chip_id == CHIP_ID_YUKON_XL) {
352 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
353 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
355 ctrl &= ~PHY_M_MAC_MD_MSK;
356 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
358
359 /* select page 1 to access Fiber registers */
360 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
361 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700362 }
363
364 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
365 if (sky2->autoneg == AUTONEG_DISABLE)
366 ctrl &= ~PHY_CT_ANE;
367 else
368 ctrl |= PHY_CT_ANE;
369
370 ctrl |= PHY_CT_RESET;
371 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
372
373 ctrl = 0;
374 ct1000 = 0;
375 adv = PHY_AN_CSMA;
376
377 if (sky2->autoneg == AUTONEG_ENABLE) {
378 if (hw->copper) {
379 if (sky2->advertising & ADVERTISED_1000baseT_Full)
380 ct1000 |= PHY_M_1000C_AFD;
381 if (sky2->advertising & ADVERTISED_1000baseT_Half)
382 ct1000 |= PHY_M_1000C_AHD;
383 if (sky2->advertising & ADVERTISED_100baseT_Full)
384 adv |= PHY_M_AN_100_FD;
385 if (sky2->advertising & ADVERTISED_100baseT_Half)
386 adv |= PHY_M_AN_100_HD;
387 if (sky2->advertising & ADVERTISED_10baseT_Full)
388 adv |= PHY_M_AN_10_FD;
389 if (sky2->advertising & ADVERTISED_10baseT_Half)
390 adv |= PHY_M_AN_10_HD;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700391 } else /* special defines for FIBER (88E1011S only) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700392 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
393
394 /* Set Flow-control capabilities */
395 if (sky2->tx_pause && sky2->rx_pause)
Stephen Hemminger793b8832005-09-14 16:06:14 -0700396 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700397 else if (sky2->rx_pause && !sky2->tx_pause)
Stephen Hemminger793b8832005-09-14 16:06:14 -0700398 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700399 else if (!sky2->rx_pause && sky2->tx_pause)
400 adv |= PHY_AN_PAUSE_ASYM; /* local */
401
402 /* Restart Auto-negotiation */
403 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
404 } else {
405 /* forced speed/duplex settings */
406 ct1000 = PHY_M_1000C_MSE;
407
408 if (sky2->duplex == DUPLEX_FULL)
409 ctrl |= PHY_CT_DUP_MD;
410
411 switch (sky2->speed) {
412 case SPEED_1000:
413 ctrl |= PHY_CT_SP1000;
414 break;
415 case SPEED_100:
416 ctrl |= PHY_CT_SP100;
417 break;
418 }
419
420 ctrl |= PHY_CT_RESET;
421 }
422
423 if (hw->chip_id != CHIP_ID_YUKON_FE)
424 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
425
426 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
427 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
428
429 /* Setup Phy LED's */
430 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
431 ledover = 0;
432
433 switch (hw->chip_id) {
434 case CHIP_ID_YUKON_FE:
435 /* on 88E3082 these bits are at 11..9 (shifted left) */
436 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
437
438 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
439
440 /* delete ACT LED control bits */
441 ctrl &= ~PHY_M_FELP_LED1_MSK;
442 /* change ACT LED control to blink mode */
443 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
444 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
445 break;
446
447 case CHIP_ID_YUKON_XL:
Stephen Hemminger793b8832005-09-14 16:06:14 -0700448 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700449
450 /* select page 3 to access LED control register */
451 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
452
453 /* set LED Function Control register */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700454 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
455 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
456 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
457 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
458 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700459
460 /* set Polarity Control register */
461 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
Stephen Hemminger793b8832005-09-14 16:06:14 -0700462 (PHY_M_POLC_LS1_P_MIX(4) |
463 PHY_M_POLC_IS0_P_MIX(4) |
464 PHY_M_POLC_LOS_CTRL(2) |
465 PHY_M_POLC_INIT_CTRL(2) |
466 PHY_M_POLC_STA1_CTRL(2) |
467 PHY_M_POLC_STA0_CTRL(2)));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700468
469 /* restore page register */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700470 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700471 break;
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700472 case CHIP_ID_YUKON_EC_U:
473 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
474
475 /* select page 3 to access LED control register */
476 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
477
478 /* set LED Function Control register */
479 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
480 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
481 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
482 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
483 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
484
485 /* set Blink Rate in LED Timer Control Register */
486 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
487 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
488 /* restore page register */
489 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
490 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700491
492 default:
493 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
494 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
495 /* turn off the Rx LED (LED_RX) */
496 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
497 }
498
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700499 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800500 /* apply fixes in PHY AFE */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700501 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
503
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800504 /* increase differential signal amplitude in 10BASE-T */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700505 gm_phy_write(hw, port, 0x18, 0xaa99);
506 gm_phy_write(hw, port, 0x17, 0x2011);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700507
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800508 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700509 gm_phy_write(hw, port, 0x18, 0xa204);
510 gm_phy_write(hw, port, 0x17, 0x2002);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800511
512 /* set page register to 0 */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800514 } else {
515 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
516
517 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
518 /* turn on 100 Mbps LED (LED_LINK100) */
519 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
520 }
521
522 if (ledover)
523 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
524
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700525 }
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700526 /* Enable phy interrupt on auto-negotiation complete (or link up) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700527 if (sky2->autoneg == AUTONEG_ENABLE)
528 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
529 else
530 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
531}
532
Stephen Hemminger1b537562005-12-20 15:08:07 -0800533/* Force a renegotiation */
534static void sky2_phy_reinit(struct sky2_port *sky2)
535{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800536 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger1b537562005-12-20 15:08:07 -0800537 sky2_phy_init(sky2->hw, sky2->port);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800538 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger1b537562005-12-20 15:08:07 -0800539}
540
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700541static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
542{
543 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
544 u16 reg;
545 int i;
546 const u8 *addr = hw->dev[port]->dev_addr;
547
shemminger@osdl.org42eeea02005-11-30 11:45:13 -0800548 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
549 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700550
551 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
552
Stephen Hemminger793b8832005-09-14 16:06:14 -0700553 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700554 /* WA DEV_472 -- looks like crossed wires on port 2 */
555 /* clear GMAC 1 Control reset */
556 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
557 do {
558 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
559 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
560 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
561 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
562 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
563 }
564
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700565 if (sky2->autoneg == AUTONEG_DISABLE) {
566 reg = gma_read16(hw, port, GM_GP_CTRL);
567 reg |= GM_GPCR_AU_ALL_DIS;
568 gma_write16(hw, port, GM_GP_CTRL, reg);
569 gma_read16(hw, port, GM_GP_CTRL);
570
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700571 switch (sky2->speed) {
572 case SPEED_1000:
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -0800573 reg &= ~GM_GPCR_SPEED_100;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700574 reg |= GM_GPCR_SPEED_1000;
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -0800575 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700576 case SPEED_100:
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -0800577 reg &= ~GM_GPCR_SPEED_1000;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700578 reg |= GM_GPCR_SPEED_100;
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -0800579 break;
580 case SPEED_10:
581 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
582 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700583 }
584
585 if (sky2->duplex == DUPLEX_FULL)
586 reg |= GM_GPCR_DUP_FULL;
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700587
588 /* turn off pause in 10/100mbps half duplex */
589 else if (sky2->speed != SPEED_1000 &&
590 hw->chip_id != CHIP_ID_YUKON_EC_U)
591 sky2->tx_pause = sky2->rx_pause = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700592 } else
593 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
594
595 if (!sky2->tx_pause && !sky2->rx_pause) {
596 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700597 reg |=
598 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
599 } else if (sky2->tx_pause && !sky2->rx_pause) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700600 /* disable Rx flow-control */
601 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
602 }
603
604 gma_write16(hw, port, GM_GP_CTRL, reg);
605
Stephen Hemminger793b8832005-09-14 16:06:14 -0700606 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700607
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800608 spin_lock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700609 sky2_phy_init(hw, port);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800610 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700611
612 /* MIB clear */
613 reg = gma_read16(hw, port, GM_PHY_ADDR);
614 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
615
Stephen Hemminger43f2f102006-04-05 17:47:15 -0700616 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
617 gma_read16(hw, port, i);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700618 gma_write16(hw, port, GM_PHY_ADDR, reg);
619
620 /* transmit control */
621 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
622
623 /* receive control reg: unicast + multicast + no FCS */
624 gma_write16(hw, port, GM_RX_CTRL,
Stephen Hemminger793b8832005-09-14 16:06:14 -0700625 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700626
627 /* transmit flow control */
628 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
629
630 /* transmit parameter */
631 gma_write16(hw, port, GM_TX_PARAM,
632 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
633 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
634 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
635 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
636
637 /* serial mode register */
638 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700639 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700640
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700641 if (hw->dev[port]->mtu > ETH_DATA_LEN)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700642 reg |= GM_SMOD_JUMBO_ENA;
643
644 gma_write16(hw, port, GM_SERIAL_MODE, reg);
645
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700646 /* virtual address for data */
647 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
648
Stephen Hemminger793b8832005-09-14 16:06:14 -0700649 /* physical address: used for pause frames */
650 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
651
652 /* ignore counter overflows */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700653 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
654 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
655 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
656
657 /* Configure Rx MAC FIFO */
658 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
Stephen Hemminger70f1be42006-03-07 11:06:37 -0800659 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
660 GMF_OPER_ON | GMF_RX_F_FL_ON);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700661
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700662 /* Flush Rx MAC FIFO on any flow control or error */
shemminger@osdl.org42eeea02005-11-30 11:45:13 -0800663 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700664
Stephen Hemminger793b8832005-09-14 16:06:14 -0700665 /* Set threshold to 0xa (64 bytes)
666 * ASF disabled so no need to do WA dev #4.30
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700667 */
668 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
669
670 /* Configure Tx MAC FIFO */
671 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
672 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800673
674 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
675 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
676 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
677 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
678 /* set Tx GMAC FIFO Almost Empty Threshold */
679 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
680 /* Disable Store & Forward mode for TX */
681 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
682 }
683 }
684
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700685}
686
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800687/* Assign Ram Buffer allocation.
688 * start and end are in units of 4k bytes
689 * ram registers are in units of 64bit words
690 */
691static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700692{
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800693 u32 start, end;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700694
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800695 start = startk * 4096/8;
696 end = (endk * 4096/8) - 1;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700697
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700698 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
699 sky2_write32(hw, RB_ADDR(q, RB_START), start);
700 sky2_write32(hw, RB_ADDR(q, RB_END), end);
701 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
702 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
703
704 if (q == Q_R1 || q == Q_R2) {
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800705 u32 space = (endk - startk) * 4096/8;
706 u32 tp = space - space/4;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700707
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800708 /* On receive queue's set the thresholds
709 * give receiver priority when > 3/4 full
710 * send pause when down to 2K
711 */
712 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
713 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700714
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800715 tp = space - 2048/8;
716 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
717 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700718 } else {
719 /* Enable store & forward on Tx queue's because
720 * Tx FIFO is only 1K on Yukon
721 */
722 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
723 }
724
725 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700726 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700727}
728
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700729/* Setup Bus Memory Interface */
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800730static void sky2_qset(struct sky2_hw *hw, u16 q)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700731{
732 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
733 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
734 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800735 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700736}
737
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700738/* Setup prefetch unit registers. This is the interface between
739 * hardware and driver list elements
740 */
Stephen Hemminger8cc048e2005-12-09 11:35:07 -0800741static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700742 u64 addr, u32 last)
743{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700744 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
745 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
746 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
747 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
748 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
749 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700750
751 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700752}
753
Stephen Hemminger793b8832005-09-14 16:06:14 -0700754static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
755{
756 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
757
Stephen Hemmingercb5d9542006-05-08 15:11:29 -0700758 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700759 return le;
760}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700761
Stephen Hemminger290d4de2006-03-20 15:48:15 -0800762/* Update chip's next pointer */
763static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700764{
Stephen Hemminger762c2de2006-01-17 13:43:14 -0800765 wmb();
Stephen Hemminger290d4de2006-03-20 15:48:15 -0800766 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
Stephen Hemminger762c2de2006-01-17 13:43:14 -0800767 mmiowb();
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700768}
769
Stephen Hemminger793b8832005-09-14 16:06:14 -0700770
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700771static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
772{
773 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
Stephen Hemmingercb5d9542006-05-08 15:11:29 -0700774 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700775 return le;
776}
777
shemminger@osdl.orga018e332005-11-30 11:45:16 -0800778/* Return high part of DMA address (could be 32 or 64 bit) */
779static inline u32 high32(dma_addr_t a)
780{
Stephen Hemmingera0361192006-01-17 13:43:16 -0800781 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
shemminger@osdl.orga018e332005-11-30 11:45:16 -0800782}
783
Stephen Hemminger793b8832005-09-14 16:06:14 -0700784/* Build description to hardware about buffer */
Stephen Hemminger28bd1812006-01-17 13:43:19 -0800785static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700786{
787 struct sky2_rx_le *le;
Stephen Hemminger734d1862005-12-09 11:35:00 -0800788 u32 hi = high32(map);
789 u16 len = sky2->rx_bufsize;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700790
Stephen Hemminger793b8832005-09-14 16:06:14 -0700791 if (sky2->rx_addr64 != hi) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700792 le = sky2_next_rx(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700793 le->addr = cpu_to_le32(hi);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700794 le->ctrl = 0;
795 le->opcode = OP_ADDR64 | HW_OWNER;
Stephen Hemminger734d1862005-12-09 11:35:00 -0800796 sky2->rx_addr64 = high32(map + len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700797 }
Stephen Hemminger793b8832005-09-14 16:06:14 -0700798
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700799 le = sky2_next_rx(sky2);
Stephen Hemminger734d1862005-12-09 11:35:00 -0800800 le->addr = cpu_to_le32((u32) map);
801 le->length = cpu_to_le16(len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700802 le->ctrl = 0;
803 le->opcode = OP_PACKET | HW_OWNER;
804}
805
Stephen Hemminger793b8832005-09-14 16:06:14 -0700806
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700807/* Tell chip where to start receive checksum.
808 * Actually has two checksums, but set both same to avoid possible byte
809 * order problems.
810 */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700811static void rx_set_checksum(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700812{
813 struct sky2_rx_le *le;
814
Stephen Hemminger793b8832005-09-14 16:06:14 -0700815 le = sky2_next_rx(sky2);
816 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
817 le->ctrl = 0;
818 le->opcode = OP_TCPSTART | HW_OWNER;
819
Stephen Hemminger793b8832005-09-14 16:06:14 -0700820 sky2_write32(sky2->hw,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700821 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
822 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
823
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700824}
825
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700826/*
827 * The RX Stop command will not work for Yukon-2 if the BMU does not
828 * reach the end of packet and since we can't make sure that we have
829 * incoming data, we must reset the BMU while it is not doing a DMA
830 * transfer. Since it is possible that the RX path is still active,
831 * the RX RAM buffer will be stopped first, so any possible incoming
832 * data will not trigger a DMA. After the RAM buffer is stopped, the
833 * BMU is polled until any DMA in progress is ended and only then it
834 * will be reset.
835 */
836static void sky2_rx_stop(struct sky2_port *sky2)
837{
838 struct sky2_hw *hw = sky2->hw;
839 unsigned rxq = rxqaddr[sky2->port];
840 int i;
841
842 /* disable the RAM Buffer receive queue */
843 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
844
845 for (i = 0; i < 0xffff; i++)
846 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
847 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
848 goto stopped;
849
850 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
851 sky2->netdev->name);
852stopped:
853 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
854
855 /* reset the Rx prefetch unit */
856 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
857}
Stephen Hemminger793b8832005-09-14 16:06:14 -0700858
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700859/* Clean out receive buffer area, assumes receiver hardware stopped */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700860static void sky2_rx_clean(struct sky2_port *sky2)
861{
862 unsigned i;
863
864 memset(sky2->rx_le, 0, RX_LE_BYTES);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700865 for (i = 0; i < sky2->rx_pending; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700866 struct ring_info *re = sky2->rx_ring + i;
867
868 if (re->skb) {
Stephen Hemminger793b8832005-09-14 16:06:14 -0700869 pci_unmap_single(sky2->hw->pdev,
Stephen Hemminger734d1862005-12-09 11:35:00 -0800870 re->mapaddr, sky2->rx_bufsize,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700871 PCI_DMA_FROMDEVICE);
872 kfree_skb(re->skb);
873 re->skb = NULL;
874 }
875 }
876}
877
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800878/* Basic MII support */
879static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
880{
881 struct mii_ioctl_data *data = if_mii(ifr);
882 struct sky2_port *sky2 = netdev_priv(dev);
883 struct sky2_hw *hw = sky2->hw;
884 int err = -EOPNOTSUPP;
885
886 if (!netif_running(dev))
887 return -ENODEV; /* Phy still in reset */
888
Stephen Hemmingerd89e1342006-03-20 15:48:20 -0800889 switch (cmd) {
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800890 case SIOCGMIIPHY:
891 data->phy_id = PHY_ADDR_MARV;
892
893 /* fallthru */
894 case SIOCGMIIREG: {
895 u16 val = 0;
Stephen Hemminger91c86df2005-12-09 11:34:57 -0800896
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800897 spin_lock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800898 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800899 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -0800900
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800901 data->val_out = val;
902 break;
903 }
904
905 case SIOCSMIIREG:
906 if (!capable(CAP_NET_ADMIN))
907 return -EPERM;
908
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800909 spin_lock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800910 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
911 data->val_in);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800912 spin_unlock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800913 break;
914 }
915 return err;
916}
917
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700918#ifdef SKY2_VLAN_TAG_USED
919static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
920{
921 struct sky2_port *sky2 = netdev_priv(dev);
922 struct sky2_hw *hw = sky2->hw;
923 u16 port = sky2->port;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700924
Stephen Hemminger302d1252006-01-17 13:43:20 -0800925 spin_lock_bh(&sky2->tx_lock);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700926
927 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
928 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
929 sky2->vlgrp = grp;
930
Stephen Hemminger302d1252006-01-17 13:43:20 -0800931 spin_unlock_bh(&sky2->tx_lock);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700932}
933
934static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
935{
936 struct sky2_port *sky2 = netdev_priv(dev);
937 struct sky2_hw *hw = sky2->hw;
938 u16 port = sky2->port;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700939
Stephen Hemminger302d1252006-01-17 13:43:20 -0800940 spin_lock_bh(&sky2->tx_lock);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700941
942 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
943 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
944 if (sky2->vlgrp)
945 sky2->vlgrp->vlan_devices[vid] = NULL;
946
Stephen Hemminger302d1252006-01-17 13:43:20 -0800947 spin_unlock_bh(&sky2->tx_lock);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700948}
949#endif
950
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700951/*
Stephen Hemminger82788c72006-01-17 13:43:10 -0800952 * It appears the hardware has a bug in the FIFO logic that
953 * cause it to hang if the FIFO gets overrun and the receive buffer
954 * is not aligned. ALso alloc_skb() won't align properly if slab
955 * debugging is enabled.
956 */
957static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
958{
959 struct sk_buff *skb;
960
961 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
962 if (likely(skb)) {
963 unsigned long p = (unsigned long) skb->data;
Stephen Hemminger4a15d562006-04-25 10:58:52 -0700964 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
Stephen Hemminger82788c72006-01-17 13:43:10 -0800965 }
966
967 return skb;
968}
969
970/*
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700971 * Allocate and setup receiver buffer pool.
972 * In case of 64 bit dma, there are 2X as many list elements
973 * available as ring entries
974 * and need to reserve one list element so we don't wrap around.
975 */
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700976static int sky2_rx_start(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700977{
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700978 struct sky2_hw *hw = sky2->hw;
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700979 unsigned rxq = rxqaddr[sky2->port];
980 int i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700981
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700982 sky2->rx_put = sky2->rx_next = 0;
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800983 sky2_qset(hw, rxq);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800984
985 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
986 /* MAC Rx RAM Read is controlled by hardware */
987 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
988 }
989
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700990 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
991
992 rx_set_checksum(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700993 for (i = 0; i < sky2->rx_pending; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700994 struct ring_info *re = sky2->rx_ring + i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700995
Stephen Hemminger82788c72006-01-17 13:43:10 -0800996 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700997 if (!re->skb)
998 goto nomem;
999
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001000 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
Stephen Hemminger734d1862005-12-09 11:35:00 -08001001 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1002 sky2_rx_add(sky2, re->mapaddr);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001003 }
1004
Stephen Hemminger70f1be42006-03-07 11:06:37 -08001005 /* Truncate oversize frames */
1006 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
1007 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1008
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001009 /* Tell chip about available buffers */
1010 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001011 return 0;
1012nomem:
1013 sky2_rx_clean(sky2);
1014 return -ENOMEM;
1015}
1016
1017/* Bring up network interface. */
1018static int sky2_up(struct net_device *dev)
1019{
1020 struct sky2_port *sky2 = netdev_priv(dev);
1021 struct sky2_hw *hw = sky2->hw;
1022 unsigned port = sky2->port;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001023 u32 ramsize, rxspace, imask;
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001024 int cap, err = -ENOMEM;
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001025 struct net_device *otherdev = hw->dev[sky2->port^1];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001026
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001027 /*
1028 * On dual port PCI-X card, there is an problem where status
1029 * can be received out of order due to split transactions
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001030 */
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001031 if (otherdev && netif_running(otherdev) &&
1032 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1033 struct sky2_port *osky2 = netdev_priv(otherdev);
1034 u16 cmd;
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001035
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001036 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1037 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1038 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1039
1040 sky2->rx_csum = 0;
1041 osky2->rx_csum = 0;
1042 }
1043
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001044 if (netif_msg_ifup(sky2))
1045 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1046
1047 /* must be power of 2 */
1048 sky2->tx_le = pci_alloc_consistent(hw->pdev,
Stephen Hemminger793b8832005-09-14 16:06:14 -07001049 TX_RING_SIZE *
1050 sizeof(struct sky2_tx_le),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001051 &sky2->tx_le_map);
1052 if (!sky2->tx_le)
1053 goto err_out;
1054
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001055 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001056 GFP_KERNEL);
1057 if (!sky2->tx_ring)
1058 goto err_out;
1059 sky2->tx_prod = sky2->tx_cons = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001060
1061 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1062 &sky2->rx_le_map);
1063 if (!sky2->rx_le)
1064 goto err_out;
1065 memset(sky2->rx_le, 0, RX_LE_BYTES);
1066
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001067 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001068 GFP_KERNEL);
1069 if (!sky2->rx_ring)
1070 goto err_out;
1071
1072 sky2_mac_init(hw, port);
1073
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001074 /* Determine available ram buffer space (in 4K blocks).
1075 * Note: not sure about the FE setting below yet
1076 */
1077 if (hw->chip_id == CHIP_ID_YUKON_FE)
1078 ramsize = 4;
1079 else
1080 ramsize = sky2_read8(hw, B2_E_0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001081
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001082 /* Give transmitter one third (rounded up) */
1083 rxspace = ramsize - (ramsize + 2) / 3;
1084
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001085 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001086 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001087
Stephen Hemminger793b8832005-09-14 16:06:14 -07001088 /* Make sure SyncQ is disabled */
1089 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1090 RB_RST_SET);
1091
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -08001092 sky2_qset(hw, txqaddr[port]);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001093
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001094 /* Set almost empty threshold */
1095 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1096 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001097
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001098 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1099 TX_RING_SIZE - 1);
1100
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001101 err = sky2_rx_start(sky2);
1102 if (err)
1103 goto err_out;
1104
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001105 /* Enable interrupts from phy/mac for port */
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001106 imask = sky2_read32(hw, B0_IMSK);
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -07001107 imask |= portirq_msk[port];
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001108 sky2_write32(hw, B0_IMSK, imask);
1109
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001110 return 0;
1111
1112err_out:
Stephen Hemminger1b537562005-12-20 15:08:07 -08001113 if (sky2->rx_le) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001114 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1115 sky2->rx_le, sky2->rx_le_map);
Stephen Hemminger1b537562005-12-20 15:08:07 -08001116 sky2->rx_le = NULL;
1117 }
1118 if (sky2->tx_le) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001119 pci_free_consistent(hw->pdev,
1120 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1121 sky2->tx_le, sky2->tx_le_map);
Stephen Hemminger1b537562005-12-20 15:08:07 -08001122 sky2->tx_le = NULL;
1123 }
1124 kfree(sky2->tx_ring);
1125 kfree(sky2->rx_ring);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001126
Stephen Hemminger1b537562005-12-20 15:08:07 -08001127 sky2->tx_ring = NULL;
1128 sky2->rx_ring = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001129 return err;
1130}
1131
Stephen Hemminger793b8832005-09-14 16:06:14 -07001132/* Modular subtraction in ring */
1133static inline int tx_dist(unsigned tail, unsigned head)
1134{
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001135 return (head - tail) & (TX_RING_SIZE - 1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001136}
1137
1138/* Number of list elements available for next tx */
1139static inline int tx_avail(const struct sky2_port *sky2)
1140{
1141 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1142}
1143
1144/* Estimate of number of transmit list elements required */
Stephen Hemminger28bd1812006-01-17 13:43:19 -08001145static unsigned tx_le_req(const struct sk_buff *skb)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001146{
1147 unsigned count;
1148
1149 count = sizeof(dma_addr_t) / sizeof(u32);
1150 count += skb_shinfo(skb)->nr_frags * count;
1151
1152 if (skb_shinfo(skb)->tso_size)
1153 ++count;
1154
Stephen Hemminger0e3ff6a2005-12-09 11:35:02 -08001155 if (skb->ip_summed == CHECKSUM_HW)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001156 ++count;
1157
1158 return count;
1159}
1160
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001161/*
Stephen Hemminger793b8832005-09-14 16:06:14 -07001162 * Put one packet in ring for transmit.
1163 * A single packet can generate multiple list elements, and
1164 * the number of ring elements will probably be less than the number
1165 * of list elements used.
Stephen Hemmingerf2e46562005-12-09 11:34:58 -08001166 *
1167 * No BH disabling for tx_lock here (like tg3)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001168 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001169static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1170{
1171 struct sky2_port *sky2 = netdev_priv(dev);
1172 struct sky2_hw *hw = sky2->hw;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001173 struct sky2_tx_le *le = NULL;
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001174 struct tx_ring_info *re;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001175 unsigned i, len;
Stephen Hemmingerb19666d2006-03-07 11:06:36 -08001176 int avail;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001177 dma_addr_t mapping;
1178 u32 addr64;
1179 u16 mss;
1180 u8 ctrl;
1181
Stephen Hemminger302d1252006-01-17 13:43:20 -08001182 /* No BH disabling for tx_lock here. We are running in BH disabled
1183 * context and TX reclaim runs via poll inside of a software
1184 * interrupt, and no related locks in IRQ processing.
1185 */
Stephen Hemmingerf2e46562005-12-09 11:34:58 -08001186 if (!spin_trylock(&sky2->tx_lock))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001187 return NETDEV_TX_LOCKED;
1188
Stephen Hemminger793b8832005-09-14 16:06:14 -07001189 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
Stephen Hemminger8c463ef2005-12-09 11:35:08 -08001190 /* There is a known but harmless race with lockless tx
1191 * and netif_stop_queue.
1192 */
1193 if (!netif_queue_stopped(dev)) {
1194 netif_stop_queue(dev);
Stephen Hemminger3be92a72006-01-17 13:43:17 -08001195 if (net_ratelimit())
1196 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1197 dev->name);
Stephen Hemminger8c463ef2005-12-09 11:35:08 -08001198 }
Stephen Hemmingerf2e46562005-12-09 11:34:58 -08001199 spin_unlock(&sky2->tx_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001200
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001201 return NETDEV_TX_BUSY;
1202 }
1203
Stephen Hemminger793b8832005-09-14 16:06:14 -07001204 if (unlikely(netif_msg_tx_queued(sky2)))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001205 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1206 dev->name, sky2->tx_prod, skb->len);
1207
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001208 len = skb_headlen(skb);
1209 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001210 addr64 = high32(mapping);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001211
1212 re = sky2->tx_ring + sky2->tx_prod;
1213
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001214 /* Send high bits if changed or crosses boundary */
1215 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001216 le = get_tx_le(sky2);
1217 le->tx.addr = cpu_to_le32(addr64);
1218 le->ctrl = 0;
1219 le->opcode = OP_ADDR64 | HW_OWNER;
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001220 sky2->tx_addr64 = high32(mapping + len);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001221 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001222
1223 /* Check for TCP Segmentation Offload */
1224 mss = skb_shinfo(skb)->tso_size;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001225 if (mss != 0) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001226 /* just drop the packet if non-linear expansion fails */
1227 if (skb_header_cloned(skb) &&
1228 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
Stephen Hemminger15240072006-03-23 08:51:38 -08001229 dev_kfree_skb(skb);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001230 goto out_unlock;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001231 }
1232
1233 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1234 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1235 mss += ETH_HLEN;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001236 }
1237
Stephen Hemminger793b8832005-09-14 16:06:14 -07001238 if (mss != sky2->tx_last_mss) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001239 le = get_tx_le(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001240 le->tx.tso.size = cpu_to_le16(mss);
1241 le->tx.tso.rsvd = 0;
1242 le->opcode = OP_LRGLEN | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001243 le->ctrl = 0;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001244 sky2->tx_last_mss = mss;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001245 }
1246
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001247 ctrl = 0;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001248#ifdef SKY2_VLAN_TAG_USED
1249 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1250 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1251 if (!le) {
1252 le = get_tx_le(sky2);
1253 le->tx.addr = 0;
1254 le->opcode = OP_VLAN|HW_OWNER;
1255 le->ctrl = 0;
1256 } else
1257 le->opcode |= OP_VLAN;
1258 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1259 ctrl |= INS_VLAN;
1260 }
1261#endif
1262
1263 /* Handle TCP checksum offload */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001264 if (skb->ip_summed == CHECKSUM_HW) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001265 u16 hdr = skb->h.raw - skb->data;
1266 u16 offset = hdr + skb->csum;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001267
1268 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1269 if (skb->nh.iph->protocol == IPPROTO_UDP)
1270 ctrl |= UDPTCP;
1271
1272 le = get_tx_le(sky2);
1273 le->tx.csum.start = cpu_to_le16(hdr);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001274 le->tx.csum.offset = cpu_to_le16(offset);
1275 le->length = 0; /* initial checksum value */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001276 le->ctrl = 1; /* one packet */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001277 le->opcode = OP_TCPLISW | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001278 }
1279
1280 le = get_tx_le(sky2);
1281 le->tx.addr = cpu_to_le32((u32) mapping);
1282 le->length = cpu_to_le16(len);
1283 le->ctrl = ctrl;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001284 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001285
Stephen Hemminger793b8832005-09-14 16:06:14 -07001286 /* Record the transmit mapping info */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001287 re->skb = skb;
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001288 pci_unmap_addr_set(re, mapaddr, mapping);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001289
1290 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1291 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001292 struct tx_ring_info *fre;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001293
1294 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1295 frag->size, PCI_DMA_TODEVICE);
Stephen Hemmingera0361192006-01-17 13:43:16 -08001296 addr64 = high32(mapping);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001297 if (addr64 != sky2->tx_addr64) {
1298 le = get_tx_le(sky2);
1299 le->tx.addr = cpu_to_le32(addr64);
1300 le->ctrl = 0;
1301 le->opcode = OP_ADDR64 | HW_OWNER;
1302 sky2->tx_addr64 = addr64;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001303 }
1304
1305 le = get_tx_le(sky2);
1306 le->tx.addr = cpu_to_le32((u32) mapping);
1307 le->length = cpu_to_le16(frag->size);
1308 le->ctrl = ctrl;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001309 le->opcode = OP_BUFFER | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001310
Stephen Hemminger793b8832005-09-14 16:06:14 -07001311 fre = sky2->tx_ring
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001312 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001313 pci_unmap_addr_set(fre, mapaddr, mapping);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001314 }
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001315
Stephen Hemminger793b8832005-09-14 16:06:14 -07001316 re->idx = sky2->tx_prod;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001317 le->ctrl |= EOP;
1318
Stephen Hemmingerb19666d2006-03-07 11:06:36 -08001319 avail = tx_avail(sky2);
1320 if (mss != 0 || avail < TX_MIN_PENDING) {
1321 le->ctrl |= FRC_STAT;
1322 if (avail <= MAX_SKB_TX_LE)
1323 netif_stop_queue(dev);
1324 }
1325
Stephen Hemminger290d4de2006-03-20 15:48:15 -08001326 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001327
Stephen Hemminger793b8832005-09-14 16:06:14 -07001328out_unlock:
Stephen Hemmingerf2e46562005-12-09 11:34:58 -08001329 spin_unlock(&sky2->tx_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001330
1331 dev->trans_start = jiffies;
1332 return NETDEV_TX_OK;
1333}
1334
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001335/*
Stephen Hemminger793b8832005-09-14 16:06:14 -07001336 * Free ring elements from starting at tx_cons until "done"
1337 *
1338 * NB: the hardware will tell us about partial completion of multi-part
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001339 * buffers; these are deferred until completion.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001340 */
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001341static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001342{
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001343 struct net_device *dev = sky2->netdev;
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001344 struct pci_dev *pdev = sky2->hw->pdev;
1345 u16 nxt, put;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001346 unsigned i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001347
Stephen Hemminger0e3ff6a2005-12-09 11:35:02 -08001348 BUG_ON(done >= TX_RING_SIZE);
shemminger@osdl.org22247952005-11-30 11:45:19 -08001349
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001350 if (unlikely(netif_msg_tx_done(sky2)))
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001351 printk(KERN_DEBUG "%s: tx done, up to %u\n",
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001352 dev->name, done);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001353
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001354 for (put = sky2->tx_cons; put != done; put = nxt) {
1355 struct tx_ring_info *re = sky2->tx_ring + put;
1356 struct sk_buff *skb = re->skb;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001357
Stephen Hemmingerd89e1342006-03-20 15:48:20 -08001358 nxt = re->idx;
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001359 BUG_ON(nxt >= TX_RING_SIZE);
Stephen Hemmingerd70cd512005-12-09 11:35:09 -08001360 prefetch(sky2->tx_ring + nxt);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001361
Stephen Hemminger793b8832005-09-14 16:06:14 -07001362 /* Check for partial status */
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001363 if (tx_dist(put, done) < tx_dist(put, nxt))
1364 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001365
Stephen Hemminger793b8832005-09-14 16:06:14 -07001366 skb = re->skb;
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001367 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
Stephen Hemminger734d1862005-12-09 11:35:00 -08001368 skb_headlen(skb), PCI_DMA_TODEVICE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001369
Stephen Hemminger793b8832005-09-14 16:06:14 -07001370 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001371 struct tx_ring_info *fre;
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001372 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001373 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
Stephen Hemmingerd89e1342006-03-20 15:48:20 -08001374 skb_shinfo(skb)->frags[i].size,
Stephen Hemminger734d1862005-12-09 11:35:00 -08001375 PCI_DMA_TODEVICE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001376 }
1377
Stephen Hemminger15240072006-03-23 08:51:38 -08001378 dev_kfree_skb(skb);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001379 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001380
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001381 sky2->tx_cons = put;
Stephen Hemminger8f246642006-03-20 15:48:21 -08001382 if (tx_avail(sky2) > MAX_SKB_TX_LE)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001383 netif_wake_queue(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001384}
1385
1386/* Cleanup all untransmitted buffers, assume transmitter not running */
Stephen Hemminger13b97b72005-12-09 11:35:03 -08001387static void sky2_tx_clean(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001388{
Stephen Hemminger302d1252006-01-17 13:43:20 -08001389 spin_lock_bh(&sky2->tx_lock);
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001390 sky2_tx_complete(sky2, sky2->tx_prod);
Stephen Hemminger302d1252006-01-17 13:43:20 -08001391 spin_unlock_bh(&sky2->tx_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001392}
1393
1394/* Network shutdown */
1395static int sky2_down(struct net_device *dev)
1396{
1397 struct sky2_port *sky2 = netdev_priv(dev);
1398 struct sky2_hw *hw = sky2->hw;
1399 unsigned port = sky2->port;
1400 u16 ctrl;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001401 u32 imask;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001402
Stephen Hemminger1b537562005-12-20 15:08:07 -08001403 /* Never really got started! */
1404 if (!sky2->tx_le)
1405 return 0;
1406
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001407 if (netif_msg_ifdown(sky2))
1408 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1409
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001410 /* Stop more packets from being queued */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001411 netif_stop_queue(dev);
1412
Stephen Hemminger793b8832005-09-14 16:06:14 -07001413 sky2_phy_reset(hw, port);
1414
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001415 /* Stop transmitter */
1416 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1417 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1418
1419 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
Stephen Hemminger793b8832005-09-14 16:06:14 -07001420 RB_RST_SET | RB_DIS_OP_MD);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001421
1422 ctrl = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001423 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001424 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1425
1426 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1427
1428 /* Workaround shared GMAC reset */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001429 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1430 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001431 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1432
1433 /* Disable Force Sync bit and Enable Alloc bit */
1434 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1435 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1436
1437 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1438 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1439 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1440
1441 /* Reset the PCI FIFO of the async Tx queue */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001442 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1443 BMU_RST_SET | BMU_FIFO_RST);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001444
1445 /* Reset the Tx prefetch units */
1446 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1447 PREF_UNIT_RST_SET);
1448
1449 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1450
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001451 sky2_rx_stop(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001452
1453 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1454 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1455
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001456 /* Disable port IRQ */
1457 imask = sky2_read32(hw, B0_IMSK);
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -07001458 imask &= ~portirq_msk[port];
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001459 sky2_write32(hw, B0_IMSK, imask);
1460
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001461 /* turn off LED's */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001462 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1463
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001464 synchronize_irq(hw->pdev->irq);
1465
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001466 sky2_tx_clean(sky2);
1467 sky2_rx_clean(sky2);
1468
1469 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1470 sky2->rx_le, sky2->rx_le_map);
1471 kfree(sky2->rx_ring);
1472
1473 pci_free_consistent(hw->pdev,
1474 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1475 sky2->tx_le, sky2->tx_le_map);
1476 kfree(sky2->tx_ring);
1477
Stephen Hemminger1b537562005-12-20 15:08:07 -08001478 sky2->tx_le = NULL;
1479 sky2->rx_le = NULL;
1480
1481 sky2->rx_ring = NULL;
1482 sky2->tx_ring = NULL;
1483
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001484 return 0;
1485}
1486
1487static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1488{
Stephen Hemminger793b8832005-09-14 16:06:14 -07001489 if (!hw->copper)
1490 return SPEED_1000;
1491
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001492 if (hw->chip_id == CHIP_ID_YUKON_FE)
1493 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1494
1495 switch (aux & PHY_M_PS_SPEED_MSK) {
1496 case PHY_M_PS_SPEED_1000:
1497 return SPEED_1000;
1498 case PHY_M_PS_SPEED_100:
1499 return SPEED_100;
1500 default:
1501 return SPEED_10;
1502 }
1503}
1504
1505static void sky2_link_up(struct sky2_port *sky2)
1506{
1507 struct sky2_hw *hw = sky2->hw;
1508 unsigned port = sky2->port;
1509 u16 reg;
1510
1511 /* Enable Transmit FIFO Underrun */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001512 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001513
1514 reg = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -08001515 if (sky2->autoneg == AUTONEG_DISABLE) {
1516 reg |= GM_GPCR_AU_ALL_DIS;
1517
1518 /* Is write/read necessary? Copied from sky2_mac_init */
1519 gma_write16(hw, port, GM_GP_CTRL, reg);
1520 gma_read16(hw, port, GM_GP_CTRL);
1521
1522 switch (sky2->speed) {
1523 case SPEED_1000:
1524 reg &= ~GM_GPCR_SPEED_100;
1525 reg |= GM_GPCR_SPEED_1000;
1526 break;
1527 case SPEED_100:
1528 reg &= ~GM_GPCR_SPEED_1000;
1529 reg |= GM_GPCR_SPEED_100;
1530 break;
1531 case SPEED_10:
1532 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1533 break;
1534 }
1535 } else
1536 reg &= ~GM_GPCR_AU_ALL_DIS;
1537
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001538 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1539 reg |= GM_GPCR_DUP_FULL;
1540
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001541 /* enable Rx/Tx */
1542 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1543 gma_write16(hw, port, GM_GP_CTRL, reg);
1544 gma_read16(hw, port, GM_GP_CTRL);
1545
1546 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1547
1548 netif_carrier_on(sky2->netdev);
1549 netif_wake_queue(sky2->netdev);
1550
1551 /* Turn on link LED */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001552 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001553 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1554
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001555 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001556 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001557 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1558
1559 switch(sky2->speed) {
1560 case SPEED_10:
1561 led |= PHY_M_LEDC_INIT_CTRL(7);
1562 break;
1563
1564 case SPEED_100:
1565 led |= PHY_M_LEDC_STA1_CTRL(7);
1566 break;
1567
1568 case SPEED_1000:
1569 led |= PHY_M_LEDC_STA0_CTRL(7);
1570 break;
1571 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001572
1573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001574 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1576 }
1577
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001578 if (netif_msg_link(sky2))
1579 printk(KERN_INFO PFX
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001580 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001581 sky2->netdev->name, sky2->speed,
1582 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1583 (sky2->tx_pause && sky2->rx_pause) ? "both" :
Stephen Hemminger793b8832005-09-14 16:06:14 -07001584 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001585}
1586
1587static void sky2_link_down(struct sky2_port *sky2)
1588{
1589 struct sky2_hw *hw = sky2->hw;
1590 unsigned port = sky2->port;
1591 u16 reg;
1592
1593 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1594
1595 reg = gma_read16(hw, port, GM_GP_CTRL);
1596 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1597 gma_write16(hw, port, GM_GP_CTRL, reg);
1598 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1599
1600 if (sky2->rx_pause && !sky2->tx_pause) {
1601 /* restore Asymmetric Pause bit */
1602 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
Stephen Hemminger793b8832005-09-14 16:06:14 -07001603 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1604 | PHY_M_AN_ASP);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001605 }
1606
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001607 netif_carrier_off(sky2->netdev);
1608 netif_stop_queue(sky2->netdev);
1609
1610 /* Turn on link LED */
1611 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1612
1613 if (netif_msg_link(sky2))
1614 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1615 sky2_phy_init(hw, port);
1616}
1617
Stephen Hemminger793b8832005-09-14 16:06:14 -07001618static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1619{
1620 struct sky2_hw *hw = sky2->hw;
1621 unsigned port = sky2->port;
1622 u16 lpa;
1623
1624 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1625
1626 if (lpa & PHY_M_AN_RF) {
1627 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1628 return -1;
1629 }
1630
1631 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1632 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1633 printk(KERN_ERR PFX "%s: master/slave fault",
1634 sky2->netdev->name);
1635 return -1;
1636 }
1637
1638 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1639 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1640 sky2->netdev->name);
1641 return -1;
1642 }
1643
1644 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1645
1646 sky2->speed = sky2_phy_speed(hw, aux);
1647
1648 /* Pause bits are offset (9..8) */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001649 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001650 aux >>= 6;
1651
1652 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1653 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1654
1655 if ((sky2->tx_pause || sky2->rx_pause)
1656 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1657 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1658 else
1659 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1660
1661 return 0;
1662}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001663
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001664/* Interrupt from PHY */
1665static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001666{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001667 struct net_device *dev = hw->dev[port];
1668 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001669 u16 istatus, phystat;
1670
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001671 spin_lock(&sky2->phy_lock);
1672 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1673 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1674
1675 if (!netif_running(dev))
1676 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001677
1678 if (netif_msg_intr(sky2))
1679 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1680 sky2->netdev->name, istatus, phystat);
1681
1682 if (istatus & PHY_M_IS_AN_COMPL) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001683 if (sky2_autoneg_done(sky2, phystat) == 0)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001684 sky2_link_up(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001685 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001686 }
1687
Stephen Hemminger793b8832005-09-14 16:06:14 -07001688 if (istatus & PHY_M_IS_LSP_CHANGE)
1689 sky2->speed = sky2_phy_speed(hw, phystat);
1690
1691 if (istatus & PHY_M_IS_DUP_CHANGE)
1692 sky2->duplex =
1693 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1694
1695 if (istatus & PHY_M_IS_LST_CHANGE) {
1696 if (phystat & PHY_M_PS_LINK_UP)
1697 sky2_link_up(sky2);
1698 else
1699 sky2_link_down(sky2);
1700 }
1701out:
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001702 spin_unlock(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001703}
1704
Stephen Hemminger302d1252006-01-17 13:43:20 -08001705
1706/* Transmit timeout is only called if we are running, carries is up
1707 * and tx queue is full (stopped).
1708 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001709static void sky2_tx_timeout(struct net_device *dev)
1710{
1711 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger8cc048e2005-12-09 11:35:07 -08001712 struct sky2_hw *hw = sky2->hw;
1713 unsigned txq = txqaddr[sky2->port];
Stephen Hemminger8f246642006-03-20 15:48:21 -08001714 u16 report, done;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001715
1716 if (netif_msg_timer(sky2))
1717 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1718
Stephen Hemminger8f246642006-03-20 15:48:21 -08001719 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1720 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001721
Stephen Hemminger8f246642006-03-20 15:48:21 -08001722 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1723 dev->name,
1724 sky2->tx_cons, sky2->tx_prod, report, done);
Stephen Hemminger8cc048e2005-12-09 11:35:07 -08001725
Stephen Hemminger8f246642006-03-20 15:48:21 -08001726 if (report != done) {
1727 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1728
1729 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1730 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1731 } else if (report != sky2->tx_cons) {
1732 printk(KERN_INFO PFX "status report lost?\n");
1733
1734 spin_lock_bh(&sky2->tx_lock);
1735 sky2_tx_complete(sky2, report);
1736 spin_unlock_bh(&sky2->tx_lock);
1737 } else {
1738 printk(KERN_INFO PFX "hardware hung? flushing\n");
1739
1740 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1741 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1742
1743 sky2_tx_clean(sky2);
1744
1745 sky2_qset(hw, txq);
1746 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1747 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001748}
1749
Stephen Hemminger734d1862005-12-09 11:35:00 -08001750
Stephen Hemminger70f1be42006-03-07 11:06:37 -08001751/* Want receive buffer size to be multiple of 64 bits
1752 * and incl room for vlan and truncation
1753 */
Stephen Hemminger734d1862005-12-09 11:35:00 -08001754static inline unsigned sky2_buf_size(int mtu)
1755{
Stephen Hemminger4a15d562006-04-25 10:58:52 -07001756 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
Stephen Hemminger734d1862005-12-09 11:35:00 -08001757}
1758
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001759static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1760{
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001761 struct sky2_port *sky2 = netdev_priv(dev);
1762 struct sky2_hw *hw = sky2->hw;
1763 int err;
1764 u16 ctl, mode;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001765 u32 imask;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001766
1767 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1768 return -EINVAL;
1769
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001770 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1771 return -EINVAL;
1772
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001773 if (!netif_running(dev)) {
1774 dev->mtu = new_mtu;
1775 return 0;
1776 }
1777
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001778 imask = sky2_read32(hw, B0_IMSK);
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001779 sky2_write32(hw, B0_IMSK, 0);
1780
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001781 dev->trans_start = jiffies; /* prevent tx timeout */
1782 netif_stop_queue(dev);
1783 netif_poll_disable(hw->dev[0]);
1784
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001785 synchronize_irq(hw->pdev->irq);
1786
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001787 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1788 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1789 sky2_rx_stop(sky2);
1790 sky2_rx_clean(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001791
1792 dev->mtu = new_mtu;
Stephen Hemminger734d1862005-12-09 11:35:00 -08001793 sky2->rx_bufsize = sky2_buf_size(new_mtu);
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001794 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1795 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001796
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001797 if (dev->mtu > ETH_DATA_LEN)
1798 mode |= GM_SMOD_JUMBO_ENA;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001799
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001800 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1801
1802 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1803
1804 err = sky2_rx_start(sky2);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001805 sky2_write32(hw, B0_IMSK, imask);
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001806
Stephen Hemminger1b537562005-12-20 15:08:07 -08001807 if (err)
1808 dev_close(dev);
1809 else {
1810 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1811
1812 netif_poll_enable(hw->dev[0]);
1813 netif_wake_queue(dev);
1814 }
1815
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001816 return err;
1817}
1818
1819/*
1820 * Receive one packet.
1821 * For small packets or errors, just reuse existing skb.
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001822 * For larger packets, get new buffer.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001823 */
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001824static struct sk_buff *sky2_receive(struct sky2_port *sky2,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001825 u16 length, u32 status)
1826{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001827 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001828 struct sk_buff *skb = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001829
1830 if (unlikely(netif_msg_rx_status(sky2)))
1831 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001832 sky2->netdev->name, sky2->rx_next, status, length);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001833
Stephen Hemminger793b8832005-09-14 16:06:14 -07001834 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
Stephen Hemmingerd70cd512005-12-09 11:35:09 -08001835 prefetch(sky2->rx_ring + sky2->rx_next);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001836
shemminger@osdl.org42eeea02005-11-30 11:45:13 -08001837 if (status & GMR_FS_ANY_ERR)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001838 goto error;
1839
shemminger@osdl.org42eeea02005-11-30 11:45:13 -08001840 if (!(status & GMR_FS_RX_OK))
1841 goto resubmit;
1842
Stephen Hemminger70f1be42006-03-07 11:06:37 -08001843 if (length > sky2->netdev->mtu + ETH_HLEN)
Stephen Hemminger6e15b712005-12-20 15:08:09 -08001844 goto oversize;
1845
Stephen Hemmingerbdb5c582005-12-09 11:34:55 -08001846 if (length < copybreak) {
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001847 skb = alloc_skb(length + 2, GFP_ATOMIC);
1848 if (!skb)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001849 goto resubmit;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001850
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001851 skb_reserve(skb, 2);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001852 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1853 length, PCI_DMA_FROMDEVICE);
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001854 memcpy(skb->data, re->skb->data, length);
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001855 skb->ip_summed = re->skb->ip_summed;
1856 skb->csum = re->skb->csum;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001857 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1858 length, PCI_DMA_FROMDEVICE);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001859 } else {
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001860 struct sk_buff *nskb;
1861
Stephen Hemminger82788c72006-01-17 13:43:10 -08001862 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001863 if (!nskb)
1864 goto resubmit;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001865
Stephen Hemminger793b8832005-09-14 16:06:14 -07001866 skb = re->skb;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001867 re->skb = nskb;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001868 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
Stephen Hemminger734d1862005-12-09 11:35:00 -08001869 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001870 prefetch(skb->data);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001871
Stephen Hemminger793b8832005-09-14 16:06:14 -07001872 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
Stephen Hemminger734d1862005-12-09 11:35:00 -08001873 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001874 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001875
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001876 skb_put(skb, length);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001877resubmit:
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001878 re->skb->ip_summed = CHECKSUM_NONE;
Stephen Hemminger734d1862005-12-09 11:35:00 -08001879 sky2_rx_add(sky2, re->mapaddr);
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001880
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07001881 /* Tell receiver about new buffers. */
Stephen Hemminger290d4de2006-03-20 15:48:15 -08001882 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07001883
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001884 return skb;
1885
Stephen Hemminger6e15b712005-12-20 15:08:09 -08001886oversize:
1887 ++sky2->net_stats.rx_over_errors;
1888 goto resubmit;
1889
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001890error:
Stephen Hemminger6e15b712005-12-20 15:08:09 -08001891 ++sky2->net_stats.rx_errors;
1892
Stephen Hemminger3be92a72006-01-17 13:43:17 -08001893 if (netif_msg_rx_err(sky2) && net_ratelimit())
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001894 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1895 sky2->netdev->name, status, length);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001896
1897 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001898 sky2->net_stats.rx_length_errors++;
1899 if (status & GMR_FS_FRAGMENT)
1900 sky2->net_stats.rx_frame_errors++;
1901 if (status & GMR_FS_CRC_ERR)
1902 sky2->net_stats.rx_crc_errors++;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001903 if (status & GMR_FS_RX_FF_OV)
1904 sky2->net_stats.rx_fifo_errors++;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001905
Stephen Hemminger793b8832005-09-14 16:06:14 -07001906 goto resubmit;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001907}
1908
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001909/* Transmit complete */
1910static inline void sky2_tx_done(struct net_device *dev, u16 last)
Stephen Hemminger13b97b72005-12-09 11:35:03 -08001911{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001912 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger302d1252006-01-17 13:43:20 -08001913
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001914 if (netif_running(dev)) {
1915 spin_lock(&sky2->tx_lock);
1916 sky2_tx_complete(sky2, last);
1917 spin_unlock(&sky2->tx_lock);
shemminger@osdl.org22247952005-11-30 11:45:19 -08001918 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001919}
1920
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001921/* Process status response ring */
1922static int sky2_status_intr(struct sky2_hw *hw, int to_do)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001923{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001924 int work_done = 0;
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001925 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001926
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001927 rmb();
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07001928
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001929 while (hw->st_idx != hwidx) {
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08001930 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1931 struct net_device *dev;
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001932 struct sky2_port *sky2;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001933 struct sk_buff *skb;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001934 u32 status;
1935 u16 length;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001936
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001937 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07001938
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001939 BUG_ON(le->link >= 2);
1940 dev = hw->dev[le->link];
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08001941
1942 sky2 = netdev_priv(dev);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001943 length = le->length;
1944 status = le->status;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001945
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001946 switch (le->opcode & ~HW_OWNER) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001947 case OP_RXSTAT:
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001948 skb = sky2_receive(sky2, length, status);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001949 if (!skb)
1950 break;
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08001951
1952 skb->dev = dev;
1953 skb->protocol = eth_type_trans(skb, dev);
1954 dev->last_rx = jiffies;
1955
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001956#ifdef SKY2_VLAN_TAG_USED
1957 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1958 vlan_hwaccel_receive_skb(skb,
1959 sky2->vlgrp,
1960 be16_to_cpu(sky2->rx_tag));
1961 } else
1962#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001963 netif_receive_skb(skb);
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08001964
1965 if (++work_done >= to_do)
1966 goto exit_loop;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001967 break;
1968
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001969#ifdef SKY2_VLAN_TAG_USED
1970 case OP_RXVLAN:
1971 sky2->rx_tag = length;
1972 break;
1973
1974 case OP_RXCHKSVLAN:
1975 sky2->rx_tag = length;
1976 /* fall through */
1977#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001978 case OP_RXCHKS:
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001979 skb = sky2->rx_ring[sky2->rx_next].skb;
1980 skb->ip_summed = CHECKSUM_HW;
1981 skb->csum = le16_to_cpu(status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001982 break;
1983
1984 case OP_TXINDEXLE:
Stephen Hemminger13b97b72005-12-09 11:35:03 -08001985 /* TX index reports status for both ports */
Stephen Hemmingerf55925d2006-05-08 15:11:28 -07001986 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1987 sky2_tx_done(hw->dev[0], status & 0xfff);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001988 if (hw->dev[1])
1989 sky2_tx_done(hw->dev[1],
1990 ((status >> 24) & 0xff)
1991 | (u16)(length & 0xf) << 8);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001992 break;
1993
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001994 default:
1995 if (net_ratelimit())
Stephen Hemminger793b8832005-09-14 16:06:14 -07001996 printk(KERN_WARNING PFX
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001997 "unknown status opcode 0x%x\n", le->opcode);
1998 goto exit_loop;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001999 }
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002000 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002001
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002002exit_loop:
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002003 return work_done;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002004}
2005
2006static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2007{
2008 struct net_device *dev = hw->dev[port];
2009
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002010 if (net_ratelimit())
2011 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2012 dev->name, status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002013
2014 if (status & Y2_IS_PAR_RD1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002015 if (net_ratelimit())
2016 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2017 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002018 /* Clear IRQ */
2019 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2020 }
2021
2022 if (status & Y2_IS_PAR_WR1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002023 if (net_ratelimit())
2024 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2025 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002026
2027 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2028 }
2029
2030 if (status & Y2_IS_PAR_MAC1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002031 if (net_ratelimit())
2032 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002033 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2034 }
2035
2036 if (status & Y2_IS_PAR_RX1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002037 if (net_ratelimit())
2038 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002039 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2040 }
2041
2042 if (status & Y2_IS_TCP_TXA1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002043 if (net_ratelimit())
2044 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2045 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002046 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2047 }
2048}
2049
2050static void sky2_hw_intr(struct sky2_hw *hw)
2051{
2052 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2053
Stephen Hemminger793b8832005-09-14 16:06:14 -07002054 if (status & Y2_IS_TIST_OV)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002055 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002056
2057 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002058 u16 pci_err;
2059
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002060 pci_err = sky2_pci_read16(hw, PCI_STATUS);
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002061 if (net_ratelimit())
2062 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2063 pci_name(hw->pdev), pci_err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002064
2065 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002066 sky2_pci_write16(hw, PCI_STATUS,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002067 pci_err | PCI_STATUS_ERROR_BITS);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002068 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2069 }
2070
2071 if (status & Y2_IS_PCI_EXP) {
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07002072 /* PCI-Express uncorrectable Error occurred */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002073 u32 pex_err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002074
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002075 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002076
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002077 if (net_ratelimit())
2078 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2079 pci_name(hw->pdev), pex_err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002080
2081 /* clear the interrupt */
2082 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002083 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002084 0xffffffffUL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002085 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2086
2087 if (pex_err & PEX_FATAL_ERRORS) {
2088 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2089 hwmsk &= ~Y2_IS_PCI_EXP;
2090 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2091 }
2092 }
2093
2094 if (status & Y2_HWE_L1_MASK)
2095 sky2_hw_error(hw, 0, status);
2096 status >>= 8;
2097 if (status & Y2_HWE_L1_MASK)
2098 sky2_hw_error(hw, 1, status);
2099}
2100
2101static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2102{
2103 struct net_device *dev = hw->dev[port];
2104 struct sky2_port *sky2 = netdev_priv(dev);
2105 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2106
2107 if (netif_msg_intr(sky2))
2108 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2109 dev->name, status);
2110
2111 if (status & GM_IS_RX_FF_OR) {
2112 ++sky2->net_stats.rx_fifo_errors;
2113 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2114 }
2115
2116 if (status & GM_IS_TX_FF_UR) {
2117 ++sky2->net_stats.tx_fifo_errors;
2118 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2119 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002120}
2121
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002122/* This should never happen it is a fatal situation */
2123static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2124 const char *rxtx, u32 mask)
2125{
2126 struct net_device *dev = hw->dev[port];
2127 struct sky2_port *sky2 = netdev_priv(dev);
2128 u32 imask;
2129
2130 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2131 dev ? dev->name : "<not registered>", rxtx);
2132
2133 imask = sky2_read32(hw, B0_IMSK);
2134 imask &= ~mask;
2135 sky2_write32(hw, B0_IMSK, imask);
2136
2137 if (dev) {
2138 spin_lock(&sky2->phy_lock);
2139 sky2_link_down(sky2);
2140 spin_unlock(&sky2->phy_lock);
2141 }
2142}
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002143
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002144/* If idle then force a fake soft NAPI poll once a second
2145 * to work around cases where sharing an edge triggered interrupt.
2146 */
2147static void sky2_idle(unsigned long arg)
2148{
Stephen Hemminger01bd7562006-05-08 15:11:30 -07002149 struct sky2_hw *hw = (struct sky2_hw *) arg;
2150 struct net_device *dev = hw->dev[0];
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002151
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002152 if (__netif_rx_schedule_prep(dev))
2153 __netif_rx_schedule(dev);
Stephen Hemminger01bd7562006-05-08 15:11:30 -07002154
2155 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002156}
2157
2158
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002159static int sky2_poll(struct net_device *dev0, int *budget)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002160{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002161 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2162 int work_limit = min(dev0->quota, *budget);
2163 int work_done = 0;
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08002164 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002165
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002166 if (status & Y2_IS_HW_ERR)
2167 sky2_hw_intr(hw);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002168
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002169 if (status & Y2_IS_IRQ_PHY1)
2170 sky2_phy_intr(hw, 0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002171
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002172 if (status & Y2_IS_IRQ_PHY2)
2173 sky2_phy_intr(hw, 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002174
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002175 if (status & Y2_IS_IRQ_MAC1)
2176 sky2_mac_intr(hw, 0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002177
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002178 if (status & Y2_IS_IRQ_MAC2)
2179 sky2_mac_intr(hw, 1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002180
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002181 if (status & Y2_IS_CHK_RX1)
2182 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002183
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002184 if (status & Y2_IS_CHK_RX2)
2185 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002186
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002187 if (status & Y2_IS_CHK_TXA1)
2188 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002189
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002190 if (status & Y2_IS_CHK_TXA2)
2191 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002192
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002193 if (status & Y2_IS_STAT_BMU)
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002194 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002195
2196 work_done = sky2_status_intr(hw, work_limit);
2197 *budget -= work_done;
2198 dev0->quota -= work_done;
2199
2200 if (work_done >= work_limit)
2201 return 1;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002202
Stephen Hemmingerd3240312006-05-08 15:11:26 -07002203 netif_rx_complete(dev0);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002204
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08002205 status = sky2_read32(hw, B0_Y2_SP_LISR);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002206 return 0;
2207}
2208
2209static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2210{
2211 struct sky2_hw *hw = dev_id;
2212 struct net_device *dev0 = hw->dev[0];
2213 u32 status;
2214
2215 /* Reading this mask interrupts as side effect */
2216 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2217 if (status == 0 || status == ~0)
2218 return IRQ_NONE;
2219
2220 prefetch(&hw->st_le[hw->st_idx]);
2221 if (likely(__netif_rx_schedule_prep(dev0)))
2222 __netif_rx_schedule(dev0);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002223
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002224 return IRQ_HANDLED;
2225}
2226
2227#ifdef CONFIG_NET_POLL_CONTROLLER
2228static void sky2_netpoll(struct net_device *dev)
2229{
2230 struct sky2_port *sky2 = netdev_priv(dev);
2231
Stephen Hemminger793b8832005-09-14 16:06:14 -07002232 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002233}
2234#endif
2235
2236/* Chip internal frequency for clock calculations */
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002237static inline u32 sky2_mhz(const struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002238{
Stephen Hemminger793b8832005-09-14 16:06:14 -07002239 switch (hw->chip_id) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002240 case CHIP_ID_YUKON_EC:
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08002241 case CHIP_ID_YUKON_EC_U:
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002242 return 125; /* 125 Mhz */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002243 case CHIP_ID_YUKON_FE:
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002244 return 100; /* 100 Mhz */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002245 default: /* YUKON_XL */
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002246 return 156; /* 156 Mhz */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002247 }
2248}
2249
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002250static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2251{
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002252 return sky2_mhz(hw) * us;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002253}
2254
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002255static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2256{
2257 return clk / sky2_mhz(hw);
2258}
2259
2260
Stephen Hemminger98712e52006-04-25 10:58:53 -07002261static int __devinit sky2_reset(struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002262{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002263 u16 status;
2264 u8 t8, pmd_type;
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002265 int i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002266
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002267 sky2_write8(hw, B0_CTST, CS_RST_CLR);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08002268
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002269 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2270 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2271 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2272 pci_name(hw->pdev), hw->chip_id);
2273 return -EOPNOTSUPP;
2274 }
2275
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002276 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2277
2278 /* This rev is really old, and requires untested workarounds */
2279 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2280 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2281 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2282 hw->chip_id, hw->chip_rev);
2283 return -EOPNOTSUPP;
2284 }
2285
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002286 /* disable ASF */
2287 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2288 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2289 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2290 }
2291
2292 /* do a SW reset */
2293 sky2_write8(hw, B0_CTST, CS_RST_SET);
2294 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2295
2296 /* clear PCI errors, if any */
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002297 status = sky2_pci_read16(hw, PCI_STATUS);
Stephen Hemminger2d42d212006-01-30 11:37:55 -08002298
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002299 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002300 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2301
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002302
2303 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2304
2305 /* clear any PEX errors */
Stephen Hemmingerd89e1342006-03-20 15:48:20 -08002306 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002307 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2308
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002309
2310 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2311 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2312
2313 hw->ports = 1;
2314 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2315 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2316 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2317 ++hw->ports;
2318 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002319
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07002320 sky2_set_power_state(hw, PCI_D0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002321
2322 for (i = 0; i < hw->ports; i++) {
2323 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2324 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2325 }
2326
2327 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2328
Stephen Hemminger793b8832005-09-14 16:06:14 -07002329 /* Clear I2C IRQ noise */
2330 sky2_write32(hw, B2_I2C_IRQ, 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002331
2332 /* turn off hardware timer (unused) */
2333 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2334 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002335
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002336 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2337
Stephen Hemminger69634ee2005-12-09 11:35:06 -08002338 /* Turn off descriptor polling */
2339 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002340
2341 /* Turn off receive timestamp */
2342 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002343 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002344
2345 /* enable the Tx Arbiters */
2346 for (i = 0; i < hw->ports; i++)
2347 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2348
2349 /* Initialize ram interface */
2350 for (i = 0; i < hw->ports; i++) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002351 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002352
2353 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2354 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2355 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2356 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2357 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2358 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2359 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2360 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2361 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2362 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2363 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2364 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2365 }
2366
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002367 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2368
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002369 for (i = 0; i < hw->ports; i++)
2370 sky2_phy_reset(hw, i);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002371
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002372 memset(hw->st_le, 0, STATUS_LE_BYTES);
2373 hw->st_idx = 0;
2374
2375 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2376 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2377
2378 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002379 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002380
2381 /* Set the list last index */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002382 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002383
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002384 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2385 sky2_write8(hw, STAT_FIFO_WM, 16);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002386
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002387 /* set Status-FIFO ISR watermark */
2388 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2389 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2390 else
2391 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002392
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002393 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08002394 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2395 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002396
Stephen Hemminger793b8832005-09-14 16:06:14 -07002397 /* enable status unit */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002398 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2399
2400 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2401 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2402 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2403
2404 return 0;
2405}
2406
Stephen Hemminger28bd1812006-01-17 13:43:19 -08002407static u32 sky2_supported_modes(const struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002408{
2409 u32 modes;
2410 if (hw->copper) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002411 modes = SUPPORTED_10baseT_Half
2412 | SUPPORTED_10baseT_Full
2413 | SUPPORTED_100baseT_Half
2414 | SUPPORTED_100baseT_Full
2415 | SUPPORTED_Autoneg | SUPPORTED_TP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002416
2417 if (hw->chip_id != CHIP_ID_YUKON_FE)
2418 modes |= SUPPORTED_1000baseT_Half
Stephen Hemminger793b8832005-09-14 16:06:14 -07002419 | SUPPORTED_1000baseT_Full;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002420 } else
2421 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
Stephen Hemminger793b8832005-09-14 16:06:14 -07002422 | SUPPORTED_Autoneg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002423 return modes;
2424}
2425
Stephen Hemminger793b8832005-09-14 16:06:14 -07002426static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002427{
2428 struct sky2_port *sky2 = netdev_priv(dev);
2429 struct sky2_hw *hw = sky2->hw;
2430
2431 ecmd->transceiver = XCVR_INTERNAL;
2432 ecmd->supported = sky2_supported_modes(hw);
2433 ecmd->phy_address = PHY_ADDR_MARV;
2434 if (hw->copper) {
2435 ecmd->supported = SUPPORTED_10baseT_Half
Stephen Hemminger793b8832005-09-14 16:06:14 -07002436 | SUPPORTED_10baseT_Full
2437 | SUPPORTED_100baseT_Half
2438 | SUPPORTED_100baseT_Full
2439 | SUPPORTED_1000baseT_Half
2440 | SUPPORTED_1000baseT_Full
2441 | SUPPORTED_Autoneg | SUPPORTED_TP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002442 ecmd->port = PORT_TP;
2443 } else
2444 ecmd->port = PORT_FIBRE;
2445
2446 ecmd->advertising = sky2->advertising;
2447 ecmd->autoneg = sky2->autoneg;
2448 ecmd->speed = sky2->speed;
2449 ecmd->duplex = sky2->duplex;
2450 return 0;
2451}
2452
2453static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2454{
2455 struct sky2_port *sky2 = netdev_priv(dev);
2456 const struct sky2_hw *hw = sky2->hw;
2457 u32 supported = sky2_supported_modes(hw);
2458
2459 if (ecmd->autoneg == AUTONEG_ENABLE) {
2460 ecmd->advertising = supported;
2461 sky2->duplex = -1;
2462 sky2->speed = -1;
2463 } else {
2464 u32 setting;
2465
Stephen Hemminger793b8832005-09-14 16:06:14 -07002466 switch (ecmd->speed) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002467 case SPEED_1000:
2468 if (ecmd->duplex == DUPLEX_FULL)
2469 setting = SUPPORTED_1000baseT_Full;
2470 else if (ecmd->duplex == DUPLEX_HALF)
2471 setting = SUPPORTED_1000baseT_Half;
2472 else
2473 return -EINVAL;
2474 break;
2475 case SPEED_100:
2476 if (ecmd->duplex == DUPLEX_FULL)
2477 setting = SUPPORTED_100baseT_Full;
2478 else if (ecmd->duplex == DUPLEX_HALF)
2479 setting = SUPPORTED_100baseT_Half;
2480 else
2481 return -EINVAL;
2482 break;
2483
2484 case SPEED_10:
2485 if (ecmd->duplex == DUPLEX_FULL)
2486 setting = SUPPORTED_10baseT_Full;
2487 else if (ecmd->duplex == DUPLEX_HALF)
2488 setting = SUPPORTED_10baseT_Half;
2489 else
2490 return -EINVAL;
2491 break;
2492 default:
2493 return -EINVAL;
2494 }
2495
2496 if ((setting & supported) == 0)
2497 return -EINVAL;
2498
2499 sky2->speed = ecmd->speed;
2500 sky2->duplex = ecmd->duplex;
2501 }
2502
2503 sky2->autoneg = ecmd->autoneg;
2504 sky2->advertising = ecmd->advertising;
2505
Stephen Hemminger1b537562005-12-20 15:08:07 -08002506 if (netif_running(dev))
2507 sky2_phy_reinit(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002508
2509 return 0;
2510}
2511
2512static void sky2_get_drvinfo(struct net_device *dev,
2513 struct ethtool_drvinfo *info)
2514{
2515 struct sky2_port *sky2 = netdev_priv(dev);
2516
2517 strcpy(info->driver, DRV_NAME);
2518 strcpy(info->version, DRV_VERSION);
2519 strcpy(info->fw_version, "N/A");
2520 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2521}
2522
2523static const struct sky2_stat {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002524 char name[ETH_GSTRING_LEN];
2525 u16 offset;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002526} sky2_stats[] = {
2527 { "tx_bytes", GM_TXO_OK_HI },
2528 { "rx_bytes", GM_RXO_OK_HI },
2529 { "tx_broadcast", GM_TXF_BC_OK },
2530 { "rx_broadcast", GM_RXF_BC_OK },
2531 { "tx_multicast", GM_TXF_MC_OK },
2532 { "rx_multicast", GM_RXF_MC_OK },
2533 { "tx_unicast", GM_TXF_UC_OK },
2534 { "rx_unicast", GM_RXF_UC_OK },
2535 { "tx_mac_pause", GM_TXF_MPAUSE },
2536 { "rx_mac_pause", GM_RXF_MPAUSE },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002537 { "collisions", GM_TXF_COL },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002538 { "late_collision",GM_TXF_LAT_COL },
2539 { "aborted", GM_TXF_ABO_COL },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002540 { "single_collisions", GM_TXF_SNG_COL },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002541 { "multi_collisions", GM_TXF_MUL_COL },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002542
Stephen Hemmingerd2604542006-03-23 08:51:36 -08002543 { "rx_short", GM_RXF_SHT },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002544 { "rx_runt", GM_RXE_FRAG },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002545 { "rx_64_byte_packets", GM_RXF_64B },
2546 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2547 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2548 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2549 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2550 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2551 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002552 { "rx_too_long", GM_RXF_LNG_ERR },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002553 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2554 { "rx_jabber", GM_RXF_JAB_PKT },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002555 { "rx_fcs_error", GM_RXF_FCS_ERR },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002556
2557 { "tx_64_byte_packets", GM_TXF_64B },
2558 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2559 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2560 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2561 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2562 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2563 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2564 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002565};
2566
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002567static u32 sky2_get_rx_csum(struct net_device *dev)
2568{
2569 struct sky2_port *sky2 = netdev_priv(dev);
2570
2571 return sky2->rx_csum;
2572}
2573
2574static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2575{
2576 struct sky2_port *sky2 = netdev_priv(dev);
2577
2578 sky2->rx_csum = data;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002579
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002580 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2581 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2582
2583 return 0;
2584}
2585
2586static u32 sky2_get_msglevel(struct net_device *netdev)
2587{
2588 struct sky2_port *sky2 = netdev_priv(netdev);
2589 return sky2->msg_enable;
2590}
2591
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002592static int sky2_nway_reset(struct net_device *dev)
2593{
2594 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002595
2596 if (sky2->autoneg != AUTONEG_ENABLE)
2597 return -EINVAL;
2598
Stephen Hemminger1b537562005-12-20 15:08:07 -08002599 sky2_phy_reinit(sky2);
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002600
2601 return 0;
2602}
2603
Stephen Hemminger793b8832005-09-14 16:06:14 -07002604static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002605{
2606 struct sky2_hw *hw = sky2->hw;
2607 unsigned port = sky2->port;
2608 int i;
2609
2610 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
Stephen Hemminger793b8832005-09-14 16:06:14 -07002611 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002612 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
Stephen Hemminger793b8832005-09-14 16:06:14 -07002613 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002614
Stephen Hemminger793b8832005-09-14 16:06:14 -07002615 for (i = 2; i < count; i++)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002616 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2617}
2618
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002619static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2620{
2621 struct sky2_port *sky2 = netdev_priv(netdev);
2622 sky2->msg_enable = value;
2623}
2624
2625static int sky2_get_stats_count(struct net_device *dev)
2626{
2627 return ARRAY_SIZE(sky2_stats);
2628}
2629
2630static void sky2_get_ethtool_stats(struct net_device *dev,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002631 struct ethtool_stats *stats, u64 * data)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002632{
2633 struct sky2_port *sky2 = netdev_priv(dev);
2634
Stephen Hemminger793b8832005-09-14 16:06:14 -07002635 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002636}
2637
Stephen Hemminger793b8832005-09-14 16:06:14 -07002638static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002639{
2640 int i;
2641
2642 switch (stringset) {
2643 case ETH_SS_STATS:
2644 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2645 memcpy(data + i * ETH_GSTRING_LEN,
2646 sky2_stats[i].name, ETH_GSTRING_LEN);
2647 break;
2648 }
2649}
2650
2651/* Use hardware MIB variables for critical path statistics and
2652 * transmit feedback not reported at interrupt.
2653 * Other errors are accounted for in interrupt handler.
2654 */
2655static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2656{
2657 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002658 u64 data[13];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002659
Stephen Hemminger793b8832005-09-14 16:06:14 -07002660 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002661
2662 sky2->net_stats.tx_bytes = data[0];
2663 sky2->net_stats.rx_bytes = data[1];
2664 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2665 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
Stephen Hemminger050ff182006-03-23 08:51:37 -08002666 sky2->net_stats.multicast = data[3] + data[5];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002667 sky2->net_stats.collisions = data[10];
2668 sky2->net_stats.tx_aborted_errors = data[12];
2669
2670 return &sky2->net_stats;
2671}
2672
2673static int sky2_set_mac_address(struct net_device *dev, void *p)
2674{
2675 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002676 struct sky2_hw *hw = sky2->hw;
2677 unsigned port = sky2->port;
2678 const struct sockaddr *addr = p;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002679
2680 if (!is_valid_ether_addr(addr->sa_data))
2681 return -EADDRNOTAVAIL;
2682
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002683 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002684 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002685 dev->dev_addr, ETH_ALEN);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002686 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002687 dev->dev_addr, ETH_ALEN);
Stephen Hemminger1b537562005-12-20 15:08:07 -08002688
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002689 /* virtual address for data */
2690 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2691
2692 /* physical address: used for pause frames */
2693 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
Stephen Hemminger1b537562005-12-20 15:08:07 -08002694
2695 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002696}
2697
2698static void sky2_set_multicast(struct net_device *dev)
2699{
2700 struct sky2_port *sky2 = netdev_priv(dev);
2701 struct sky2_hw *hw = sky2->hw;
2702 unsigned port = sky2->port;
2703 struct dev_mc_list *list = dev->mc_list;
2704 u16 reg;
2705 u8 filter[8];
2706
2707 memset(filter, 0, sizeof(filter));
2708
2709 reg = gma_read16(hw, port, GM_RX_CTRL);
2710 reg |= GM_RXCR_UCF_ENA;
2711
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07002712 if (dev->flags & IFF_PROMISC) /* promiscuous */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002713 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002714 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002715 memset(filter, 0xff, sizeof(filter));
Stephen Hemminger793b8832005-09-14 16:06:14 -07002716 else if (dev->mc_count == 0) /* no multicast */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002717 reg &= ~GM_RXCR_MCF_ENA;
2718 else {
2719 int i;
2720 reg |= GM_RXCR_MCF_ENA;
2721
2722 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2723 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002724 filter[bit / 8] |= 1 << (bit % 8);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002725 }
2726 }
2727
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002728 gma_write16(hw, port, GM_MC_ADDR_H1,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002729 (u16) filter[0] | ((u16) filter[1] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002730 gma_write16(hw, port, GM_MC_ADDR_H2,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002731 (u16) filter[2] | ((u16) filter[3] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002732 gma_write16(hw, port, GM_MC_ADDR_H3,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002733 (u16) filter[4] | ((u16) filter[5] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002734 gma_write16(hw, port, GM_MC_ADDR_H4,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002735 (u16) filter[6] | ((u16) filter[7] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002736
2737 gma_write16(hw, port, GM_RX_CTRL, reg);
2738}
2739
2740/* Can have one global because blinking is controlled by
2741 * ethtool and that is always under RTNL mutex
2742 */
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002743static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002744{
Stephen Hemminger793b8832005-09-14 16:06:14 -07002745 u16 pg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002746
Stephen Hemminger793b8832005-09-14 16:06:14 -07002747 switch (hw->chip_id) {
2748 case CHIP_ID_YUKON_XL:
2749 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2750 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2751 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2752 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2753 PHY_M_LEDC_INIT_CTRL(7) |
2754 PHY_M_LEDC_STA1_CTRL(7) |
2755 PHY_M_LEDC_STA0_CTRL(7))
2756 : 0);
2757
2758 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2759 break;
2760
2761 default:
2762 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2763 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2764 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2765 PHY_M_LED_MO_10(MO_LED_ON) |
2766 PHY_M_LED_MO_100(MO_LED_ON) |
2767 PHY_M_LED_MO_1000(MO_LED_ON) |
2768 PHY_M_LED_MO_RX(MO_LED_ON)
2769 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2770 PHY_M_LED_MO_10(MO_LED_OFF) |
2771 PHY_M_LED_MO_100(MO_LED_OFF) |
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002772 PHY_M_LED_MO_1000(MO_LED_OFF) |
2773 PHY_M_LED_MO_RX(MO_LED_OFF));
2774
Stephen Hemminger793b8832005-09-14 16:06:14 -07002775 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002776}
2777
2778/* blink LED's for finding board */
2779static int sky2_phys_id(struct net_device *dev, u32 data)
2780{
2781 struct sky2_port *sky2 = netdev_priv(dev);
2782 struct sky2_hw *hw = sky2->hw;
2783 unsigned port = sky2->port;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002784 u16 ledctrl, ledover = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002785 long ms;
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002786 int interrupted;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002787 int onoff = 1;
2788
Stephen Hemminger793b8832005-09-14 16:06:14 -07002789 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002790 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2791 else
2792 ms = data * 1000;
2793
2794 /* save initial values */
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002795 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002796 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2797 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2798 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2799 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2800 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2801 } else {
2802 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2803 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2804 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002805
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002806 interrupted = 0;
2807 while (!interrupted && ms > 0) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002808 sky2_led(hw, port, onoff);
2809 onoff = !onoff;
2810
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002811 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002812 interrupted = msleep_interruptible(250);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002813 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002814
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002815 ms -= 250;
2816 }
2817
2818 /* resume regularly scheduled programming */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002819 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2820 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2821 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2822 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2823 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2824 } else {
2825 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2826 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2827 }
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002828 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002829
2830 return 0;
2831}
2832
2833static void sky2_get_pauseparam(struct net_device *dev,
2834 struct ethtool_pauseparam *ecmd)
2835{
2836 struct sky2_port *sky2 = netdev_priv(dev);
2837
2838 ecmd->tx_pause = sky2->tx_pause;
2839 ecmd->rx_pause = sky2->rx_pause;
2840 ecmd->autoneg = sky2->autoneg;
2841}
2842
2843static int sky2_set_pauseparam(struct net_device *dev,
2844 struct ethtool_pauseparam *ecmd)
2845{
2846 struct sky2_port *sky2 = netdev_priv(dev);
2847 int err = 0;
2848
2849 sky2->autoneg = ecmd->autoneg;
2850 sky2->tx_pause = ecmd->tx_pause != 0;
2851 sky2->rx_pause = ecmd->rx_pause != 0;
2852
Stephen Hemminger1b537562005-12-20 15:08:07 -08002853 sky2_phy_reinit(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002854
2855 return err;
2856}
2857
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002858static int sky2_get_coalesce(struct net_device *dev,
2859 struct ethtool_coalesce *ecmd)
2860{
2861 struct sky2_port *sky2 = netdev_priv(dev);
2862 struct sky2_hw *hw = sky2->hw;
2863
2864 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2865 ecmd->tx_coalesce_usecs = 0;
2866 else {
2867 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2868 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2869 }
2870 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2871
2872 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2873 ecmd->rx_coalesce_usecs = 0;
2874 else {
2875 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2876 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2877 }
2878 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2879
2880 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2881 ecmd->rx_coalesce_usecs_irq = 0;
2882 else {
2883 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2884 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2885 }
2886
2887 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2888
2889 return 0;
2890}
2891
2892/* Note: this affect both ports */
2893static int sky2_set_coalesce(struct net_device *dev,
2894 struct ethtool_coalesce *ecmd)
2895{
2896 struct sky2_port *sky2 = netdev_priv(dev);
2897 struct sky2_hw *hw = sky2->hw;
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08002898 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002899
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08002900 if (ecmd->tx_coalesce_usecs > tmax ||
2901 ecmd->rx_coalesce_usecs > tmax ||
2902 ecmd->rx_coalesce_usecs_irq > tmax)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002903 return -EINVAL;
2904
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08002905 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002906 return -EINVAL;
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08002907 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002908 return -EINVAL;
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08002909 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002910 return -EINVAL;
2911
2912 if (ecmd->tx_coalesce_usecs == 0)
2913 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2914 else {
2915 sky2_write32(hw, STAT_TX_TIMER_INI,
2916 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2917 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2918 }
2919 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2920
2921 if (ecmd->rx_coalesce_usecs == 0)
2922 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2923 else {
2924 sky2_write32(hw, STAT_LEV_TIMER_INI,
2925 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2926 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2927 }
2928 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2929
2930 if (ecmd->rx_coalesce_usecs_irq == 0)
2931 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2932 else {
Stephen Hemmingerd28d4872006-01-30 11:37:56 -08002933 sky2_write32(hw, STAT_ISR_TIMER_INI,
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002934 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2935 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2936 }
2937 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2938 return 0;
2939}
2940
Stephen Hemminger793b8832005-09-14 16:06:14 -07002941static void sky2_get_ringparam(struct net_device *dev,
2942 struct ethtool_ringparam *ering)
2943{
2944 struct sky2_port *sky2 = netdev_priv(dev);
2945
2946 ering->rx_max_pending = RX_MAX_PENDING;
2947 ering->rx_mini_max_pending = 0;
2948 ering->rx_jumbo_max_pending = 0;
2949 ering->tx_max_pending = TX_RING_SIZE - 1;
2950
2951 ering->rx_pending = sky2->rx_pending;
2952 ering->rx_mini_pending = 0;
2953 ering->rx_jumbo_pending = 0;
2954 ering->tx_pending = sky2->tx_pending;
2955}
2956
2957static int sky2_set_ringparam(struct net_device *dev,
2958 struct ethtool_ringparam *ering)
2959{
2960 struct sky2_port *sky2 = netdev_priv(dev);
2961 int err = 0;
2962
2963 if (ering->rx_pending > RX_MAX_PENDING ||
2964 ering->rx_pending < 8 ||
2965 ering->tx_pending < MAX_SKB_TX_LE ||
2966 ering->tx_pending > TX_RING_SIZE - 1)
2967 return -EINVAL;
2968
2969 if (netif_running(dev))
2970 sky2_down(dev);
2971
2972 sky2->rx_pending = ering->rx_pending;
2973 sky2->tx_pending = ering->tx_pending;
2974
Stephen Hemminger1b537562005-12-20 15:08:07 -08002975 if (netif_running(dev)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002976 err = sky2_up(dev);
Stephen Hemminger1b537562005-12-20 15:08:07 -08002977 if (err)
2978 dev_close(dev);
Stephen Hemminger6ed995b2005-12-20 15:08:08 -08002979 else
2980 sky2_set_multicast(dev);
Stephen Hemminger1b537562005-12-20 15:08:07 -08002981 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07002982
2983 return err;
2984}
2985
Stephen Hemminger793b8832005-09-14 16:06:14 -07002986static int sky2_get_regs_len(struct net_device *dev)
2987{
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07002988 return 0x4000;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002989}
2990
2991/*
2992 * Returns copy of control register region
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07002993 * Note: access to the RAM address register set will cause timeouts.
Stephen Hemminger793b8832005-09-14 16:06:14 -07002994 */
2995static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2996 void *p)
2997{
2998 const struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002999 const void __iomem *io = sky2->hw->regs;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003000
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003001 BUG_ON(regs->len < B3_RI_WTO_R1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003002 regs->version = 1;
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003003 memset(p, 0, regs->len);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003004
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003005 memcpy_fromio(p, io, B3_RAM_ADDR);
3006
3007 memcpy_fromio(p + B3_RI_WTO_R1,
3008 io + B3_RI_WTO_R1,
3009 regs->len - B3_RI_WTO_R1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003010}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003011
3012static struct ethtool_ops sky2_ethtool_ops = {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003013 .get_settings = sky2_get_settings,
3014 .set_settings = sky2_set_settings,
3015 .get_drvinfo = sky2_get_drvinfo,
3016 .get_msglevel = sky2_get_msglevel,
3017 .set_msglevel = sky2_set_msglevel,
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07003018 .nway_reset = sky2_nway_reset,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003019 .get_regs_len = sky2_get_regs_len,
3020 .get_regs = sky2_get_regs,
3021 .get_link = ethtool_op_get_link,
3022 .get_sg = ethtool_op_get_sg,
3023 .set_sg = ethtool_op_set_sg,
3024 .get_tx_csum = ethtool_op_get_tx_csum,
3025 .set_tx_csum = ethtool_op_set_tx_csum,
3026 .get_tso = ethtool_op_get_tso,
3027 .set_tso = ethtool_op_set_tso,
3028 .get_rx_csum = sky2_get_rx_csum,
3029 .set_rx_csum = sky2_set_rx_csum,
3030 .get_strings = sky2_get_strings,
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003031 .get_coalesce = sky2_get_coalesce,
3032 .set_coalesce = sky2_set_coalesce,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003033 .get_ringparam = sky2_get_ringparam,
3034 .set_ringparam = sky2_set_ringparam,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003035 .get_pauseparam = sky2_get_pauseparam,
3036 .set_pauseparam = sky2_set_pauseparam,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003037 .phys_id = sky2_phys_id,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003038 .get_stats_count = sky2_get_stats_count,
3039 .get_ethtool_stats = sky2_get_ethtool_stats,
Stephen Hemminger2995bfb2005-09-28 10:01:03 -07003040 .get_perm_addr = ethtool_op_get_perm_addr,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003041};
3042
3043/* Initialize network device */
3044static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3045 unsigned port, int highmem)
3046{
3047 struct sky2_port *sky2;
3048 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3049
3050 if (!dev) {
3051 printk(KERN_ERR "sky2 etherdev alloc failed");
3052 return NULL;
3053 }
3054
3055 SET_MODULE_OWNER(dev);
3056 SET_NETDEV_DEV(dev, &hw->pdev->dev);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08003057 dev->irq = hw->pdev->irq;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003058 dev->open = sky2_up;
3059 dev->stop = sky2_down;
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08003060 dev->do_ioctl = sky2_ioctl;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003061 dev->hard_start_xmit = sky2_xmit_frame;
3062 dev->get_stats = sky2_get_stats;
3063 dev->set_multicast_list = sky2_set_multicast;
3064 dev->set_mac_address = sky2_set_mac_address;
3065 dev->change_mtu = sky2_change_mtu;
3066 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3067 dev->tx_timeout = sky2_tx_timeout;
3068 dev->watchdog_timeo = TX_WATCHDOG;
3069 if (port == 0)
3070 dev->poll = sky2_poll;
3071 dev->weight = NAPI_WEIGHT;
3072#ifdef CONFIG_NET_POLL_CONTROLLER
3073 dev->poll_controller = sky2_netpoll;
3074#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003075
3076 sky2 = netdev_priv(dev);
3077 sky2->netdev = dev;
3078 sky2->hw = hw;
3079 sky2->msg_enable = netif_msg_init(debug, default_msg);
3080
3081 spin_lock_init(&sky2->tx_lock);
3082 /* Auto speed and flow control */
3083 sky2->autoneg = AUTONEG_ENABLE;
Stephen Hemminger585b56012005-12-09 11:35:10 -08003084 sky2->tx_pause = 1;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003085 sky2->rx_pause = 1;
3086 sky2->duplex = -1;
3087 sky2->speed = -1;
3088 sky2->advertising = sky2_supported_modes(hw);
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07003089 sky2->rx_csum = 1;
Stephen Hemminger75d070c2005-12-09 11:35:11 -08003090
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003091 spin_lock_init(&sky2->phy_lock);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003092 sky2->tx_pending = TX_DEF_PENDING;
Stephen Hemminger290d4de2006-03-20 15:48:15 -08003093 sky2->rx_pending = RX_DEF_PENDING;
Stephen Hemminger734d1862005-12-09 11:35:00 -08003094 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003095
3096 hw->dev[port] = dev;
3097
3098 sky2->port = port;
3099
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08003100 dev->features |= NETIF_F_LLTX;
3101 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3102 dev->features |= NETIF_F_TSO;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003103 if (highmem)
3104 dev->features |= NETIF_F_HIGHDMA;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003105 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003106
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07003107#ifdef SKY2_VLAN_TAG_USED
3108 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3109 dev->vlan_rx_register = sky2_vlan_rx_register;
3110 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3111#endif
3112
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003113 /* read the mac address */
Stephen Hemminger793b8832005-09-14 16:06:14 -07003114 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
Stephen Hemminger2995bfb2005-09-28 10:01:03 -07003115 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003116
3117 /* device is off until link detection */
3118 netif_carrier_off(dev);
3119 netif_stop_queue(dev);
3120
3121 return dev;
3122}
3123
Stephen Hemminger28bd1812006-01-17 13:43:19 -08003124static void __devinit sky2_show_addr(struct net_device *dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003125{
3126 const struct sky2_port *sky2 = netdev_priv(dev);
3127
3128 if (netif_msg_probe(sky2))
3129 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3130 dev->name,
3131 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3132 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3133}
3134
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003135/* Handle software interrupt used during MSI test */
3136static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3137 struct pt_regs *regs)
3138{
3139 struct sky2_hw *hw = dev_id;
3140 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3141
3142 if (status == 0)
3143 return IRQ_NONE;
3144
3145 if (status & Y2_IS_IRQ_SW) {
3146 hw->msi_detected = 1;
3147 wake_up(&hw->msi_wait);
3148 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3149 }
3150 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3151
3152 return IRQ_HANDLED;
3153}
3154
3155/* Test interrupt path by forcing a a software IRQ */
3156static int __devinit sky2_test_msi(struct sky2_hw *hw)
3157{
3158 struct pci_dev *pdev = hw->pdev;
3159 int err;
3160
3161 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3162
3163 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3164 if (err) {
3165 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3166 pci_name(pdev), pdev->irq);
3167 return err;
3168 }
3169
3170 init_waitqueue_head (&hw->msi_wait);
3171
3172 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3173 wmb();
3174
3175 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3176
3177 if (!hw->msi_detected) {
3178 /* MSI test failed, go back to INTx mode */
3179 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3180 "switching to INTx mode. Please report this failure to "
3181 "the PCI maintainer and include system chipset information.\n",
3182 pci_name(pdev));
3183
3184 err = -EOPNOTSUPP;
3185 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3186 }
3187
3188 sky2_write32(hw, B0_IMSK, 0);
3189
3190 free_irq(pdev->irq, hw);
3191
3192 return err;
3193}
3194
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003195static int __devinit sky2_probe(struct pci_dev *pdev,
3196 const struct pci_device_id *ent)
3197{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003198 struct net_device *dev, *dev1 = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003199 struct sky2_hw *hw;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003200 int err, pm_cap, using_dac = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003201
Stephen Hemminger793b8832005-09-14 16:06:14 -07003202 err = pci_enable_device(pdev);
3203 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003204 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3205 pci_name(pdev));
3206 goto err_out;
3207 }
3208
Stephen Hemminger793b8832005-09-14 16:06:14 -07003209 err = pci_request_regions(pdev, DRV_NAME);
3210 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003211 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3212 pci_name(pdev));
Stephen Hemminger793b8832005-09-14 16:06:14 -07003213 goto err_out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003214 }
3215
3216 pci_set_master(pdev);
3217
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003218 /* Find power-management capability. */
3219 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3220 if (pm_cap == 0) {
3221 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3222 "aborting.\n");
3223 err = -EIO;
3224 goto err_out_free_regions;
3225 }
3226
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003227 if (sizeof(dma_addr_t) > sizeof(u32) &&
3228 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3229 using_dac = 1;
3230 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3231 if (err < 0) {
3232 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3233 "for consistent allocations\n", pci_name(pdev));
3234 goto err_out_free_regions;
3235 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003236
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003237 } else {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003238 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3239 if (err) {
3240 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3241 pci_name(pdev));
3242 goto err_out_free_regions;
3243 }
3244 }
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003245
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003246 err = -ENOMEM;
Stephen Hemminger6aad85d2006-01-17 13:43:18 -08003247 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003248 if (!hw) {
3249 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3250 pci_name(pdev));
3251 goto err_out_free_regions;
3252 }
3253
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003254 hw->pdev = pdev;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003255
3256 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3257 if (!hw->regs) {
3258 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3259 pci_name(pdev));
3260 goto err_out_free_hw;
3261 }
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003262 hw->pm_cap = pm_cap;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003263
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003264#ifdef __BIG_ENDIAN
3265 /* byte swap descriptors in hardware */
3266 {
3267 u32 reg;
3268
3269 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3270 reg |= PCI_REV_DESC;
3271 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3272 }
3273#endif
3274
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003275 /* ring for status responses */
3276 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3277 &hw->st_dma);
3278 if (!hw->st_le)
3279 goto err_out_iounmap;
3280
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003281 err = sky2_reset(hw);
3282 if (err)
Stephen Hemminger793b8832005-09-14 16:06:14 -07003283 goto err_out_iounmap;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003284
shemminger@osdl.org5f4f9dc2005-11-30 11:45:23 -08003285 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3286 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
Stephen Hemminger92f965e2005-12-09 11:34:53 -08003287 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
Stephen Hemminger793b8832005-09-14 16:06:14 -07003288 hw->chip_id, hw->chip_rev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003289
Stephen Hemminger793b8832005-09-14 16:06:14 -07003290 dev = sky2_init_netdev(hw, 0, using_dac);
3291 if (!dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003292 goto err_out_free_pci;
3293
Stephen Hemminger793b8832005-09-14 16:06:14 -07003294 err = register_netdev(dev);
3295 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003296 printk(KERN_ERR PFX "%s: cannot register net device\n",
3297 pci_name(pdev));
3298 goto err_out_free_netdev;
3299 }
3300
3301 sky2_show_addr(dev);
3302
3303 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3304 if (register_netdev(dev1) == 0)
3305 sky2_show_addr(dev1);
3306 else {
3307 /* Failure to register second port need not be fatal */
Stephen Hemminger793b8832005-09-14 16:06:14 -07003308 printk(KERN_WARNING PFX
3309 "register of second port failed\n");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003310 hw->dev[1] = NULL;
3311 free_netdev(dev1);
3312 }
3313 }
3314
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003315 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3316 err = sky2_test_msi(hw);
3317 if (err == -EOPNOTSUPP)
3318 pci_disable_msi(pdev);
3319 else if (err)
3320 goto err_out_unregister;
3321 }
3322
3323 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003324 if (err) {
3325 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3326 pci_name(pdev), pdev->irq);
3327 goto err_out_unregister;
3328 }
3329
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003330 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003331
Stephen Hemminger01bd7562006-05-08 15:11:30 -07003332 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3333 if (idle_timeout > 0)
3334 mod_timer(&hw->idle_timer,
3335 jiffies + msecs_to_jiffies(idle_timeout));
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003336
Stephen Hemminger793b8832005-09-14 16:06:14 -07003337 pci_set_drvdata(pdev, hw);
3338
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003339 return 0;
3340
Stephen Hemminger793b8832005-09-14 16:06:14 -07003341err_out_unregister:
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003342 pci_disable_msi(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003343 if (dev1) {
3344 unregister_netdev(dev1);
3345 free_netdev(dev1);
3346 }
3347 unregister_netdev(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003348err_out_free_netdev:
3349 free_netdev(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003350err_out_free_pci:
Stephen Hemminger793b8832005-09-14 16:06:14 -07003351 sky2_write8(hw, B0_CTST, CS_RST_SET);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003352 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3353err_out_iounmap:
3354 iounmap(hw->regs);
3355err_out_free_hw:
3356 kfree(hw);
3357err_out_free_regions:
3358 pci_release_regions(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003359 pci_disable_device(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003360err_out:
3361 return err;
3362}
3363
3364static void __devexit sky2_remove(struct pci_dev *pdev)
3365{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003366 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003367 struct net_device *dev0, *dev1;
3368
Stephen Hemminger793b8832005-09-14 16:06:14 -07003369 if (!hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003370 return;
3371
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003372 del_timer_sync(&hw->idle_timer);
3373
3374 sky2_write32(hw, B0_IMSK, 0);
Stephen Hemminger72cb8522006-05-08 15:11:32 -07003375 synchronize_irq(hw->pdev->irq);
3376
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003377 dev0 = hw->dev[0];
Stephen Hemminger793b8832005-09-14 16:06:14 -07003378 dev1 = hw->dev[1];
3379 if (dev1)
3380 unregister_netdev(dev1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003381 unregister_netdev(dev0);
3382
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003383 sky2_set_power_state(hw, PCI_D3hot);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003384 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003385 sky2_write8(hw, B0_CTST, CS_RST_SET);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003386 sky2_read8(hw, B0_CTST);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003387
3388 free_irq(pdev->irq, hw);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003389 pci_disable_msi(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003390 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003391 pci_release_regions(pdev);
3392 pci_disable_device(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003393
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003394 if (dev1)
3395 free_netdev(dev1);
3396 free_netdev(dev0);
3397 iounmap(hw->regs);
3398 kfree(hw);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003399
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003400 pci_set_drvdata(pdev, NULL);
3401}
3402
3403#ifdef CONFIG_PM
3404static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3405{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003406 struct sky2_hw *hw = pci_get_drvdata(pdev);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003407 int i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003408
3409 for (i = 0; i < 2; i++) {
3410 struct net_device *dev = hw->dev[i];
3411
3412 if (dev) {
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003413 if (!netif_running(dev))
3414 continue;
3415
3416 sky2_down(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003417 netif_device_detach(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003418 }
3419 }
3420
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003421 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003422}
3423
3424static int sky2_resume(struct pci_dev *pdev)
3425{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003426 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003427 int i, err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003428
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003429 pci_restore_state(pdev);
3430 pci_enable_wake(pdev, PCI_D0, 0);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003431 err = sky2_set_power_state(hw, PCI_D0);
3432 if (err)
3433 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003434
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003435 err = sky2_reset(hw);
3436 if (err)
3437 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003438
3439 for (i = 0; i < 2; i++) {
3440 struct net_device *dev = hw->dev[i];
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003441 if (dev && netif_running(dev)) {
3442 netif_device_attach(dev);
3443 err = sky2_up(dev);
3444 if (err) {
3445 printk(KERN_ERR PFX "%s: could not up: %d\n",
3446 dev->name, err);
3447 dev_close(dev);
3448 break;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003449 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003450 }
3451 }
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003452out:
3453 return err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003454}
3455#endif
3456
3457static struct pci_driver sky2_driver = {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003458 .name = DRV_NAME,
3459 .id_table = sky2_id_table,
3460 .probe = sky2_probe,
3461 .remove = __devexit_p(sky2_remove),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003462#ifdef CONFIG_PM
Stephen Hemminger793b8832005-09-14 16:06:14 -07003463 .suspend = sky2_suspend,
3464 .resume = sky2_resume,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003465#endif
3466};
3467
3468static int __init sky2_init_module(void)
3469{
shemminger@osdl.org50241c42005-11-30 11:45:22 -08003470 return pci_register_driver(&sky2_driver);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003471}
3472
3473static void __exit sky2_cleanup_module(void)
3474{
3475 pci_unregister_driver(&sky2_driver);
3476}
3477
3478module_init(sky2_init_module);
3479module_exit(sky2_cleanup_module);
3480
3481MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3482MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3483MODULE_LICENSE("GPL");
shemminger@osdl.org5f4f9dc2005-11-30 11:45:23 -08003484MODULE_VERSION(DRV_VERSION);