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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020043#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include "scsi.h"
46#include <scsi/scsi_host.h>
47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
Jeff Garzikead5de92005-05-31 11:53:57 -040051#define DRV_VERSION "1.01"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
Jeff Garzika0ea7322005-06-04 01:13:15 -040062 AHCI_CMD_TBL_CDB = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69
70 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
71
72 board_ahci = 0,
73
74 /* global controller registers */
75 HOST_CAP = 0x00, /* host capabilities */
76 HOST_CTL = 0x04, /* global host control */
77 HOST_IRQ_STAT = 0x08, /* interrupt status */
78 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
80
81 /* HOST_CTL bits */
82 HOST_RESET = (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
85
86 /* HOST_CAP bits */
87 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
88
89 /* registers for each SATA port */
90 PORT_LST_ADDR = 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT = 0x10, /* interrupt status */
95 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
96 PORT_CMD = 0x18, /* port command */
97 PORT_TFDATA = 0x20, /* taskfile data */
98 PORT_SIG = 0x24, /* device TF signature */
99 PORT_CMD_ISSUE = 0x38, /* command issue */
100 PORT_SCR = 0x28, /* SATA phy register block */
101 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
105
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
115
116 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
125
126 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
127 PORT_IRQ_HBUS_ERR |
128 PORT_IRQ_HBUS_DATA_ERR |
129 PORT_IRQ_IF_ERR,
130 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
131 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
132 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
133 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
134 PORT_IRQ_D2H_REG_FIS,
135
136 /* PORT_CMD bits */
137 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
138 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
139 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
140 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
141 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
142 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
143
144 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
145 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
146 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400147
148 /* hpriv->flags bits */
149 AHCI_FLAG_MSI = (1 << 0),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150};
151
152struct ahci_cmd_hdr {
153 u32 opts;
154 u32 status;
155 u32 tbl_addr;
156 u32 tbl_addr_hi;
157 u32 reserved[4];
158};
159
160struct ahci_sg {
161 u32 addr;
162 u32 addr_hi;
163 u32 reserved;
164 u32 flags_size;
165};
166
167struct ahci_host_priv {
168 unsigned long flags;
169 u32 cap; /* cache of HOST_CAP register */
170 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
171};
172
173struct ahci_port_priv {
174 struct ahci_cmd_hdr *cmd_slot;
175 dma_addr_t cmd_slot_dma;
176 void *cmd_tbl;
177 dma_addr_t cmd_tbl_dma;
178 struct ahci_sg *cmd_tbl_sg;
179 void *rx_fis;
180 dma_addr_t rx_fis_dma;
181};
182
183static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
184static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
185static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
186static int ahci_qc_issue(struct ata_queued_cmd *qc);
187static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
188static void ahci_phy_reset(struct ata_port *ap);
189static void ahci_irq_clear(struct ata_port *ap);
190static void ahci_eng_timeout(struct ata_port *ap);
191static int ahci_port_start(struct ata_port *ap);
192static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
194static void ahci_qc_prep(struct ata_queued_cmd *qc);
195static u8 ahci_check_status(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
Jeff Garzik907f4672005-05-12 15:03:42 -0400197static void ahci_remove_one (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198
199static Scsi_Host_Template ahci_sht = {
200 .module = THIS_MODULE,
201 .name = DRV_NAME,
202 .ioctl = ata_scsi_ioctl,
203 .queuecommand = ata_scsi_queuecmd,
204 .eh_strategy_handler = ata_scsi_error,
205 .can_queue = ATA_DEF_QUEUE,
206 .this_id = ATA_SHT_THIS_ID,
207 .sg_tablesize = AHCI_MAX_SG,
208 .max_sectors = ATA_MAX_SECTORS,
209 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
210 .emulated = ATA_SHT_EMULATED,
211 .use_clustering = AHCI_USE_CLUSTERING,
212 .proc_name = DRV_NAME,
213 .dma_boundary = AHCI_DMA_BOUNDARY,
214 .slave_configure = ata_scsi_slave_config,
215 .bios_param = ata_std_bios_param,
216 .ordered_flush = 1,
217};
218
Jeff Garzik057ace52005-10-22 14:27:05 -0400219static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 .port_disable = ata_port_disable,
221
222 .check_status = ahci_check_status,
223 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 .dev_select = ata_noop_dev_select,
225
226 .tf_read = ahci_tf_read,
227
228 .phy_reset = ahci_phy_reset,
229
230 .qc_prep = ahci_qc_prep,
231 .qc_issue = ahci_qc_issue,
232
233 .eng_timeout = ahci_eng_timeout,
234
235 .irq_handler = ahci_interrupt,
236 .irq_clear = ahci_irq_clear,
237
238 .scr_read = ahci_scr_read,
239 .scr_write = ahci_scr_write,
240
241 .port_start = ahci_port_start,
242 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243};
244
245static struct ata_port_info ahci_port_info[] = {
246 /* board_ahci */
247 {
248 .sht = &ahci_sht,
249 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
250 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
251 ATA_FLAG_PIO_DMA,
Brett Russ7da79312005-09-01 21:53:34 -0400252 .pio_mask = 0x1f, /* pio0-4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
254 .port_ops = &ahci_ops,
255 },
256};
257
258static struct pci_device_id ahci_pci_tbl[] = {
259 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 board_ahci }, /* ICH6 */
261 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH6M */
263 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ICH7 */
265 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ICH7M */
267 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ICH7R */
269 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ULi M5288 */
Jason Gaston680d3232005-04-16 15:24:45 -0700271 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
272 board_ahci }, /* ESB2 */
273 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 board_ahci }, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ESB2 */
Jason Gaston3db368f2005-08-10 06:18:43 -0700277 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ICH7-M DH */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279 { } /* terminate list */
280};
281
282
283static struct pci_driver ahci_pci_driver = {
284 .name = DRV_NAME,
285 .id_table = ahci_pci_tbl,
286 .probe = ahci_init_one,
Jeff Garzik907f4672005-05-12 15:03:42 -0400287 .remove = ahci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288};
289
290
291static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
292{
293 return base + 0x100 + (port * 0x80);
294}
295
Jeff Garzikea6ba102005-08-30 05:18:18 -0400296static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400298 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299}
300
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301static int ahci_port_start(struct ata_port *ap)
302{
303 struct device *dev = ap->host_set->dev;
304 struct ahci_host_priv *hpriv = ap->host_set->private_data;
305 struct ahci_port_priv *pp;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400306 void __iomem *mmio = ap->host_set->mmio_base;
307 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
308 void *mem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309 dma_addr_t mem_dma;
310
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
Tejun Heo0a139e72005-06-26 23:52:50 +0900312 if (!pp)
313 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314 memset(pp, 0, sizeof(*pp));
315
316 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
317 if (!mem) {
Tejun Heo0a139e72005-06-26 23:52:50 +0900318 kfree(pp);
319 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 }
321 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
322
323 /*
324 * First item in chunk of DMA memory: 32-slot command table,
325 * 32 bytes each in size
326 */
327 pp->cmd_slot = mem;
328 pp->cmd_slot_dma = mem_dma;
329
330 mem += AHCI_CMD_SLOT_SZ;
331 mem_dma += AHCI_CMD_SLOT_SZ;
332
333 /*
334 * Second item: Received-FIS area
335 */
336 pp->rx_fis = mem;
337 pp->rx_fis_dma = mem_dma;
338
339 mem += AHCI_RX_FIS_SZ;
340 mem_dma += AHCI_RX_FIS_SZ;
341
342 /*
343 * Third item: data area for storing a single command
344 * and its scatter-gather table
345 */
346 pp->cmd_tbl = mem;
347 pp->cmd_tbl_dma = mem_dma;
348
349 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
350
351 ap->private_data = pp;
352
353 if (hpriv->cap & HOST_CAP_64)
354 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
355 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
356 readl(port_mmio + PORT_LST_ADDR); /* flush */
357
358 if (hpriv->cap & HOST_CAP_64)
359 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
360 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
361 readl(port_mmio + PORT_FIS_ADDR); /* flush */
362
363 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
364 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
365 PORT_CMD_START, port_mmio + PORT_CMD);
366 readl(port_mmio + PORT_CMD); /* flush */
367
368 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369}
370
371
372static void ahci_port_stop(struct ata_port *ap)
373{
374 struct device *dev = ap->host_set->dev;
375 struct ahci_port_priv *pp = ap->private_data;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400376 void __iomem *mmio = ap->host_set->mmio_base;
377 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 u32 tmp;
379
380 tmp = readl(port_mmio + PORT_CMD);
381 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
382 writel(tmp, port_mmio + PORT_CMD);
383 readl(port_mmio + PORT_CMD); /* flush */
384
385 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
386 * this is slightly incorrect.
387 */
388 msleep(500);
389
390 ap->private_data = NULL;
391 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
392 pp->cmd_slot, pp->cmd_slot_dma);
393 kfree(pp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394}
395
396static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
397{
398 unsigned int sc_reg;
399
400 switch (sc_reg_in) {
401 case SCR_STATUS: sc_reg = 0; break;
402 case SCR_CONTROL: sc_reg = 1; break;
403 case SCR_ERROR: sc_reg = 2; break;
404 case SCR_ACTIVE: sc_reg = 3; break;
405 default:
406 return 0xffffffffU;
407 }
408
Al Viro1e4f2a92005-10-21 06:46:02 +0100409 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410}
411
412
413static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
414 u32 val)
415{
416 unsigned int sc_reg;
417
418 switch (sc_reg_in) {
419 case SCR_STATUS: sc_reg = 0; break;
420 case SCR_CONTROL: sc_reg = 1; break;
421 case SCR_ERROR: sc_reg = 2; break;
422 case SCR_ACTIVE: sc_reg = 3; break;
423 default:
424 return;
425 }
426
Al Viro1e4f2a92005-10-21 06:46:02 +0100427 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428}
429
430static void ahci_phy_reset(struct ata_port *ap)
431{
432 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
433 struct ata_taskfile tf;
434 struct ata_device *dev = &ap->device[0];
435 u32 tmp;
436
437 __sata_phy_reset(ap);
438
439 if (ap->flags & ATA_FLAG_PORT_DISABLED)
440 return;
441
442 tmp = readl(port_mmio + PORT_SIG);
443 tf.lbah = (tmp >> 24) & 0xff;
444 tf.lbam = (tmp >> 16) & 0xff;
445 tf.lbal = (tmp >> 8) & 0xff;
446 tf.nsect = (tmp) & 0xff;
447
448 dev->class = ata_dev_classify(&tf);
449 if (!ata_dev_present(dev))
450 ata_port_disable(ap);
451}
452
453static u8 ahci_check_status(struct ata_port *ap)
454{
Al Viro1e4f2a92005-10-21 06:46:02 +0100455 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
457 return readl(mmio + PORT_TFDATA) & 0xFF;
458}
459
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
461{
462 struct ahci_port_priv *pp = ap->private_data;
463 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
464
465 ata_tf_from_fis(d2h_fis, tf);
466}
467
468static void ahci_fill_sg(struct ata_queued_cmd *qc)
469{
470 struct ahci_port_priv *pp = qc->ap->private_data;
471 unsigned int i;
472
473 VPRINTK("ENTER\n");
474
475 /*
476 * Next, the S/G list.
477 */
478 for (i = 0; i < qc->n_elem; i++) {
479 u32 sg_len;
480 dma_addr_t addr;
481
482 addr = sg_dma_address(&qc->sg[i]);
483 sg_len = sg_dma_len(&qc->sg[i]);
484
485 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
486 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
487 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
488 }
489}
490
491static void ahci_qc_prep(struct ata_queued_cmd *qc)
492{
Jeff Garzika0ea7322005-06-04 01:13:15 -0400493 struct ata_port *ap = qc->ap;
494 struct ahci_port_priv *pp = ap->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495 u32 opts;
496 const u32 cmd_fis_len = 5; /* five dwords */
497
498 /*
499 * Fill in command slot information (currently only one slot,
500 * slot 0, is currently since we don't do queueing)
501 */
502
503 opts = (qc->n_elem << 16) | cmd_fis_len;
504 if (qc->tf.flags & ATA_TFLAG_WRITE)
505 opts |= AHCI_CMD_WRITE;
Jeff Garzika0ea7322005-06-04 01:13:15 -0400506 if (is_atapi_taskfile(&qc->tf))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507 opts |= AHCI_CMD_ATAPI;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508
509 pp->cmd_slot[0].opts = cpu_to_le32(opts);
510 pp->cmd_slot[0].status = 0;
511 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
512 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
513
514 /*
515 * Fill in command table information. First, the header,
516 * a SATA Register - Host to Device command FIS.
517 */
518 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
Jeff Garzika0ea7322005-06-04 01:13:15 -0400519 if (opts & AHCI_CMD_ATAPI) {
520 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
521 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
522 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523
524 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
525 return;
526
527 ahci_fill_sg(qc);
528}
529
530static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
531{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400532 void __iomem *mmio = ap->host_set->mmio_base;
533 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534 u32 tmp;
535 int work;
536
537 /* stop DMA */
538 tmp = readl(port_mmio + PORT_CMD);
539 tmp &= ~PORT_CMD_START;
540 writel(tmp, port_mmio + PORT_CMD);
541
542 /* wait for engine to stop. TODO: this could be
543 * as long as 500 msec
544 */
545 work = 1000;
546 while (work-- > 0) {
547 tmp = readl(port_mmio + PORT_CMD);
548 if ((tmp & PORT_CMD_LIST_ON) == 0)
549 break;
550 udelay(10);
551 }
552
553 /* clear SATA phy error, if any */
554 tmp = readl(port_mmio + PORT_SCR_ERR);
555 writel(tmp, port_mmio + PORT_SCR_ERR);
556
557 /* if DRQ/BSY is set, device needs to be reset.
558 * if so, issue COMRESET
559 */
560 tmp = readl(port_mmio + PORT_TFDATA);
561 if (tmp & (ATA_BUSY | ATA_DRQ)) {
562 writel(0x301, port_mmio + PORT_SCR_CTL);
563 readl(port_mmio + PORT_SCR_CTL); /* flush */
564 udelay(10);
565 writel(0x300, port_mmio + PORT_SCR_CTL);
566 readl(port_mmio + PORT_SCR_CTL); /* flush */
567 }
568
569 /* re-start DMA */
570 tmp = readl(port_mmio + PORT_CMD);
571 tmp |= PORT_CMD_START;
572 writel(tmp, port_mmio + PORT_CMD);
573 readl(port_mmio + PORT_CMD); /* flush */
574
575 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
576}
577
578static void ahci_eng_timeout(struct ata_port *ap)
579{
Jeff Garzikb8f61532005-08-25 22:01:20 -0400580 struct ata_host_set *host_set = ap->host_set;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400581 void __iomem *mmio = host_set->mmio_base;
582 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583 struct ata_queued_cmd *qc;
Jeff Garzikb8f61532005-08-25 22:01:20 -0400584 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585
586 DPRINTK("ENTER\n");
587
Jeff Garzikb8f61532005-08-25 22:01:20 -0400588 spin_lock_irqsave(&host_set->lock, flags);
589
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
591
592 qc = ata_qc_from_tag(ap, ap->active_tag);
593 if (!qc) {
594 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
595 ap->id);
596 } else {
597 /* hack alert! We cannot use the supplied completion
598 * function from inside the ->eh_strategy_handler() thread.
599 * libata is the only user of ->eh_strategy_handler() in
600 * any kernel, so the default scsi_done() assumes it is
601 * not being called from the SCSI EH.
602 */
603 qc->scsidone = scsi_finish_command;
Jeff Garzika7dac442005-10-30 04:44:42 -0500604 ata_qc_complete(qc, AC_ERR_OTHER);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605 }
606
Jeff Garzikb8f61532005-08-25 22:01:20 -0400607 spin_unlock_irqrestore(&host_set->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608}
609
610static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
611{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400612 void __iomem *mmio = ap->host_set->mmio_base;
613 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 u32 status, serr, ci;
615
616 serr = readl(port_mmio + PORT_SCR_ERR);
617 writel(serr, port_mmio + PORT_SCR_ERR);
618
619 status = readl(port_mmio + PORT_IRQ_STAT);
620 writel(status, port_mmio + PORT_IRQ_STAT);
621
622 ci = readl(port_mmio + PORT_CMD_ISSUE);
623 if (likely((ci & 0x1) == 0)) {
624 if (qc) {
625 ata_qc_complete(qc, 0);
626 qc = NULL;
627 }
628 }
629
630 if (status & PORT_IRQ_FATAL) {
631 ahci_intr_error(ap, status);
632 if (qc)
Jeff Garzika7dac442005-10-30 04:44:42 -0500633 ata_qc_complete(qc, AC_ERR_OTHER);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 }
635
636 return 1;
637}
638
639static void ahci_irq_clear(struct ata_port *ap)
640{
641 /* TODO */
642}
643
644static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
645{
646 struct ata_host_set *host_set = dev_instance;
647 struct ahci_host_priv *hpriv;
648 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400649 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650 u32 irq_stat, irq_ack = 0;
651
652 VPRINTK("ENTER\n");
653
654 hpriv = host_set->private_data;
655 mmio = host_set->mmio_base;
656
657 /* sigh. 0xffffffff is a valid return from h/w */
658 irq_stat = readl(mmio + HOST_IRQ_STAT);
659 irq_stat &= hpriv->port_map;
660 if (!irq_stat)
661 return IRQ_NONE;
662
663 spin_lock(&host_set->lock);
664
665 for (i = 0; i < host_set->n_ports; i++) {
666 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667
Jeff Garzik67846b32005-10-05 02:58:32 -0400668 if (!(irq_stat & (1 << i)))
669 continue;
670
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 ap = host_set->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -0400672 if (ap) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 struct ata_queued_cmd *qc;
674 qc = ata_qc_from_tag(ap, ap->active_tag);
Jeff Garzik67846b32005-10-05 02:58:32 -0400675 if (!ahci_host_intr(ap, qc))
676 if (ata_ratelimit()) {
677 struct pci_dev *pdev =
Jeff Garzika9524a72005-10-30 14:39:11 -0500678 to_pci_dev(ap->host_set->dev);
679 dev_printk(KERN_WARNING, &pdev->dev,
680 "unhandled interrupt on port %u\n",
681 i);
Jeff Garzik67846b32005-10-05 02:58:32 -0400682 }
683
684 VPRINTK("port %u\n", i);
685 } else {
686 VPRINTK("port %u (no irq)\n", i);
687 if (ata_ratelimit()) {
688 struct pci_dev *pdev =
Jeff Garzika9524a72005-10-30 14:39:11 -0500689 to_pci_dev(ap->host_set->dev);
690 dev_printk(KERN_WARNING, &pdev->dev,
691 "interrupt on disabled port %u\n", i);
Jeff Garzik67846b32005-10-05 02:58:32 -0400692 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 }
Jeff Garzik67846b32005-10-05 02:58:32 -0400694
695 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696 }
697
698 if (irq_ack) {
699 writel(irq_ack, mmio + HOST_IRQ_STAT);
700 handled = 1;
701 }
702
703 spin_unlock(&host_set->lock);
704
705 VPRINTK("EXIT\n");
706
707 return IRQ_RETVAL(handled);
708}
709
710static int ahci_qc_issue(struct ata_queued_cmd *qc)
711{
712 struct ata_port *ap = qc->ap;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400713 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715 writel(1, port_mmio + PORT_CMD_ISSUE);
716 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
717
718 return 0;
719}
720
721static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
722 unsigned int port_idx)
723{
724 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
725 base = ahci_port_base_ul(base, port_idx);
726 VPRINTK("base now==0x%lx\n", base);
727
728 port->cmd_addr = base;
729 port->scr_addr = base + PORT_SCR;
730
731 VPRINTK("EXIT\n");
732}
733
734static int ahci_host_init(struct ata_probe_ent *probe_ent)
735{
736 struct ahci_host_priv *hpriv = probe_ent->private_data;
737 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
738 void __iomem *mmio = probe_ent->mmio_base;
739 u32 tmp, cap_save;
740 u16 tmp16;
741 unsigned int i, j, using_dac;
742 int rc;
743 void __iomem *port_mmio;
744
745 cap_save = readl(mmio + HOST_CAP);
746 cap_save &= ( (1<<28) | (1<<17) );
747 cap_save |= (1 << 27);
748
749 /* global controller reset */
750 tmp = readl(mmio + HOST_CTL);
751 if ((tmp & HOST_RESET) == 0) {
752 writel(tmp | HOST_RESET, mmio + HOST_CTL);
753 readl(mmio + HOST_CTL); /* flush */
754 }
755
756 /* reset must complete within 1 second, or
757 * the hardware should be considered fried.
758 */
759 ssleep(1);
760
761 tmp = readl(mmio + HOST_CTL);
762 if (tmp & HOST_RESET) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500763 dev_printk(KERN_ERR, &pdev->dev,
764 "controller reset failed (0x%x)\n", tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 return -EIO;
766 }
767
768 writel(HOST_AHCI_EN, mmio + HOST_CTL);
769 (void) readl(mmio + HOST_CTL); /* flush */
770 writel(cap_save, mmio + HOST_CAP);
771 writel(0xf, mmio + HOST_PORTS_IMPL);
772 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
773
774 pci_read_config_word(pdev, 0x92, &tmp16);
775 tmp16 |= 0xf;
776 pci_write_config_word(pdev, 0x92, tmp16);
777
778 hpriv->cap = readl(mmio + HOST_CAP);
779 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
780 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
781
782 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
783 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
784
785 using_dac = hpriv->cap & HOST_CAP_64;
786 if (using_dac &&
787 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
788 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
789 if (rc) {
790 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
791 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500792 dev_printk(KERN_ERR, &pdev->dev,
793 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 return rc;
795 }
796 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 } else {
798 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
799 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500800 dev_printk(KERN_ERR, &pdev->dev,
801 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 return rc;
803 }
804 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
805 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500806 dev_printk(KERN_ERR, &pdev->dev,
807 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808 return rc;
809 }
810 }
811
812 for (i = 0; i < probe_ent->n_ports; i++) {
813#if 0 /* BIOSen initialize this incorrectly */
814 if (!(hpriv->port_map & (1 << i)))
815 continue;
816#endif
817
818 port_mmio = ahci_port_base(mmio, i);
819 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
820
821 ahci_setup_port(&probe_ent->port[i],
822 (unsigned long) mmio, i);
823
824 /* make sure port is not active */
825 tmp = readl(port_mmio + PORT_CMD);
826 VPRINTK("PORT_CMD 0x%x\n", tmp);
827 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
828 PORT_CMD_FIS_RX | PORT_CMD_START)) {
829 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
830 PORT_CMD_FIS_RX | PORT_CMD_START);
831 writel(tmp, port_mmio + PORT_CMD);
832 readl(port_mmio + PORT_CMD); /* flush */
833
834 /* spec says 500 msecs for each bit, so
835 * this is slightly incorrect.
836 */
837 msleep(500);
838 }
839
840 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
841
842 j = 0;
843 while (j < 100) {
844 msleep(10);
845 tmp = readl(port_mmio + PORT_SCR_STAT);
846 if ((tmp & 0xf) == 0x3)
847 break;
848 j++;
849 }
850
851 tmp = readl(port_mmio + PORT_SCR_ERR);
852 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
853 writel(tmp, port_mmio + PORT_SCR_ERR);
854
855 /* ack any pending irq events for this port */
856 tmp = readl(port_mmio + PORT_IRQ_STAT);
857 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
858 if (tmp)
859 writel(tmp, port_mmio + PORT_IRQ_STAT);
860
861 writel(1 << i, mmio + HOST_IRQ_STAT);
862
863 /* set irq mask (enables interrupts) */
864 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
865 }
866
867 tmp = readl(mmio + HOST_CTL);
868 VPRINTK("HOST_CTL 0x%x\n", tmp);
869 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
870 tmp = readl(mmio + HOST_CTL);
871 VPRINTK("HOST_CTL 0x%x\n", tmp);
872
873 pci_set_master(pdev);
874
875 return 0;
876}
877
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878static void ahci_print_info(struct ata_probe_ent *probe_ent)
879{
880 struct ahci_host_priv *hpriv = probe_ent->private_data;
881 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
Jeff Garzikea6ba102005-08-30 05:18:18 -0400882 void __iomem *mmio = probe_ent->mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 u32 vers, cap, impl, speed;
884 const char *speed_s;
885 u16 cc;
886 const char *scc_s;
887
888 vers = readl(mmio + HOST_VERSION);
889 cap = hpriv->cap;
890 impl = hpriv->port_map;
891
892 speed = (cap >> 20) & 0xf;
893 if (speed == 1)
894 speed_s = "1.5";
895 else if (speed == 2)
896 speed_s = "3";
897 else
898 speed_s = "?";
899
900 pci_read_config_word(pdev, 0x0a, &cc);
901 if (cc == 0x0101)
902 scc_s = "IDE";
903 else if (cc == 0x0106)
904 scc_s = "SATA";
905 else if (cc == 0x0104)
906 scc_s = "RAID";
907 else
908 scc_s = "unknown";
909
Jeff Garzika9524a72005-10-30 14:39:11 -0500910 dev_printk(KERN_INFO, &pdev->dev,
911 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
913 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914
915 (vers >> 24) & 0xff,
916 (vers >> 16) & 0xff,
917 (vers >> 8) & 0xff,
918 vers & 0xff,
919
920 ((cap >> 8) & 0x1f) + 1,
921 (cap & 0x1f) + 1,
922 speed_s,
923 impl,
924 scc_s);
925
Jeff Garzika9524a72005-10-30 14:39:11 -0500926 dev_printk(KERN_INFO, &pdev->dev,
927 "flags: "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700928 "%s%s%s%s%s%s"
929 "%s%s%s%s%s%s%s\n"
930 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931
932 cap & (1 << 31) ? "64bit " : "",
933 cap & (1 << 30) ? "ncq " : "",
934 cap & (1 << 28) ? "ilck " : "",
935 cap & (1 << 27) ? "stag " : "",
936 cap & (1 << 26) ? "pm " : "",
937 cap & (1 << 25) ? "led " : "",
938
939 cap & (1 << 24) ? "clo " : "",
940 cap & (1 << 19) ? "nz " : "",
941 cap & (1 << 18) ? "only " : "",
942 cap & (1 << 17) ? "pmp " : "",
943 cap & (1 << 15) ? "pio " : "",
944 cap & (1 << 14) ? "slum " : "",
945 cap & (1 << 13) ? "part " : ""
946 );
947}
948
949static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
950{
951 static int printed_version;
952 struct ata_probe_ent *probe_ent = NULL;
953 struct ahci_host_priv *hpriv;
954 unsigned long base;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400955 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 unsigned int board_idx = (unsigned int) ent->driver_data;
Jeff Garzik907f4672005-05-12 15:03:42 -0400957 int have_msi, pci_dev_busy = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958 int rc;
959
960 VPRINTK("ENTER\n");
961
962 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500963 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964
965 rc = pci_enable_device(pdev);
966 if (rc)
967 return rc;
968
969 rc = pci_request_regions(pdev, DRV_NAME);
970 if (rc) {
971 pci_dev_busy = 1;
972 goto err_out;
973 }
974
Jeff Garzik907f4672005-05-12 15:03:42 -0400975 if (pci_enable_msi(pdev) == 0)
976 have_msi = 1;
977 else {
978 pci_intx(pdev, 1);
979 have_msi = 0;
980 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981
982 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
983 if (probe_ent == NULL) {
984 rc = -ENOMEM;
Jeff Garzik907f4672005-05-12 15:03:42 -0400985 goto err_out_msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986 }
987
988 memset(probe_ent, 0, sizeof(*probe_ent));
989 probe_ent->dev = pci_dev_to_dev(pdev);
990 INIT_LIST_HEAD(&probe_ent->node);
991
Jeff Garzik374b1872005-08-30 05:42:52 -0400992 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 if (mmio_base == NULL) {
994 rc = -ENOMEM;
995 goto err_out_free_ent;
996 }
997 base = (unsigned long) mmio_base;
998
999 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1000 if (!hpriv) {
1001 rc = -ENOMEM;
1002 goto err_out_iounmap;
1003 }
1004 memset(hpriv, 0, sizeof(*hpriv));
1005
1006 probe_ent->sht = ahci_port_info[board_idx].sht;
1007 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1008 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1009 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1010 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1011
1012 probe_ent->irq = pdev->irq;
1013 probe_ent->irq_flags = SA_SHIRQ;
1014 probe_ent->mmio_base = mmio_base;
1015 probe_ent->private_data = hpriv;
1016
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001017 if (have_msi)
1018 hpriv->flags |= AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001019
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 /* initialize adapter */
1021 rc = ahci_host_init(probe_ent);
1022 if (rc)
1023 goto err_out_hpriv;
1024
1025 ahci_print_info(probe_ent);
1026
1027 /* FIXME: check ata_device_add return value */
1028 ata_device_add(probe_ent);
1029 kfree(probe_ent);
1030
1031 return 0;
1032
1033err_out_hpriv:
1034 kfree(hpriv);
1035err_out_iounmap:
Jeff Garzik374b1872005-08-30 05:42:52 -04001036 pci_iounmap(pdev, mmio_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037err_out_free_ent:
1038 kfree(probe_ent);
Jeff Garzik907f4672005-05-12 15:03:42 -04001039err_out_msi:
1040 if (have_msi)
1041 pci_disable_msi(pdev);
1042 else
1043 pci_intx(pdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 pci_release_regions(pdev);
1045err_out:
1046 if (!pci_dev_busy)
1047 pci_disable_device(pdev);
1048 return rc;
1049}
1050
Jeff Garzik907f4672005-05-12 15:03:42 -04001051static void ahci_remove_one (struct pci_dev *pdev)
1052{
1053 struct device *dev = pci_dev_to_dev(pdev);
1054 struct ata_host_set *host_set = dev_get_drvdata(dev);
1055 struct ahci_host_priv *hpriv = host_set->private_data;
1056 struct ata_port *ap;
1057 unsigned int i;
1058 int have_msi;
1059
1060 for (i = 0; i < host_set->n_ports; i++) {
1061 ap = host_set->ports[i];
1062
1063 scsi_remove_host(ap->host);
1064 }
1065
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001066 have_msi = hpriv->flags & AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001067 free_irq(host_set->irq, host_set);
Jeff Garzik907f4672005-05-12 15:03:42 -04001068
1069 for (i = 0; i < host_set->n_ports; i++) {
1070 ap = host_set->ports[i];
1071
1072 ata_scsi_release(ap->host);
1073 scsi_host_put(ap->host);
1074 }
1075
Jeff Garzike005f012005-08-30 04:18:28 -04001076 kfree(hpriv);
Jeff Garzik374b1872005-08-30 05:42:52 -04001077 pci_iounmap(pdev, host_set->mmio_base);
Jeff Garzikead5de92005-05-31 11:53:57 -04001078 kfree(host_set);
1079
Jeff Garzik907f4672005-05-12 15:03:42 -04001080 if (have_msi)
1081 pci_disable_msi(pdev);
1082 else
1083 pci_intx(pdev, 0);
1084 pci_release_regions(pdev);
Jeff Garzik907f4672005-05-12 15:03:42 -04001085 pci_disable_device(pdev);
1086 dev_set_drvdata(dev, NULL);
1087}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088
1089static int __init ahci_init(void)
1090{
1091 return pci_module_init(&ahci_pci_driver);
1092}
1093
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094static void __exit ahci_exit(void)
1095{
1096 pci_unregister_driver(&ahci_pci_driver);
1097}
1098
1099
1100MODULE_AUTHOR("Jeff Garzik");
1101MODULE_DESCRIPTION("AHCI SATA low-level driver");
1102MODULE_LICENSE("GPL");
1103MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001104MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105
1106module_init(ahci_init);
1107module_exit(ahci_exit);