blob: ceb03c9e749f8f918732d88c635de618d1f04125 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/string.h>
20#include <linux/kernel.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/tty.h>
24#include <linux/serial_core.h>
25#include <linux/8250_pci.h>
26#include <linux/bitops.h>
27
28#include <asm/byteorder.h>
29#include <asm/io.h>
30
31#include "8250.h"
32
33#undef SERIAL_DEBUG_PCI
34
35/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070036 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
46 int (*init)(struct pci_dev *dev);
Russell King70db3d92005-07-27 11:34:27 +010047 int (*setup)(struct serial_private *, struct pciserial_board *,
Russell King05caac52005-07-27 11:41:18 +010048 struct uart_port *, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 void (*exit)(struct pci_dev *dev);
50};
51
52#define PCI_NUM_BAR_RESOURCES 6
53
54struct serial_private {
Russell King70db3d92005-07-27 11:34:27 +010055 struct pci_dev *dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 int line[0];
60};
61
62static void moan_device(const char *str, struct pci_dev *dev)
63{
64 printk(KERN_WARNING "%s: %s\n"
65 KERN_WARNING "Please send the output of lspci -vv, this\n"
66 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 KERN_WARNING "manufacturer and name of serial board or\n"
68 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71}
72
73static int
Russell King70db3d92005-07-27 11:34:27 +010074setup_port(struct serial_private *priv, struct uart_port *port,
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 int bar, int offset, int regshift)
76{
Russell King70db3d92005-07-27 11:34:27 +010077 struct pci_dev *dev = priv->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
Russell King72ce9a82005-07-27 11:32:04 +010083 base = pci_resource_start(dev, bar);
84
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
Russell King72ce9a82005-07-27 11:32:04 +010094 port->iobase = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070099 port->iotype = UPIO_PORT;
Russell King72ce9a82005-07-27 11:32:04 +0100100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 }
105 return 0;
106}
107
108/*
109 * AFAVLAB uses a different mixture of BARs and offsets
110 * Not that ugly ;) -- HW
111 */
112static int
Russell King70db3d92005-07-27 11:34:27 +0100113afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 struct uart_port *port, int idx)
115{
116 unsigned int bar, offset = board->first_offset;
117
118 bar = FL_GET_BASE(board->flags);
119 if (idx < 4)
120 bar += idx;
121 else {
122 bar = 4;
123 offset += (idx - 4) * board->uart_offset;
124 }
125
Russell King70db3d92005-07-27 11:34:27 +0100126 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127}
128
129/*
130 * HP's Remote Management Console. The Diva chip came in several
131 * different versions. N-class, L2000 and A500 have two Diva chips, each
132 * with 3 UARTs (the third UART on the second chip is unused). Superdome
133 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
134 * one Diva chip, but it has been expanded to 5 UARTs.
135 */
Russell King61a116e2006-07-03 15:22:35 +0100136static int pci_hp_diva_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137{
138 int rc = 0;
139
140 switch (dev->subsystem_device) {
141 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
142 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
143 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
144 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
145 rc = 3;
146 break;
147 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
148 rc = 2;
149 break;
150 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
151 rc = 4;
152 break;
153 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
Justin Chen551f8f02005-10-24 22:16:38 +0100154 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 rc = 1;
156 break;
157 }
158
159 return rc;
160}
161
162/*
163 * HP's Diva chip puts the 4th/5th serial port further out, and
164 * some serial ports are supposed to be hidden on certain models.
165 */
166static int
Russell King70db3d92005-07-27 11:34:27 +0100167pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 struct uart_port *port, int idx)
169{
170 unsigned int offset = board->first_offset;
171 unsigned int bar = FL_GET_BASE(board->flags);
172
Russell King70db3d92005-07-27 11:34:27 +0100173 switch (priv->dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175 if (idx == 3)
176 idx++;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
179 if (idx > 0)
180 idx++;
181 if (idx > 2)
182 idx++;
183 break;
184 }
185 if (idx > 2)
186 offset = 0x18;
187
188 offset += idx * board->uart_offset;
189
Russell King70db3d92005-07-27 11:34:27 +0100190 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191}
192
193/*
194 * Added for EKF Intel i960 serial boards
195 */
Russell King61a116e2006-07-03 15:22:35 +0100196static int pci_inteli960ni_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197{
198 unsigned long oldval;
199
200 if (!(dev->subsystem_device & 0x1000))
201 return -ENODEV;
202
203 /* is firmware started? */
204 pci_read_config_dword(dev, 0x44, (void*) &oldval);
205 if (oldval == 0x00001000L) { /* RESET value */
206 printk(KERN_DEBUG "Local i960 firmware missing");
207 return -ENODEV;
208 }
209 return 0;
210}
211
212/*
213 * Some PCI serial cards using the PLX 9050 PCI interface chip require
214 * that the card interrupt be explicitly enabled or disabled. This
215 * seems to be mainly needed on card using the PLX which also use I/O
216 * mapped memory.
217 */
Russell King61a116e2006-07-03 15:22:35 +0100218static int pci_plx9050_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219{
220 u8 irq_config;
221 void __iomem *p;
222
223 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
224 moan_device("no memory in bar 0", dev);
225 return 0;
226 }
227
228 irq_config = 0x41;
Bjorn Helgaasadd7b582005-10-24 22:11:57 +0100229 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
230 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 irq_config = 0x43;
Bjorn Helgaasadd7b582005-10-24 22:11:57 +0100232 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
234 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
235 /*
236 * As the megawolf cards have the int pins active
237 * high, and have 2 UART chips, both ints must be
238 * enabled on the 9050. Also, the UARTS are set in
239 * 16450 mode by default, so we have to enable the
240 * 16C950 'enhanced' mode so that we can use the
241 * deep FIFOs
242 */
243 irq_config = 0x5b;
244 }
245
246 /*
247 * enable/disable interrupts
248 */
249 p = ioremap(pci_resource_start(dev, 0), 0x80);
250 if (p == NULL)
251 return -ENOMEM;
252 writel(irq_config, p + 0x4c);
253
254 /*
255 * Read the register back to ensure that it took effect.
256 */
257 readl(p + 0x4c);
258 iounmap(p);
259
260 return 0;
261}
262
263static void __devexit pci_plx9050_exit(struct pci_dev *dev)
264{
265 u8 __iomem *p;
266
267 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
268 return;
269
270 /*
271 * disable interrupts
272 */
273 p = ioremap(pci_resource_start(dev, 0), 0x80);
274 if (p != NULL) {
275 writel(0, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282 }
283}
284
285/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
286static int
Russell King70db3d92005-07-27 11:34:27 +0100287sbs_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 struct uart_port *port, int idx)
289{
290 unsigned int bar, offset = board->first_offset;
291
292 bar = 0;
293
294 if (idx < 4) {
295 /* first four channels map to 0, 0x100, 0x200, 0x300 */
296 offset += idx * board->uart_offset;
297 } else if (idx < 8) {
298 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
299 offset += idx * board->uart_offset + 0xC00;
300 } else /* we have only 8 ports on PMC-OCTALPRO */
301 return 1;
302
Russell King70db3d92005-07-27 11:34:27 +0100303 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304}
305
306/*
307* This does initialization for PMC OCTALPRO cards:
308* maps the device memory, resets the UARTs (needed, bc
309* if the module is removed and inserted again, the card
310* is in the sleep mode) and enables global interrupt.
311*/
312
313/* global control register offset for SBS PMC-OctalPro */
314#define OCT_REG_CR_OFF 0x500
315
Russell King61a116e2006-07-03 15:22:35 +0100316static int sbs_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317{
318 u8 __iomem *p;
319
320 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
321
322 if (p == NULL)
323 return -ENOMEM;
324 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
325 writeb(0x10,p + OCT_REG_CR_OFF);
326 udelay(50);
327 writeb(0x0,p + OCT_REG_CR_OFF);
328
329 /* Set bit-2 (INTENABLE) of Control Register */
330 writeb(0x4, p + OCT_REG_CR_OFF);
331 iounmap(p);
332
333 return 0;
334}
335
336/*
337 * Disables the global interrupt of PMC-OctalPro
338 */
339
340static void __devexit sbs_exit(struct pci_dev *dev)
341{
342 u8 __iomem *p;
343
344 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
345 if (p != NULL) {
346 writeb(0, p + OCT_REG_CR_OFF);
347 }
348 iounmap(p);
349}
350
351/*
352 * SIIG serial cards have an PCI interface chip which also controls
353 * the UART clocking frequency. Each UART can be clocked independently
354 * (except cards equiped with 4 UARTs) and initial clocking settings
355 * are stored in the EEPROM chip. It can cause problems because this
356 * version of serial driver doesn't support differently clocked UART's
357 * on single PCI card. To prevent this, initialization functions set
358 * high frequency clocking for all UART's on given card. It is safe (I
359 * hope) because it doesn't touch EEPROM settings to prevent conflicts
360 * with other OSes (like M$ DOS).
361 *
362 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
363 *
364 * There is two family of SIIG serial cards with different PCI
365 * interface chip and different configuration methods:
366 * - 10x cards have control registers in IO and/or memory space;
367 * - 20x cards have control registers in standard PCI configuration space.
368 *
Russell King67d74b82005-07-27 11:33:03 +0100369 * Note: all 10x cards have PCI device ids 0x10..
370 * all 20x cards have PCI device ids 0x20..
371 *
Andrey Paninfbc0dc02005-07-18 11:38:09 +0100372 * There are also Quartet Serial cards which use Oxford Semiconductor
373 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
374 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375 * Note: some SIIG cards are probed by the parport_serial object.
376 */
377
378#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
379#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
380
381static int pci_siig10x_init(struct pci_dev *dev)
382{
383 u16 data;
384 void __iomem *p;
385
386 switch (dev->device & 0xfff8) {
387 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
388 data = 0xffdf;
389 break;
390 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
391 data = 0xf7ff;
392 break;
393 default: /* 1S1P, 4S */
394 data = 0xfffb;
395 break;
396 }
397
398 p = ioremap(pci_resource_start(dev, 0), 0x80);
399 if (p == NULL)
400 return -ENOMEM;
401
402 writew(readw(p + 0x28) & data, p + 0x28);
403 readw(p + 0x28);
404 iounmap(p);
405 return 0;
406}
407
408#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
409#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
410
411static int pci_siig20x_init(struct pci_dev *dev)
412{
413 u8 data;
414
415 /* Change clock frequency for the first UART. */
416 pci_read_config_byte(dev, 0x6f, &data);
417 pci_write_config_byte(dev, 0x6f, data & 0xef);
418
419 /* If this card has 2 UART, we have to do the same with second UART. */
420 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
421 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
422 pci_read_config_byte(dev, 0x73, &data);
423 pci_write_config_byte(dev, 0x73, data & 0xef);
424 }
425 return 0;
426}
427
Russell King67d74b82005-07-27 11:33:03 +0100428static int pci_siig_init(struct pci_dev *dev)
429{
430 unsigned int type = dev->device & 0xff00;
431
432 if (type == 0x1000)
433 return pci_siig10x_init(dev);
434 else if (type == 0x2000)
435 return pci_siig20x_init(dev);
436
437 moan_device("Unknown SIIG card", dev);
438 return -ENODEV;
439}
440
Andrey Panin3ec9c592006-02-02 20:15:09 +0000441static int pci_siig_setup(struct serial_private *priv,
442 struct pciserial_board *board,
443 struct uart_port *port, int idx)
444{
445 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
446
447 if (idx > 3) {
448 bar = 4;
449 offset = (idx - 4) * 8;
450 }
451
452 return setup_port(priv, port, bar, offset, 0);
453}
454
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455/*
456 * Timedia has an explosion of boards, and to avoid the PCI table from
457 * growing *huge*, we use this function to collapse some 70 entries
458 * in the PCI table into one, for sanity's and compactness's sake.
459 */
Helge Dellere9422e02006-08-29 21:57:29 +0200460static const unsigned short timedia_single_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
462};
463
Helge Dellere9422e02006-08-29 21:57:29 +0200464static const unsigned short timedia_dual_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
466 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
467 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
468 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
469 0xD079, 0
470};
471
Helge Dellere9422e02006-08-29 21:57:29 +0200472static const unsigned short timedia_quad_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
474 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
475 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
476 0xB157, 0
477};
478
Helge Dellere9422e02006-08-29 21:57:29 +0200479static const unsigned short timedia_eight_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
481 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
482};
483
Arjan van de Vencb3592b2005-11-28 21:04:11 +0000484static const struct timedia_struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485 int num;
Helge Dellere9422e02006-08-29 21:57:29 +0200486 const unsigned short *ids;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487} timedia_data[] = {
488 { 1, timedia_single_port },
489 { 2, timedia_dual_port },
490 { 4, timedia_quad_port },
Helge Dellere9422e02006-08-29 21:57:29 +0200491 { 8, timedia_eight_port }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492};
493
Russell King61a116e2006-07-03 15:22:35 +0100494static int pci_timedia_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495{
Helge Dellere9422e02006-08-29 21:57:29 +0200496 const unsigned short *ids;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 int i, j;
498
Helge Dellere9422e02006-08-29 21:57:29 +0200499 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 ids = timedia_data[i].ids;
501 for (j = 0; ids[j]; j++)
502 if (dev->subsystem_device == ids[j])
503 return timedia_data[i].num;
504 }
505 return 0;
506}
507
508/*
509 * Timedia/SUNIX uses a mixture of BARs and offsets
510 * Ugh, this is ugly as all hell --- TYT
511 */
512static int
Russell King70db3d92005-07-27 11:34:27 +0100513pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 struct uart_port *port, int idx)
515{
516 unsigned int bar = 0, offset = board->first_offset;
517
518 switch (idx) {
519 case 0:
520 bar = 0;
521 break;
522 case 1:
523 offset = board->uart_offset;
524 bar = 0;
525 break;
526 case 2:
527 bar = 1;
528 break;
529 case 3:
530 offset = board->uart_offset;
Dave Jonesc2cd6d32005-12-07 18:11:26 +0000531 /* FALLTHROUGH */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532 case 4: /* BAR 2 */
533 case 5: /* BAR 3 */
534 case 6: /* BAR 4 */
535 case 7: /* BAR 5 */
536 bar = idx - 2;
537 }
538
Russell King70db3d92005-07-27 11:34:27 +0100539 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540}
541
542/*
543 * Some Titan cards are also a little weird
544 */
545static int
Russell King70db3d92005-07-27 11:34:27 +0100546titan_400l_800l_setup(struct serial_private *priv,
Russell King1c7c1fe2005-07-27 11:31:19 +0100547 struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548 struct uart_port *port, int idx)
549{
550 unsigned int bar, offset = board->first_offset;
551
552 switch (idx) {
553 case 0:
554 bar = 1;
555 break;
556 case 1:
557 bar = 2;
558 break;
559 default:
560 bar = 4;
561 offset = (idx - 2) * board->uart_offset;
562 }
563
Russell King70db3d92005-07-27 11:34:27 +0100564 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565}
566
Russell King61a116e2006-07-03 15:22:35 +0100567static int pci_xircom_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568{
569 msleep(100);
570 return 0;
571}
572
Russell King61a116e2006-07-03 15:22:35 +0100573static int pci_netmos_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574{
575 /* subdevice 0x00PS means <P> parallel, <S> serial */
576 unsigned int num_serial = dev->subsystem_device & 0xf;
577
578 if (num_serial == 0)
579 return -ENODEV;
580 return num_serial;
581}
582
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700583/*
584 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
585 *
586 * These chips are available with optionally one parallel port and up to
587 * two serial ports. Unfortunately they all have the same product id.
588 *
589 * Basic configuration is done over a region of 32 I/O ports. The base
590 * ioport is called INTA or INTC, depending on docs/other drivers.
591 *
592 * The region of the 32 I/O ports is configured in POSIO0R...
593 */
594
595/* registers */
596#define ITE_887x_MISCR 0x9c
597#define ITE_887x_INTCBAR 0x78
598#define ITE_887x_UARTBAR 0x7c
599#define ITE_887x_PS0BAR 0x10
600#define ITE_887x_POSIO0 0x60
601
602/* I/O space size */
603#define ITE_887x_IOSIZE 32
604/* I/O space size (bits 26-24; 8 bytes = 011b) */
605#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
606/* I/O space size (bits 26-24; 32 bytes = 101b) */
607#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
608/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
609#define ITE_887x_POSIO_SPEED (3 << 29)
610/* enable IO_Space bit */
611#define ITE_887x_POSIO_ENABLE (1 << 31)
612
Ralf Baechlef79abb82007-08-30 23:56:31 -0700613static int pci_ite887x_init(struct pci_dev *dev)
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700614{
615 /* inta_addr are the configuration addresses of the ITE */
616 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
617 0x200, 0x280, 0 };
618 int ret, i, type;
619 struct resource *iobase = NULL;
620 u32 miscr, uartbar, ioport;
621
622 /* search for the base-ioport */
623 i = 0;
624 while (inta_addr[i] && iobase == NULL) {
625 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
626 "ite887x");
627 if (iobase != NULL) {
628 /* write POSIO0R - speed | size | ioport */
629 pci_write_config_dword(dev, ITE_887x_POSIO0,
630 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
631 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
632 /* write INTCBAR - ioport */
633 pci_write_config_dword(dev, ITE_887x_INTCBAR, inta_addr[i]);
634 ret = inb(inta_addr[i]);
635 if (ret != 0xff) {
636 /* ioport connected */
637 break;
638 }
639 release_region(iobase->start, ITE_887x_IOSIZE);
640 iobase = NULL;
641 }
642 i++;
643 }
644
645 if (!inta_addr[i]) {
646 printk(KERN_ERR "ite887x: could not find iobase\n");
647 return -ENODEV;
648 }
649
650 /* start of undocumented type checking (see parport_pc.c) */
651 type = inb(iobase->start + 0x18) & 0x0f;
652
653 switch (type) {
654 case 0x2: /* ITE8871 (1P) */
655 case 0xa: /* ITE8875 (1P) */
656 ret = 0;
657 break;
658 case 0xe: /* ITE8872 (2S1P) */
659 ret = 2;
660 break;
661 case 0x6: /* ITE8873 (1S) */
662 ret = 1;
663 break;
664 case 0x8: /* ITE8874 (2S) */
665 ret = 2;
666 break;
667 default:
668 moan_device("Unknown ITE887x", dev);
669 ret = -ENODEV;
670 }
671
672 /* configure all serial ports */
673 for (i = 0; i < ret; i++) {
674 /* read the I/O port from the device */
675 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
676 &ioport);
677 ioport &= 0x0000FF00; /* the actual base address */
678 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
679 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
680 ITE_887x_POSIO_IOSIZE_8 | ioport);
681
682 /* write the ioport to the UARTBAR */
683 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
684 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
685 uartbar |= (ioport << (16 * i)); /* set the ioport */
686 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
687
688 /* get current config */
689 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
690 /* disable interrupts (UARTx_Routing[3:0]) */
691 miscr &= ~(0xf << (12 - 4 * i));
692 /* activate the UART (UARTx_En) */
693 miscr |= 1 << (23 - i);
694 /* write new config with activated UART */
695 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
696 }
697
698 if (ret <= 0) {
699 /* the device has no UARTs if we get here */
700 release_region(iobase->start, ITE_887x_IOSIZE);
701 }
702
703 return ret;
704}
705
706static void __devexit pci_ite887x_exit(struct pci_dev *dev)
707{
708 u32 ioport;
709 /* the ioport is bit 0-15 in POSIO0R */
710 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
711 ioport &= 0xffff;
712 release_region(ioport, ITE_887x_IOSIZE);
713}
714
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715static int
Russell King70db3d92005-07-27 11:34:27 +0100716pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 struct uart_port *port, int idx)
718{
719 unsigned int bar, offset = board->first_offset, maxnr;
720
721 bar = FL_GET_BASE(board->flags);
722 if (board->flags & FL_BASE_BARS)
723 bar += idx;
724 else
725 offset += idx * board->uart_offset;
726
Greg Kroah-Hartman2427ddd2006-06-12 17:07:52 -0700727 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
728 (board->reg_shift + 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729
730 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
731 return 1;
732
Russell King70db3d92005-07-27 11:34:27 +0100733 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734}
735
736/* This should be in linux/pci_ids.h */
737#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
738#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
739#define PCI_DEVICE_ID_OCTPRO 0x0001
740#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
741#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
742#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
743#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
744
745/*
746 * Master list of serial port init/setup/exit quirks.
747 * This does not describe the general nature of the port.
748 * (ie, baud base, number and location of ports, etc)
749 *
750 * This list is ordered alphabetically by vendor then device.
751 * Specific entries must come before more generic entries.
752 */
753static struct pci_serial_quirk pci_serial_quirks[] = {
754 /*
Russell King61a116e2006-07-03 15:22:35 +0100755 * AFAVLAB cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756 * It is not clear whether this applies to all products.
757 */
758 {
759 .vendor = PCI_VENDOR_ID_AFAVLAB,
760 .device = PCI_ANY_ID,
761 .subvendor = PCI_ANY_ID,
762 .subdevice = PCI_ANY_ID,
763 .setup = afavlab_setup,
764 },
765 /*
766 * HP Diva
767 */
768 {
769 .vendor = PCI_VENDOR_ID_HP,
770 .device = PCI_DEVICE_ID_HP_DIVA,
771 .subvendor = PCI_ANY_ID,
772 .subdevice = PCI_ANY_ID,
773 .init = pci_hp_diva_init,
774 .setup = pci_hp_diva_setup,
775 },
776 /*
777 * Intel
778 */
779 {
780 .vendor = PCI_VENDOR_ID_INTEL,
781 .device = PCI_DEVICE_ID_INTEL_80960_RP,
782 .subvendor = 0xe4bf,
783 .subdevice = PCI_ANY_ID,
784 .init = pci_inteli960ni_init,
785 .setup = pci_default_setup,
786 },
787 /*
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700788 * ITE
789 */
790 {
791 .vendor = PCI_VENDOR_ID_ITE,
792 .device = PCI_DEVICE_ID_ITE_8872,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .init = pci_ite887x_init,
796 .setup = pci_default_setup,
797 .exit = __devexit_p(pci_ite887x_exit),
798 },
799 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 * Panacom
801 */
802 {
803 .vendor = PCI_VENDOR_ID_PANACOM,
804 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .init = pci_plx9050_init,
808 .setup = pci_default_setup,
809 .exit = __devexit_p(pci_plx9050_exit),
810 },
811 {
812 .vendor = PCI_VENDOR_ID_PANACOM,
813 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
814 .subvendor = PCI_ANY_ID,
815 .subdevice = PCI_ANY_ID,
816 .init = pci_plx9050_init,
817 .setup = pci_default_setup,
818 .exit = __devexit_p(pci_plx9050_exit),
819 },
820 /*
821 * PLX
822 */
823 {
824 .vendor = PCI_VENDOR_ID_PLX,
Thomas Hoehn48212002007-02-10 01:46:05 -0800825 .device = PCI_DEVICE_ID_PLX_9030,
826 .subvendor = PCI_SUBVENDOR_ID_PERLE,
827 .subdevice = PCI_ANY_ID,
828 .setup = pci_default_setup,
829 },
830 {
831 .vendor = PCI_VENDOR_ID_PLX,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 .device = PCI_DEVICE_ID_PLX_9050,
Bjorn Helgaasadd7b582005-10-24 22:11:57 +0100833 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
834 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
835 .init = pci_plx9050_init,
836 .setup = pci_default_setup,
837 .exit = __devexit_p(pci_plx9050_exit),
838 },
839 {
840 .vendor = PCI_VENDOR_ID_PLX,
841 .device = PCI_DEVICE_ID_PLX_9050,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
843 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
844 .init = pci_plx9050_init,
845 .setup = pci_default_setup,
846 .exit = __devexit_p(pci_plx9050_exit),
847 },
848 {
849 .vendor = PCI_VENDOR_ID_PLX,
850 .device = PCI_DEVICE_ID_PLX_ROMULUS,
851 .subvendor = PCI_VENDOR_ID_PLX,
852 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
853 .init = pci_plx9050_init,
854 .setup = pci_default_setup,
855 .exit = __devexit_p(pci_plx9050_exit),
856 },
857 /*
858 * SBS Technologies, Inc., PMC-OCTALPRO 232
859 */
860 {
861 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
862 .device = PCI_DEVICE_ID_OCTPRO,
863 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
864 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
865 .init = sbs_init,
866 .setup = sbs_setup,
867 .exit = __devexit_p(sbs_exit),
868 },
869 /*
870 * SBS Technologies, Inc., PMC-OCTALPRO 422
871 */
872 {
873 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
874 .device = PCI_DEVICE_ID_OCTPRO,
875 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
876 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
877 .init = sbs_init,
878 .setup = sbs_setup,
879 .exit = __devexit_p(sbs_exit),
880 },
881 /*
882 * SBS Technologies, Inc., P-Octal 232
883 */
884 {
885 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
886 .device = PCI_DEVICE_ID_OCTPRO,
887 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
888 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
889 .init = sbs_init,
890 .setup = sbs_setup,
891 .exit = __devexit_p(sbs_exit),
892 },
893 /*
894 * SBS Technologies, Inc., P-Octal 422
895 */
896 {
897 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
898 .device = PCI_DEVICE_ID_OCTPRO,
899 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
900 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
901 .init = sbs_init,
902 .setup = sbs_setup,
903 .exit = __devexit_p(sbs_exit),
904 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 /*
Russell King61a116e2006-07-03 15:22:35 +0100906 * SIIG cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 */
908 {
909 .vendor = PCI_VENDOR_ID_SIIG,
Russell King67d74b82005-07-27 11:33:03 +0100910 .device = PCI_ANY_ID,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911 .subvendor = PCI_ANY_ID,
912 .subdevice = PCI_ANY_ID,
Russell King67d74b82005-07-27 11:33:03 +0100913 .init = pci_siig_init,
Andrey Panin3ec9c592006-02-02 20:15:09 +0000914 .setup = pci_siig_setup,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700915 },
916 /*
917 * Titan cards
918 */
919 {
920 .vendor = PCI_VENDOR_ID_TITAN,
921 .device = PCI_DEVICE_ID_TITAN_400L,
922 .subvendor = PCI_ANY_ID,
923 .subdevice = PCI_ANY_ID,
924 .setup = titan_400l_800l_setup,
925 },
926 {
927 .vendor = PCI_VENDOR_ID_TITAN,
928 .device = PCI_DEVICE_ID_TITAN_800L,
929 .subvendor = PCI_ANY_ID,
930 .subdevice = PCI_ANY_ID,
931 .setup = titan_400l_800l_setup,
932 },
933 /*
934 * Timedia cards
935 */
936 {
937 .vendor = PCI_VENDOR_ID_TIMEDIA,
938 .device = PCI_DEVICE_ID_TIMEDIA_1889,
939 .subvendor = PCI_VENDOR_ID_TIMEDIA,
940 .subdevice = PCI_ANY_ID,
941 .init = pci_timedia_init,
942 .setup = pci_timedia_setup,
943 },
944 {
945 .vendor = PCI_VENDOR_ID_TIMEDIA,
946 .device = PCI_ANY_ID,
947 .subvendor = PCI_ANY_ID,
948 .subdevice = PCI_ANY_ID,
949 .setup = pci_timedia_setup,
950 },
951 /*
952 * Xircom cards
953 */
954 {
955 .vendor = PCI_VENDOR_ID_XIRCOM,
956 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
959 .init = pci_xircom_init,
960 .setup = pci_default_setup,
961 },
962 /*
Russell King61a116e2006-07-03 15:22:35 +0100963 * Netmos cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964 */
965 {
966 .vendor = PCI_VENDOR_ID_NETMOS,
967 .device = PCI_ANY_ID,
968 .subvendor = PCI_ANY_ID,
969 .subdevice = PCI_ANY_ID,
970 .init = pci_netmos_init,
971 .setup = pci_default_setup,
972 },
973 /*
974 * Default "match everything" terminator entry
975 */
976 {
977 .vendor = PCI_ANY_ID,
978 .device = PCI_ANY_ID,
979 .subvendor = PCI_ANY_ID,
980 .subdevice = PCI_ANY_ID,
981 .setup = pci_default_setup,
982 }
983};
984
985static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
986{
987 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
988}
989
990static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
991{
992 struct pci_serial_quirk *quirk;
993
994 for (quirk = pci_serial_quirks; ; quirk++)
995 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
996 quirk_id_matches(quirk->device, dev->device) &&
997 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
998 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
999 break;
1000 return quirk;
1001}
1002
Andrew Mortondd68e882006-01-05 10:55:26 +00001003static inline int get_pci_irq(struct pci_dev *dev,
1004 struct pciserial_board *board)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005{
1006 if (board->flags & FL_NOIRQ)
1007 return 0;
1008 else
1009 return dev->irq;
1010}
1011
1012/*
1013 * This is the configuration table for all of the PCI serial boards
1014 * which we support. It is directly indexed by the pci_board_num_t enum
1015 * value, which is encoded in the pci_device_id PCI probe table's
1016 * driver_data member.
1017 *
1018 * The makeup of these names are:
Gareth Howlett26e92862006-01-04 17:00:42 +00001019 * pbn_bn{_bt}_n_baud{_offsetinhex}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 *
Gareth Howlett26e92862006-01-04 17:00:42 +00001021 * bn = PCI BAR number
1022 * bt = Index using PCI BARs
1023 * n = number of serial ports
1024 * baud = baud rate
1025 * offsetinhex = offset for each sequential port (in hex)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001026 *
Gareth Howlett26e92862006-01-04 17:00:42 +00001027 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
Russell Kingf1690f32005-05-06 10:19:09 +01001028 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029 * Please note: in theory if n = 1, _bt infix should make no difference.
1030 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1031 */
1032enum pci_board_num_t {
1033 pbn_default = 0,
1034
1035 pbn_b0_1_115200,
1036 pbn_b0_2_115200,
1037 pbn_b0_4_115200,
1038 pbn_b0_5_115200,
Alan Coxbf0df632007-10-16 01:24:00 -07001039 pbn_b0_8_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040
1041 pbn_b0_1_921600,
1042 pbn_b0_2_921600,
1043 pbn_b0_4_921600,
1044
David Ransondb1de152005-07-27 11:43:55 -07001045 pbn_b0_2_1130000,
1046
Andrey Paninfbc0dc02005-07-18 11:38:09 +01001047 pbn_b0_4_1152000,
1048
Gareth Howlett26e92862006-01-04 17:00:42 +00001049 pbn_b0_2_1843200,
1050 pbn_b0_4_1843200,
1051
1052 pbn_b0_2_1843200_200,
1053 pbn_b0_4_1843200_200,
1054 pbn_b0_8_1843200_200,
1055
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056 pbn_b0_bt_1_115200,
1057 pbn_b0_bt_2_115200,
1058 pbn_b0_bt_8_115200,
1059
1060 pbn_b0_bt_1_460800,
1061 pbn_b0_bt_2_460800,
1062 pbn_b0_bt_4_460800,
1063
1064 pbn_b0_bt_1_921600,
1065 pbn_b0_bt_2_921600,
1066 pbn_b0_bt_4_921600,
1067 pbn_b0_bt_8_921600,
1068
1069 pbn_b1_1_115200,
1070 pbn_b1_2_115200,
1071 pbn_b1_4_115200,
1072 pbn_b1_8_115200,
1073
1074 pbn_b1_1_921600,
1075 pbn_b1_2_921600,
1076 pbn_b1_4_921600,
1077 pbn_b1_8_921600,
1078
Gareth Howlett26e92862006-01-04 17:00:42 +00001079 pbn_b1_2_1250000,
1080
Niels de Vos84f8c6f2007-08-22 14:01:14 -07001081 pbn_b1_bt_1_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082 pbn_b1_bt_2_921600,
1083
1084 pbn_b1_1_1382400,
1085 pbn_b1_2_1382400,
1086 pbn_b1_4_1382400,
1087 pbn_b1_8_1382400,
1088
1089 pbn_b2_1_115200,
Peter Horton737c1752006-08-26 09:07:36 +01001090 pbn_b2_2_115200,
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08001091 pbn_b2_4_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001092 pbn_b2_8_115200,
1093
1094 pbn_b2_1_460800,
1095 pbn_b2_4_460800,
1096 pbn_b2_8_460800,
1097 pbn_b2_16_460800,
1098
1099 pbn_b2_1_921600,
1100 pbn_b2_4_921600,
1101 pbn_b2_8_921600,
1102
1103 pbn_b2_bt_1_115200,
1104 pbn_b2_bt_2_115200,
1105 pbn_b2_bt_4_115200,
1106
1107 pbn_b2_bt_2_921600,
1108 pbn_b2_bt_4_921600,
1109
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00001110 pbn_b3_2_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111 pbn_b3_4_115200,
1112 pbn_b3_8_115200,
1113
1114 /*
1115 * Board-specific versions.
1116 */
1117 pbn_panacom,
1118 pbn_panacom2,
1119 pbn_panacom4,
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01001120 pbn_exsys_4055,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121 pbn_plx_romulus,
1122 pbn_oxsemi,
1123 pbn_intel_i960,
1124 pbn_sgi_ioc3,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125 pbn_computone_4,
1126 pbn_computone_6,
1127 pbn_computone_8,
1128 pbn_sbsxrsio,
1129 pbn_exar_XR17C152,
1130 pbn_exar_XR17C154,
1131 pbn_exar_XR17C158,
Olof Johanssonaa798502007-08-22 14:01:55 -07001132 pbn_pasemi_1682M,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001133};
1134
1135/*
1136 * uart_offset - the space between channels
1137 * reg_shift - describes how the UART registers are mapped
1138 * to PCI memory by the card.
1139 * For example IER register on SBS, Inc. PMC-OctPro is located at
1140 * offset 0x10 from the UART base, while UART_IER is defined as 1
1141 * in include/linux/serial_reg.h,
1142 * see first lines of serial_in() and serial_out() in 8250.c
1143*/
1144
Russell King1c7c1fe2005-07-27 11:31:19 +01001145static struct pciserial_board pci_boards[] __devinitdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 [pbn_default] = {
1147 .flags = FL_BASE0,
1148 .num_ports = 1,
1149 .base_baud = 115200,
1150 .uart_offset = 8,
1151 },
1152 [pbn_b0_1_115200] = {
1153 .flags = FL_BASE0,
1154 .num_ports = 1,
1155 .base_baud = 115200,
1156 .uart_offset = 8,
1157 },
1158 [pbn_b0_2_115200] = {
1159 .flags = FL_BASE0,
1160 .num_ports = 2,
1161 .base_baud = 115200,
1162 .uart_offset = 8,
1163 },
1164 [pbn_b0_4_115200] = {
1165 .flags = FL_BASE0,
1166 .num_ports = 4,
1167 .base_baud = 115200,
1168 .uart_offset = 8,
1169 },
1170 [pbn_b0_5_115200] = {
1171 .flags = FL_BASE0,
1172 .num_ports = 5,
1173 .base_baud = 115200,
1174 .uart_offset = 8,
1175 },
Alan Coxbf0df632007-10-16 01:24:00 -07001176 [pbn_b0_8_115200] = {
1177 .flags = FL_BASE0,
1178 .num_ports = 8,
1179 .base_baud = 115200,
1180 .uart_offset = 8,
1181 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182
1183 [pbn_b0_1_921600] = {
1184 .flags = FL_BASE0,
1185 .num_ports = 1,
1186 .base_baud = 921600,
1187 .uart_offset = 8,
1188 },
1189 [pbn_b0_2_921600] = {
1190 .flags = FL_BASE0,
1191 .num_ports = 2,
1192 .base_baud = 921600,
1193 .uart_offset = 8,
1194 },
1195 [pbn_b0_4_921600] = {
1196 .flags = FL_BASE0,
1197 .num_ports = 4,
1198 .base_baud = 921600,
1199 .uart_offset = 8,
1200 },
David Ransondb1de152005-07-27 11:43:55 -07001201
1202 [pbn_b0_2_1130000] = {
1203 .flags = FL_BASE0,
1204 .num_ports = 2,
1205 .base_baud = 1130000,
1206 .uart_offset = 8,
1207 },
1208
Andrey Paninfbc0dc02005-07-18 11:38:09 +01001209 [pbn_b0_4_1152000] = {
1210 .flags = FL_BASE0,
1211 .num_ports = 4,
1212 .base_baud = 1152000,
1213 .uart_offset = 8,
1214 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215
Gareth Howlett26e92862006-01-04 17:00:42 +00001216 [pbn_b0_2_1843200] = {
1217 .flags = FL_BASE0,
1218 .num_ports = 2,
1219 .base_baud = 1843200,
1220 .uart_offset = 8,
1221 },
1222 [pbn_b0_4_1843200] = {
1223 .flags = FL_BASE0,
1224 .num_ports = 4,
1225 .base_baud = 1843200,
1226 .uart_offset = 8,
1227 },
1228
1229 [pbn_b0_2_1843200_200] = {
1230 .flags = FL_BASE0,
1231 .num_ports = 2,
1232 .base_baud = 1843200,
1233 .uart_offset = 0x200,
1234 },
1235 [pbn_b0_4_1843200_200] = {
1236 .flags = FL_BASE0,
1237 .num_ports = 4,
1238 .base_baud = 1843200,
1239 .uart_offset = 0x200,
1240 },
1241 [pbn_b0_8_1843200_200] = {
1242 .flags = FL_BASE0,
1243 .num_ports = 8,
1244 .base_baud = 1843200,
1245 .uart_offset = 0x200,
1246 },
1247
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248 [pbn_b0_bt_1_115200] = {
1249 .flags = FL_BASE0|FL_BASE_BARS,
1250 .num_ports = 1,
1251 .base_baud = 115200,
1252 .uart_offset = 8,
1253 },
1254 [pbn_b0_bt_2_115200] = {
1255 .flags = FL_BASE0|FL_BASE_BARS,
1256 .num_ports = 2,
1257 .base_baud = 115200,
1258 .uart_offset = 8,
1259 },
1260 [pbn_b0_bt_8_115200] = {
1261 .flags = FL_BASE0|FL_BASE_BARS,
1262 .num_ports = 8,
1263 .base_baud = 115200,
1264 .uart_offset = 8,
1265 },
1266
1267 [pbn_b0_bt_1_460800] = {
1268 .flags = FL_BASE0|FL_BASE_BARS,
1269 .num_ports = 1,
1270 .base_baud = 460800,
1271 .uart_offset = 8,
1272 },
1273 [pbn_b0_bt_2_460800] = {
1274 .flags = FL_BASE0|FL_BASE_BARS,
1275 .num_ports = 2,
1276 .base_baud = 460800,
1277 .uart_offset = 8,
1278 },
1279 [pbn_b0_bt_4_460800] = {
1280 .flags = FL_BASE0|FL_BASE_BARS,
1281 .num_ports = 4,
1282 .base_baud = 460800,
1283 .uart_offset = 8,
1284 },
1285
1286 [pbn_b0_bt_1_921600] = {
1287 .flags = FL_BASE0|FL_BASE_BARS,
1288 .num_ports = 1,
1289 .base_baud = 921600,
1290 .uart_offset = 8,
1291 },
1292 [pbn_b0_bt_2_921600] = {
1293 .flags = FL_BASE0|FL_BASE_BARS,
1294 .num_ports = 2,
1295 .base_baud = 921600,
1296 .uart_offset = 8,
1297 },
1298 [pbn_b0_bt_4_921600] = {
1299 .flags = FL_BASE0|FL_BASE_BARS,
1300 .num_ports = 4,
1301 .base_baud = 921600,
1302 .uart_offset = 8,
1303 },
1304 [pbn_b0_bt_8_921600] = {
1305 .flags = FL_BASE0|FL_BASE_BARS,
1306 .num_ports = 8,
1307 .base_baud = 921600,
1308 .uart_offset = 8,
1309 },
1310
1311 [pbn_b1_1_115200] = {
1312 .flags = FL_BASE1,
1313 .num_ports = 1,
1314 .base_baud = 115200,
1315 .uart_offset = 8,
1316 },
1317 [pbn_b1_2_115200] = {
1318 .flags = FL_BASE1,
1319 .num_ports = 2,
1320 .base_baud = 115200,
1321 .uart_offset = 8,
1322 },
1323 [pbn_b1_4_115200] = {
1324 .flags = FL_BASE1,
1325 .num_ports = 4,
1326 .base_baud = 115200,
1327 .uart_offset = 8,
1328 },
1329 [pbn_b1_8_115200] = {
1330 .flags = FL_BASE1,
1331 .num_ports = 8,
1332 .base_baud = 115200,
1333 .uart_offset = 8,
1334 },
1335
1336 [pbn_b1_1_921600] = {
1337 .flags = FL_BASE1,
1338 .num_ports = 1,
1339 .base_baud = 921600,
1340 .uart_offset = 8,
1341 },
1342 [pbn_b1_2_921600] = {
1343 .flags = FL_BASE1,
1344 .num_ports = 2,
1345 .base_baud = 921600,
1346 .uart_offset = 8,
1347 },
1348 [pbn_b1_4_921600] = {
1349 .flags = FL_BASE1,
1350 .num_ports = 4,
1351 .base_baud = 921600,
1352 .uart_offset = 8,
1353 },
1354 [pbn_b1_8_921600] = {
1355 .flags = FL_BASE1,
1356 .num_ports = 8,
1357 .base_baud = 921600,
1358 .uart_offset = 8,
1359 },
Gareth Howlett26e92862006-01-04 17:00:42 +00001360 [pbn_b1_2_1250000] = {
1361 .flags = FL_BASE1,
1362 .num_ports = 2,
1363 .base_baud = 1250000,
1364 .uart_offset = 8,
1365 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366
Niels de Vos84f8c6f2007-08-22 14:01:14 -07001367 [pbn_b1_bt_1_115200] = {
1368 .flags = FL_BASE1|FL_BASE_BARS,
1369 .num_ports = 1,
1370 .base_baud = 115200,
1371 .uart_offset = 8,
1372 },
1373
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 [pbn_b1_bt_2_921600] = {
1375 .flags = FL_BASE1|FL_BASE_BARS,
1376 .num_ports = 2,
1377 .base_baud = 921600,
1378 .uart_offset = 8,
1379 },
1380
1381 [pbn_b1_1_1382400] = {
1382 .flags = FL_BASE1,
1383 .num_ports = 1,
1384 .base_baud = 1382400,
1385 .uart_offset = 8,
1386 },
1387 [pbn_b1_2_1382400] = {
1388 .flags = FL_BASE1,
1389 .num_ports = 2,
1390 .base_baud = 1382400,
1391 .uart_offset = 8,
1392 },
1393 [pbn_b1_4_1382400] = {
1394 .flags = FL_BASE1,
1395 .num_ports = 4,
1396 .base_baud = 1382400,
1397 .uart_offset = 8,
1398 },
1399 [pbn_b1_8_1382400] = {
1400 .flags = FL_BASE1,
1401 .num_ports = 8,
1402 .base_baud = 1382400,
1403 .uart_offset = 8,
1404 },
1405
1406 [pbn_b2_1_115200] = {
1407 .flags = FL_BASE2,
1408 .num_ports = 1,
1409 .base_baud = 115200,
1410 .uart_offset = 8,
1411 },
Peter Horton737c1752006-08-26 09:07:36 +01001412 [pbn_b2_2_115200] = {
1413 .flags = FL_BASE2,
1414 .num_ports = 2,
1415 .base_baud = 115200,
1416 .uart_offset = 8,
1417 },
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08001418 [pbn_b2_4_115200] = {
1419 .flags = FL_BASE2,
1420 .num_ports = 4,
1421 .base_baud = 115200,
1422 .uart_offset = 8,
1423 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424 [pbn_b2_8_115200] = {
1425 .flags = FL_BASE2,
1426 .num_ports = 8,
1427 .base_baud = 115200,
1428 .uart_offset = 8,
1429 },
1430
1431 [pbn_b2_1_460800] = {
1432 .flags = FL_BASE2,
1433 .num_ports = 1,
1434 .base_baud = 460800,
1435 .uart_offset = 8,
1436 },
1437 [pbn_b2_4_460800] = {
1438 .flags = FL_BASE2,
1439 .num_ports = 4,
1440 .base_baud = 460800,
1441 .uart_offset = 8,
1442 },
1443 [pbn_b2_8_460800] = {
1444 .flags = FL_BASE2,
1445 .num_ports = 8,
1446 .base_baud = 460800,
1447 .uart_offset = 8,
1448 },
1449 [pbn_b2_16_460800] = {
1450 .flags = FL_BASE2,
1451 .num_ports = 16,
1452 .base_baud = 460800,
1453 .uart_offset = 8,
1454 },
1455
1456 [pbn_b2_1_921600] = {
1457 .flags = FL_BASE2,
1458 .num_ports = 1,
1459 .base_baud = 921600,
1460 .uart_offset = 8,
1461 },
1462 [pbn_b2_4_921600] = {
1463 .flags = FL_BASE2,
1464 .num_ports = 4,
1465 .base_baud = 921600,
1466 .uart_offset = 8,
1467 },
1468 [pbn_b2_8_921600] = {
1469 .flags = FL_BASE2,
1470 .num_ports = 8,
1471 .base_baud = 921600,
1472 .uart_offset = 8,
1473 },
1474
1475 [pbn_b2_bt_1_115200] = {
1476 .flags = FL_BASE2|FL_BASE_BARS,
1477 .num_ports = 1,
1478 .base_baud = 115200,
1479 .uart_offset = 8,
1480 },
1481 [pbn_b2_bt_2_115200] = {
1482 .flags = FL_BASE2|FL_BASE_BARS,
1483 .num_ports = 2,
1484 .base_baud = 115200,
1485 .uart_offset = 8,
1486 },
1487 [pbn_b2_bt_4_115200] = {
1488 .flags = FL_BASE2|FL_BASE_BARS,
1489 .num_ports = 4,
1490 .base_baud = 115200,
1491 .uart_offset = 8,
1492 },
1493
1494 [pbn_b2_bt_2_921600] = {
1495 .flags = FL_BASE2|FL_BASE_BARS,
1496 .num_ports = 2,
1497 .base_baud = 921600,
1498 .uart_offset = 8,
1499 },
1500 [pbn_b2_bt_4_921600] = {
1501 .flags = FL_BASE2|FL_BASE_BARS,
1502 .num_ports = 4,
1503 .base_baud = 921600,
1504 .uart_offset = 8,
1505 },
1506
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00001507 [pbn_b3_2_115200] = {
1508 .flags = FL_BASE3,
1509 .num_ports = 2,
1510 .base_baud = 115200,
1511 .uart_offset = 8,
1512 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001513 [pbn_b3_4_115200] = {
1514 .flags = FL_BASE3,
1515 .num_ports = 4,
1516 .base_baud = 115200,
1517 .uart_offset = 8,
1518 },
1519 [pbn_b3_8_115200] = {
1520 .flags = FL_BASE3,
1521 .num_ports = 8,
1522 .base_baud = 115200,
1523 .uart_offset = 8,
1524 },
1525
1526 /*
1527 * Entries following this are board-specific.
1528 */
1529
1530 /*
1531 * Panacom - IOMEM
1532 */
1533 [pbn_panacom] = {
1534 .flags = FL_BASE2,
1535 .num_ports = 2,
1536 .base_baud = 921600,
1537 .uart_offset = 0x400,
1538 .reg_shift = 7,
1539 },
1540 [pbn_panacom2] = {
1541 .flags = FL_BASE2|FL_BASE_BARS,
1542 .num_ports = 2,
1543 .base_baud = 921600,
1544 .uart_offset = 0x400,
1545 .reg_shift = 7,
1546 },
1547 [pbn_panacom4] = {
1548 .flags = FL_BASE2|FL_BASE_BARS,
1549 .num_ports = 4,
1550 .base_baud = 921600,
1551 .uart_offset = 0x400,
1552 .reg_shift = 7,
1553 },
1554
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01001555 [pbn_exsys_4055] = {
1556 .flags = FL_BASE2,
1557 .num_ports = 4,
1558 .base_baud = 115200,
1559 .uart_offset = 8,
1560 },
1561
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562 /* I think this entry is broken - the first_offset looks wrong --rmk */
1563 [pbn_plx_romulus] = {
1564 .flags = FL_BASE2,
1565 .num_ports = 4,
1566 .base_baud = 921600,
1567 .uart_offset = 8 << 2,
1568 .reg_shift = 2,
1569 .first_offset = 0x03,
1570 },
1571
1572 /*
1573 * This board uses the size of PCI Base region 0 to
1574 * signal now many ports are available
1575 */
1576 [pbn_oxsemi] = {
1577 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1578 .num_ports = 32,
1579 .base_baud = 115200,
1580 .uart_offset = 8,
1581 },
1582
1583 /*
1584 * EKF addition for i960 Boards form EKF with serial port.
1585 * Max 256 ports.
1586 */
1587 [pbn_intel_i960] = {
1588 .flags = FL_BASE0,
1589 .num_ports = 32,
1590 .base_baud = 921600,
1591 .uart_offset = 8 << 2,
1592 .reg_shift = 2,
1593 .first_offset = 0x10000,
1594 },
1595 [pbn_sgi_ioc3] = {
1596 .flags = FL_BASE0|FL_NOIRQ,
1597 .num_ports = 1,
1598 .base_baud = 458333,
1599 .uart_offset = 8,
1600 .reg_shift = 0,
1601 .first_offset = 0x20178,
1602 },
1603
1604 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001605 * Computone - uses IOMEM.
1606 */
1607 [pbn_computone_4] = {
1608 .flags = FL_BASE0,
1609 .num_ports = 4,
1610 .base_baud = 921600,
1611 .uart_offset = 0x40,
1612 .reg_shift = 2,
1613 .first_offset = 0x200,
1614 },
1615 [pbn_computone_6] = {
1616 .flags = FL_BASE0,
1617 .num_ports = 6,
1618 .base_baud = 921600,
1619 .uart_offset = 0x40,
1620 .reg_shift = 2,
1621 .first_offset = 0x200,
1622 },
1623 [pbn_computone_8] = {
1624 .flags = FL_BASE0,
1625 .num_ports = 8,
1626 .base_baud = 921600,
1627 .uart_offset = 0x40,
1628 .reg_shift = 2,
1629 .first_offset = 0x200,
1630 },
1631 [pbn_sbsxrsio] = {
1632 .flags = FL_BASE0,
1633 .num_ports = 8,
1634 .base_baud = 460800,
1635 .uart_offset = 256,
1636 .reg_shift = 4,
1637 },
1638 /*
1639 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1640 * Only basic 16550A support.
1641 * XR17C15[24] are not tested, but they should work.
1642 */
1643 [pbn_exar_XR17C152] = {
1644 .flags = FL_BASE0,
1645 .num_ports = 2,
1646 .base_baud = 921600,
1647 .uart_offset = 0x200,
1648 },
1649 [pbn_exar_XR17C154] = {
1650 .flags = FL_BASE0,
1651 .num_ports = 4,
1652 .base_baud = 921600,
1653 .uart_offset = 0x200,
1654 },
1655 [pbn_exar_XR17C158] = {
1656 .flags = FL_BASE0,
1657 .num_ports = 8,
1658 .base_baud = 921600,
1659 .uart_offset = 0x200,
1660 },
Olof Johanssonaa798502007-08-22 14:01:55 -07001661 /*
1662 * PA Semi PWRficient PA6T-1682M on-chip UART
1663 */
1664 [pbn_pasemi_1682M] = {
1665 .flags = FL_BASE0,
1666 .num_ports = 1,
1667 .base_baud = 8333333,
1668 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669};
1670
Christian Schmidt436bbd42007-08-22 14:01:19 -07001671static const struct pci_device_id softmodem_blacklist[] = {
1672 { PCI_VDEVICE ( AL, 0x5457 ), }, /* ALi Corporation M5457 AC'97 Modem */
1673};
1674
Linus Torvalds1da177e2005-04-16 15:20:36 -07001675/*
1676 * Given a complete unknown PCI device, try to use some heuristics to
1677 * guess what the configuration might be, based on the pitiful PCI
1678 * serial specs. Returns 0 on success, 1 on failure.
1679 */
1680static int __devinit
Russell King1c7c1fe2005-07-27 11:31:19 +01001681serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682{
Christian Schmidt436bbd42007-08-22 14:01:19 -07001683 const struct pci_device_id *blacklist;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684 int num_iomem, num_port, first_port = -1, i;
1685
1686 /*
1687 * If it is not a communications device or the programming
1688 * interface is greater than 6, give up.
1689 *
1690 * (Should we try to make guesses for multiport serial devices
1691 * later?)
1692 */
1693 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1694 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1695 (dev->class & 0xff) > 6)
1696 return -ENODEV;
1697
Christian Schmidt436bbd42007-08-22 14:01:19 -07001698 /*
1699 * Do not access blacklisted devices that are known not to
1700 * feature serial ports.
1701 */
1702 for (blacklist = softmodem_blacklist;
1703 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1704 blacklist++) {
1705 if (dev->vendor == blacklist->vendor &&
1706 dev->device == blacklist->device)
1707 return -ENODEV;
1708 }
1709
Linus Torvalds1da177e2005-04-16 15:20:36 -07001710 num_iomem = num_port = 0;
1711 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1712 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1713 num_port++;
1714 if (first_port == -1)
1715 first_port = i;
1716 }
1717 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1718 num_iomem++;
1719 }
1720
1721 /*
1722 * If there is 1 or 0 iomem regions, and exactly one port,
1723 * use it. We guess the number of ports based on the IO
1724 * region size.
1725 */
1726 if (num_iomem <= 1 && num_port == 1) {
1727 board->flags = first_port;
1728 board->num_ports = pci_resource_len(dev, first_port) / 8;
1729 return 0;
1730 }
1731
1732 /*
1733 * Now guess if we've got a board which indexes by BARs.
1734 * Each IO BAR should be 8 bytes, and they should follow
1735 * consecutively.
1736 */
1737 first_port = -1;
1738 num_port = 0;
1739 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1740 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1741 pci_resource_len(dev, i) == 8 &&
1742 (first_port == -1 || (first_port + num_port) == i)) {
1743 num_port++;
1744 if (first_port == -1)
1745 first_port = i;
1746 }
1747 }
1748
1749 if (num_port > 1) {
1750 board->flags = first_port | FL_BASE_BARS;
1751 board->num_ports = num_port;
1752 return 0;
1753 }
1754
1755 return -ENODEV;
1756}
1757
1758static inline int
Russell King1c7c1fe2005-07-27 11:31:19 +01001759serial_pci_matches(struct pciserial_board *board,
1760 struct pciserial_board *guessed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761{
1762 return
1763 board->num_ports == guessed->num_ports &&
1764 board->base_baud == guessed->base_baud &&
1765 board->uart_offset == guessed->uart_offset &&
1766 board->reg_shift == guessed->reg_shift &&
1767 board->first_offset == guessed->first_offset;
1768}
1769
Russell King241fc432005-07-27 11:35:54 +01001770struct serial_private *
1771pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1772{
1773 struct uart_port serial_port;
1774 struct serial_private *priv;
1775 struct pci_serial_quirk *quirk;
1776 int rc, nr_ports, i;
1777
1778 nr_ports = board->num_ports;
1779
1780 /*
1781 * Find an init and setup quirks.
1782 */
1783 quirk = find_quirk(dev);
1784
1785 /*
1786 * Run the new-style initialization function.
1787 * The initialization function returns:
1788 * <0 - error
1789 * 0 - use board->num_ports
1790 * >0 - number of ports
1791 */
1792 if (quirk->init) {
1793 rc = quirk->init(dev);
1794 if (rc < 0) {
1795 priv = ERR_PTR(rc);
1796 goto err_out;
1797 }
1798 if (rc)
1799 nr_ports = rc;
1800 }
1801
Burman Yan8f31bb32007-02-14 00:33:07 -08001802 priv = kzalloc(sizeof(struct serial_private) +
Russell King241fc432005-07-27 11:35:54 +01001803 sizeof(unsigned int) * nr_ports,
1804 GFP_KERNEL);
1805 if (!priv) {
1806 priv = ERR_PTR(-ENOMEM);
1807 goto err_deinit;
1808 }
1809
Russell King241fc432005-07-27 11:35:54 +01001810 priv->dev = dev;
1811 priv->quirk = quirk;
1812
1813 memset(&serial_port, 0, sizeof(struct uart_port));
1814 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1815 serial_port.uartclk = board->base_baud * 16;
1816 serial_port.irq = get_pci_irq(dev, board);
1817 serial_port.dev = &dev->dev;
1818
1819 for (i = 0; i < nr_ports; i++) {
1820 if (quirk->setup(priv, board, &serial_port, i))
1821 break;
1822
1823#ifdef SERIAL_DEBUG_PCI
1824 printk("Setup PCI port: port %x, irq %d, type %d\n",
1825 serial_port.iobase, serial_port.irq, serial_port.iotype);
1826#endif
1827
1828 priv->line[i] = serial8250_register_port(&serial_port);
1829 if (priv->line[i] < 0) {
1830 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1831 break;
1832 }
1833 }
1834
1835 priv->nr = i;
1836
1837 return priv;
1838
1839 err_deinit:
1840 if (quirk->exit)
1841 quirk->exit(dev);
1842 err_out:
1843 return priv;
1844}
1845EXPORT_SYMBOL_GPL(pciserial_init_ports);
1846
1847void pciserial_remove_ports(struct serial_private *priv)
1848{
1849 struct pci_serial_quirk *quirk;
1850 int i;
1851
1852 for (i = 0; i < priv->nr; i++)
1853 serial8250_unregister_port(priv->line[i]);
1854
1855 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1856 if (priv->remapped_bar[i])
1857 iounmap(priv->remapped_bar[i]);
1858 priv->remapped_bar[i] = NULL;
1859 }
1860
1861 /*
1862 * Find the exit quirks.
1863 */
1864 quirk = find_quirk(priv->dev);
1865 if (quirk->exit)
1866 quirk->exit(priv->dev);
1867
1868 kfree(priv);
1869}
1870EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1871
1872void pciserial_suspend_ports(struct serial_private *priv)
1873{
1874 int i;
1875
1876 for (i = 0; i < priv->nr; i++)
1877 if (priv->line[i] >= 0)
1878 serial8250_suspend_port(priv->line[i]);
1879}
1880EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1881
1882void pciserial_resume_ports(struct serial_private *priv)
1883{
1884 int i;
1885
1886 /*
1887 * Ensure that the board is correctly configured.
1888 */
1889 if (priv->quirk->init)
1890 priv->quirk->init(priv->dev);
1891
1892 for (i = 0; i < priv->nr; i++)
1893 if (priv->line[i] >= 0)
1894 serial8250_resume_port(priv->line[i]);
1895}
1896EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1897
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898/*
1899 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1900 * to the arrangement of serial ports on a PCI card.
1901 */
1902static int __devinit
1903pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1904{
1905 struct serial_private *priv;
Russell King1c7c1fe2005-07-27 11:31:19 +01001906 struct pciserial_board *board, tmp;
Russell King241fc432005-07-27 11:35:54 +01001907 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001908
1909 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1910 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1911 ent->driver_data);
1912 return -EINVAL;
1913 }
1914
1915 board = &pci_boards[ent->driver_data];
1916
1917 rc = pci_enable_device(dev);
1918 if (rc)
1919 return rc;
1920
1921 if (ent->driver_data == pbn_default) {
1922 /*
1923 * Use a copy of the pci_board entry for this;
1924 * avoid changing entries in the table.
1925 */
Russell King1c7c1fe2005-07-27 11:31:19 +01001926 memcpy(&tmp, board, sizeof(struct pciserial_board));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927 board = &tmp;
1928
1929 /*
1930 * We matched one of our class entries. Try to
1931 * determine the parameters of this board.
1932 */
1933 rc = serial_pci_guess_board(dev, board);
1934 if (rc)
1935 goto disable;
1936 } else {
1937 /*
1938 * We matched an explicit entry. If we are able to
1939 * detect this boards settings with our heuristic,
1940 * then we no longer need this entry.
1941 */
Russell King1c7c1fe2005-07-27 11:31:19 +01001942 memcpy(&tmp, &pci_boards[pbn_default],
1943 sizeof(struct pciserial_board));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001944 rc = serial_pci_guess_board(dev, &tmp);
1945 if (rc == 0 && serial_pci_matches(board, &tmp))
1946 moan_device("Redundant entry in serial pci_table.",
1947 dev);
1948 }
1949
Russell King241fc432005-07-27 11:35:54 +01001950 priv = pciserial_init_ports(dev, board);
1951 if (!IS_ERR(priv)) {
1952 pci_set_drvdata(dev, priv);
1953 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954 }
1955
Russell King241fc432005-07-27 11:35:54 +01001956 rc = PTR_ERR(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001957
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958 disable:
1959 pci_disable_device(dev);
1960 return rc;
1961}
1962
1963static void __devexit pciserial_remove_one(struct pci_dev *dev)
1964{
1965 struct serial_private *priv = pci_get_drvdata(dev);
1966
1967 pci_set_drvdata(dev, NULL);
1968
Russell King241fc432005-07-27 11:35:54 +01001969 pciserial_remove_ports(priv);
Russell King056a8762005-07-22 10:15:04 +01001970
1971 pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001972}
1973
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07001974#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07001975static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1976{
1977 struct serial_private *priv = pci_get_drvdata(dev);
1978
Russell King241fc432005-07-27 11:35:54 +01001979 if (priv)
1980 pciserial_suspend_ports(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001981
Linus Torvalds1da177e2005-04-16 15:20:36 -07001982 pci_save_state(dev);
1983 pci_set_power_state(dev, pci_choose_state(dev, state));
1984 return 0;
1985}
1986
1987static int pciserial_resume_one(struct pci_dev *dev)
1988{
Dirk Hohndelccb9d592007-10-29 06:28:17 -07001989 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001990 struct serial_private *priv = pci_get_drvdata(dev);
1991
1992 pci_set_power_state(dev, PCI_D0);
1993 pci_restore_state(dev);
1994
1995 if (priv) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001996 /*
1997 * The device may have been disabled. Re-enable it.
1998 */
Dirk Hohndelccb9d592007-10-29 06:28:17 -07001999 err = pci_enable_device(dev);
2000 if (err)
2001 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002002
Russell King241fc432005-07-27 11:35:54 +01002003 pciserial_resume_ports(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002004 }
2005 return 0;
2006}
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002007#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002008
2009static struct pci_device_id serial_pci_tbl[] = {
2010 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2011 PCI_SUBVENDOR_ID_CONNECT_TECH,
2012 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2013 pbn_b1_8_1382400 },
2014 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2015 PCI_SUBVENDOR_ID_CONNECT_TECH,
2016 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2017 pbn_b1_4_1382400 },
2018 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2019 PCI_SUBVENDOR_ID_CONNECT_TECH,
2020 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2021 pbn_b1_2_1382400 },
2022 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2023 PCI_SUBVENDOR_ID_CONNECT_TECH,
2024 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2025 pbn_b1_8_1382400 },
2026 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2027 PCI_SUBVENDOR_ID_CONNECT_TECH,
2028 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2029 pbn_b1_4_1382400 },
2030 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2031 PCI_SUBVENDOR_ID_CONNECT_TECH,
2032 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2033 pbn_b1_2_1382400 },
2034 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2035 PCI_SUBVENDOR_ID_CONNECT_TECH,
2036 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2037 pbn_b1_8_921600 },
2038 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2039 PCI_SUBVENDOR_ID_CONNECT_TECH,
2040 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2041 pbn_b1_8_921600 },
2042 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2043 PCI_SUBVENDOR_ID_CONNECT_TECH,
2044 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2045 pbn_b1_4_921600 },
2046 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2047 PCI_SUBVENDOR_ID_CONNECT_TECH,
2048 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2049 pbn_b1_4_921600 },
2050 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2051 PCI_SUBVENDOR_ID_CONNECT_TECH,
2052 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2053 pbn_b1_2_921600 },
2054 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2055 PCI_SUBVENDOR_ID_CONNECT_TECH,
2056 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2057 pbn_b1_8_921600 },
2058 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2059 PCI_SUBVENDOR_ID_CONNECT_TECH,
2060 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2061 pbn_b1_8_921600 },
2062 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2063 PCI_SUBVENDOR_ID_CONNECT_TECH,
2064 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2065 pbn_b1_4_921600 },
Gareth Howlett26e92862006-01-04 17:00:42 +00002066 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2067 PCI_SUBVENDOR_ID_CONNECT_TECH,
2068 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2069 pbn_b1_2_1250000 },
2070 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2071 PCI_SUBVENDOR_ID_CONNECT_TECH,
2072 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2073 pbn_b0_2_1843200 },
2074 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2075 PCI_SUBVENDOR_ID_CONNECT_TECH,
2076 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2077 pbn_b0_4_1843200 },
Yoichi Yuasa85d14942006-02-08 21:46:24 +00002078 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2079 PCI_VENDOR_ID_AFAVLAB,
2080 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2081 pbn_b0_4_1152000 },
Gareth Howlett26e92862006-01-04 17:00:42 +00002082 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2083 PCI_SUBVENDOR_ID_CONNECT_TECH,
2084 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2085 pbn_b0_2_1843200_200 },
2086 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2087 PCI_SUBVENDOR_ID_CONNECT_TECH,
2088 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2089 pbn_b0_4_1843200_200 },
2090 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2091 PCI_SUBVENDOR_ID_CONNECT_TECH,
2092 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2093 pbn_b0_8_1843200_200 },
2094 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2095 PCI_SUBVENDOR_ID_CONNECT_TECH,
2096 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2097 pbn_b0_2_1843200_200 },
2098 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2099 PCI_SUBVENDOR_ID_CONNECT_TECH,
2100 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2101 pbn_b0_4_1843200_200 },
2102 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2103 PCI_SUBVENDOR_ID_CONNECT_TECH,
2104 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2105 pbn_b0_8_1843200_200 },
2106 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2107 PCI_SUBVENDOR_ID_CONNECT_TECH,
2108 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2109 pbn_b0_2_1843200_200 },
2110 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2111 PCI_SUBVENDOR_ID_CONNECT_TECH,
2112 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2113 pbn_b0_4_1843200_200 },
2114 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2115 PCI_SUBVENDOR_ID_CONNECT_TECH,
2116 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2117 pbn_b0_8_1843200_200 },
2118 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2119 PCI_SUBVENDOR_ID_CONNECT_TECH,
2120 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2121 pbn_b0_2_1843200_200 },
2122 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2123 PCI_SUBVENDOR_ID_CONNECT_TECH,
2124 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2125 pbn_b0_4_1843200_200 },
2126 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2127 PCI_SUBVENDOR_ID_CONNECT_TECH,
2128 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2129 pbn_b0_8_1843200_200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002130
2131 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2133 pbn_b2_bt_1_115200 },
2134 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2136 pbn_b2_bt_2_115200 },
2137 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2139 pbn_b2_bt_4_115200 },
2140 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2142 pbn_b2_bt_2_115200 },
2143 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145 pbn_b2_bt_4_115200 },
2146 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148 pbn_b2_8_115200 },
2149 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151 pbn_b2_8_115200 },
2152
2153 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2155 pbn_b2_bt_2_115200 },
2156 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2158 pbn_b2_bt_2_921600 },
2159 /*
2160 * VScom SPCOM800, from sl@s.pl
2161 */
2162 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2164 pbn_b2_8_921600 },
2165 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2167 pbn_b2_4_921600 },
2168 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2169 PCI_SUBVENDOR_ID_KEYSPAN,
2170 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2171 pbn_panacom },
2172 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2174 pbn_panacom4 },
2175 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2177 pbn_panacom2 },
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08002178 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2179 PCI_VENDOR_ID_ESDGMBH,
2180 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2181 pbn_b2_4_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002182 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2183 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2184 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2185 pbn_b2_4_460800 },
2186 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2187 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2188 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2189 pbn_b2_8_460800 },
2190 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2191 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2192 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2193 pbn_b2_16_460800 },
2194 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2195 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2196 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2197 pbn_b2_16_460800 },
2198 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2199 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2200 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2201 pbn_b2_4_460800 },
2202 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2203 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2204 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2205 pbn_b2_8_460800 },
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01002206 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2207 PCI_SUBVENDOR_ID_EXSYS,
2208 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2209 pbn_exsys_4055 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002210 /*
2211 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2212 * (Exoray@isys.ca)
2213 */
2214 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2215 0x10b5, 0x106a, 0, 0,
2216 pbn_plx_romulus },
2217 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2219 pbn_b1_4_115200 },
2220 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2222 pbn_b1_2_115200 },
2223 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2225 pbn_b1_8_115200 },
2226 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2228 pbn_b1_8_115200 },
2229 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2230 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2231 pbn_b0_4_921600 },
2232 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
Andrey Paninfbc0dc02005-07-18 11:38:09 +01002233 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2234 pbn_b0_4_1152000 },
David Ransondb1de152005-07-27 11:43:55 -07002235
2236 /*
2237 * The below card is a little controversial since it is the
2238 * subject of a PCI vendor/device ID clash. (See
2239 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2240 * For now just used the hex ID 0x950a.
2241 */
2242 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2244 pbn_b0_2_1130000 },
Andrey Paninfbc0dc02005-07-18 11:38:09 +01002245 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2247 pbn_b0_4_115200 },
2248 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2250 pbn_b0_bt_2_921600 },
2251
2252 /*
2253 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2254 * from skokodyn@yahoo.com
2255 */
2256 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2257 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2258 pbn_sbsxrsio },
2259 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2260 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2261 pbn_sbsxrsio },
2262 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2263 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2264 pbn_sbsxrsio },
2265 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2266 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2267 pbn_sbsxrsio },
2268
2269 /*
2270 * Digitan DS560-558, from jimd@esoft.com
2271 */
2272 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2274 pbn_b1_1_115200 },
2275
2276 /*
2277 * Titan Electronic cards
2278 * The 400L and 800L have a custom setup quirk.
2279 */
2280 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2282 pbn_b0_1_921600 },
2283 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2285 pbn_b0_2_921600 },
2286 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2288 pbn_b0_4_921600 },
2289 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2291 pbn_b0_4_921600 },
2292 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2294 pbn_b1_1_921600 },
2295 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2297 pbn_b1_bt_2_921600 },
2298 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2300 pbn_b0_bt_4_921600 },
2301 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2303 pbn_b0_bt_8_921600 },
2304
2305 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2307 pbn_b2_1_460800 },
2308 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2310 pbn_b2_1_460800 },
2311 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2313 pbn_b2_1_460800 },
2314 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2316 pbn_b2_bt_2_921600 },
2317 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2319 pbn_b2_bt_2_921600 },
2320 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2322 pbn_b2_bt_2_921600 },
2323 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2325 pbn_b2_bt_4_921600 },
2326 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2328 pbn_b2_bt_4_921600 },
2329 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2331 pbn_b2_bt_4_921600 },
2332 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2334 pbn_b0_1_921600 },
2335 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2337 pbn_b0_1_921600 },
2338 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2340 pbn_b0_1_921600 },
2341 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2343 pbn_b0_bt_2_921600 },
2344 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2346 pbn_b0_bt_2_921600 },
2347 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2349 pbn_b0_bt_2_921600 },
2350 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2352 pbn_b0_bt_4_921600 },
2353 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2355 pbn_b0_bt_4_921600 },
2356 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2358 pbn_b0_bt_4_921600 },
Andrey Panin3ec9c592006-02-02 20:15:09 +00002359 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2361 pbn_b0_bt_8_921600 },
2362 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2364 pbn_b0_bt_8_921600 },
2365 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2367 pbn_b0_bt_8_921600 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002368
2369 /*
2370 * Computone devices submitted by Doug McNash dmcnash@computone.com
2371 */
2372 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2373 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2374 0, 0, pbn_computone_4 },
2375 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2376 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2377 0, 0, pbn_computone_8 },
2378 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2379 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2380 0, 0, pbn_computone_6 },
2381
2382 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2384 pbn_oxsemi },
2385 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2386 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2387 pbn_b0_bt_1_921600 },
2388
2389 /*
2390 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2391 */
2392 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2394 pbn_b0_bt_8_115200 },
2395 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2397 pbn_b0_bt_8_115200 },
2398
2399 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2401 pbn_b0_bt_2_115200 },
2402 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2404 pbn_b0_bt_2_115200 },
2405 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2407 pbn_b0_bt_2_115200 },
2408 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2410 pbn_b0_bt_4_460800 },
2411 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2413 pbn_b0_bt_4_460800 },
2414 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2416 pbn_b0_bt_2_460800 },
2417 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2419 pbn_b0_bt_2_460800 },
2420 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2422 pbn_b0_bt_2_460800 },
2423 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2425 pbn_b0_bt_1_115200 },
2426 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2428 pbn_b0_bt_1_460800 },
2429
2430 /*
Russell King1fb8cac2006-12-13 14:45:46 +00002431 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2432 * Cards are identified by their subsystem vendor IDs, which
2433 * (in hex) match the model number.
2434 *
2435 * Note that JC140x are RS422/485 cards which require ox950
2436 * ACR = 0x10, and as such are not currently fully supported.
2437 */
2438 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2439 0x1204, 0x0004, 0, 0,
2440 pbn_b0_4_921600 },
2441 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2442 0x1208, 0x0004, 0, 0,
2443 pbn_b0_4_921600 },
2444/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2445 0x1402, 0x0002, 0, 0,
2446 pbn_b0_2_921600 }, */
2447/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2448 0x1404, 0x0004, 0, 0,
2449 pbn_b0_4_921600 }, */
2450 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2451 0x1208, 0x0004, 0, 0,
2452 pbn_b0_4_921600 },
2453
2454 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002455 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2456 */
2457 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2459 pbn_b1_1_1382400 },
2460
2461 /*
2462 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2463 */
2464 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2466 pbn_b1_1_1382400 },
2467
2468 /*
2469 * RAStel 2 port modem, gerg@moreton.com.au
2470 */
2471 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2473 pbn_b2_bt_2_115200 },
2474
2475 /*
2476 * EKF addition for i960 Boards form EKF with serial port
2477 */
2478 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2479 0xE4BF, PCI_ANY_ID, 0, 0,
2480 pbn_intel_i960 },
2481
2482 /*
2483 * Xircom Cardbus/Ethernet combos
2484 */
2485 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2487 pbn_b0_1_115200 },
2488 /*
2489 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2490 */
2491 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2493 pbn_b0_1_115200 },
2494
2495 /*
2496 * Untested PCI modems, sent in from various folks...
2497 */
2498
2499 /*
2500 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2501 */
2502 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2503 0x1048, 0x1500, 0, 0,
2504 pbn_b1_1_115200 },
2505
2506 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2507 0xFF00, 0, 0, 0,
2508 pbn_sgi_ioc3 },
2509
2510 /*
2511 * HP Diva card
2512 */
2513 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2514 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2515 pbn_b1_1_115200 },
2516 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2518 pbn_b0_5_115200 },
2519 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2521 pbn_b2_1_115200 },
2522
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00002523 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2525 pbn_b3_2_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002526 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2528 pbn_b3_4_115200 },
2529 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2531 pbn_b3_8_115200 },
2532
2533 /*
2534 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2535 */
2536 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2537 PCI_ANY_ID, PCI_ANY_ID,
2538 0,
2539 0, pbn_exar_XR17C152 },
2540 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2541 PCI_ANY_ID, PCI_ANY_ID,
2542 0,
2543 0, pbn_exar_XR17C154 },
2544 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2545 PCI_ANY_ID, PCI_ANY_ID,
2546 0,
2547 0, pbn_exar_XR17C158 },
2548
2549 /*
2550 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2551 */
2552 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2554 pbn_b0_1_115200 },
Niels de Vos84f8c6f2007-08-22 14:01:14 -07002555 /*
2556 * ITE
2557 */
2558 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2559 PCI_ANY_ID, PCI_ANY_ID,
2560 0, 0,
2561 pbn_b1_bt_1_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002562
2563 /*
Peter Horton737c1752006-08-26 09:07:36 +01002564 * IntaShield IS-200
2565 */
2566 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2567 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2568 pbn_b2_2_115200 },
2569
2570 /*
Thomas Hoehn48212002007-02-10 01:46:05 -08002571 * Perle PCI-RAS cards
2572 */
2573 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2574 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2575 0, 0, pbn_b2_4_921600 },
2576 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2577 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2578 0, 0, pbn_b2_8_921600 },
Alan Coxbf0df632007-10-16 01:24:00 -07002579
2580 /*
2581 * Mainpine series cards: Fairly standard layout but fools
2582 * parts of the autodetect in some cases and uses otherwise
2583 * unmatched communications subclasses in the PCI Express case
2584 */
2585
2586 { /* RockForceDUO */
2587 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2588 PCI_VENDOR_ID_MAINPINE, 0x0200,
2589 0, 0, pbn_b0_2_115200 },
2590 { /* RockForceQUATRO */
2591 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2592 PCI_VENDOR_ID_MAINPINE, 0x0300,
2593 0, 0, pbn_b0_4_115200 },
2594 { /* RockForceDUO+ */
2595 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2596 PCI_VENDOR_ID_MAINPINE, 0x0400,
2597 0, 0, pbn_b0_2_115200 },
2598 { /* RockForceQUATRO+ */
2599 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2600 PCI_VENDOR_ID_MAINPINE, 0x0500,
2601 0, 0, pbn_b0_4_115200 },
2602 { /* RockForce+ */
2603 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2604 PCI_VENDOR_ID_MAINPINE, 0x0600,
2605 0, 0, pbn_b0_2_115200 },
2606 { /* RockForce+ */
2607 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2608 PCI_VENDOR_ID_MAINPINE, 0x0700,
2609 0, 0, pbn_b0_4_115200 },
2610 { /* RockForceOCTO+ */
2611 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2612 PCI_VENDOR_ID_MAINPINE, 0x0800,
2613 0, 0, pbn_b0_8_115200 },
2614 { /* RockForceDUO+ */
2615 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2616 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2617 0, 0, pbn_b0_2_115200 },
2618 { /* RockForceQUARTRO+ */
2619 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2620 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2621 0, 0, pbn_b0_4_115200 },
2622 { /* RockForceOCTO+ */
2623 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2624 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2625 0, 0, pbn_b0_8_115200 },
2626 { /* RockForceD1 */
2627 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2628 PCI_VENDOR_ID_MAINPINE, 0x2000,
2629 0, 0, pbn_b0_1_115200 },
2630 { /* RockForceF1 */
2631 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2632 PCI_VENDOR_ID_MAINPINE, 0x2100,
2633 0, 0, pbn_b0_1_115200 },
2634 { /* RockForceD2 */
2635 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2636 PCI_VENDOR_ID_MAINPINE, 0x2200,
2637 0, 0, pbn_b0_2_115200 },
2638 { /* RockForceF2 */
2639 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2640 PCI_VENDOR_ID_MAINPINE, 0x2300,
2641 0, 0, pbn_b0_2_115200 },
2642 { /* RockForceD4 */
2643 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2644 PCI_VENDOR_ID_MAINPINE, 0x2400,
2645 0, 0, pbn_b0_4_115200 },
2646 { /* RockForceF4 */
2647 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2648 PCI_VENDOR_ID_MAINPINE, 0x2500,
2649 0, 0, pbn_b0_4_115200 },
2650 { /* RockForceD8 */
2651 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2652 PCI_VENDOR_ID_MAINPINE, 0x2600,
2653 0, 0, pbn_b0_8_115200 },
2654 { /* RockForceF8 */
2655 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2656 PCI_VENDOR_ID_MAINPINE, 0x2700,
2657 0, 0, pbn_b0_8_115200 },
2658 { /* IQ Express D1 */
2659 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2660 PCI_VENDOR_ID_MAINPINE, 0x3000,
2661 0, 0, pbn_b0_1_115200 },
2662 { /* IQ Express F1 */
2663 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2664 PCI_VENDOR_ID_MAINPINE, 0x3100,
2665 0, 0, pbn_b0_1_115200 },
2666 { /* IQ Express D2 */
2667 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2668 PCI_VENDOR_ID_MAINPINE, 0x3200,
2669 0, 0, pbn_b0_2_115200 },
2670 { /* IQ Express F2 */
2671 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2672 PCI_VENDOR_ID_MAINPINE, 0x3300,
2673 0, 0, pbn_b0_2_115200 },
2674 { /* IQ Express D4 */
2675 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2676 PCI_VENDOR_ID_MAINPINE, 0x3400,
2677 0, 0, pbn_b0_4_115200 },
2678 { /* IQ Express F4 */
2679 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2680 PCI_VENDOR_ID_MAINPINE, 0x3500,
2681 0, 0, pbn_b0_4_115200 },
2682 { /* IQ Express D8 */
2683 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2684 PCI_VENDOR_ID_MAINPINE, 0x3C00,
2685 0, 0, pbn_b0_8_115200 },
2686 { /* IQ Express F8 */
2687 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2688 PCI_VENDOR_ID_MAINPINE, 0x3D00,
2689 0, 0, pbn_b0_8_115200 },
2690
2691
Thomas Hoehn48212002007-02-10 01:46:05 -08002692 /*
Olof Johanssonaa798502007-08-22 14:01:55 -07002693 * PA Semi PA6T-1682M on-chip UART
2694 */
2695 { PCI_VENDOR_ID_PASEMI, 0xa004,
2696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2697 pbn_pasemi_1682M },
2698
2699 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002700 * These entries match devices with class COMMUNICATION_SERIAL,
2701 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2702 */
2703 { PCI_ANY_ID, PCI_ANY_ID,
2704 PCI_ANY_ID, PCI_ANY_ID,
2705 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2706 0xffff00, pbn_default },
2707 { PCI_ANY_ID, PCI_ANY_ID,
2708 PCI_ANY_ID, PCI_ANY_ID,
2709 PCI_CLASS_COMMUNICATION_MODEM << 8,
2710 0xffff00, pbn_default },
2711 { PCI_ANY_ID, PCI_ANY_ID,
2712 PCI_ANY_ID, PCI_ANY_ID,
2713 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2714 0xffff00, pbn_default },
2715 { 0, }
2716};
2717
2718static struct pci_driver serial_pci_driver = {
2719 .name = "serial",
2720 .probe = pciserial_init_one,
2721 .remove = __devexit_p(pciserial_remove_one),
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002722#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002723 .suspend = pciserial_suspend_one,
2724 .resume = pciserial_resume_one,
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07002725#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002726 .id_table = serial_pci_tbl,
2727};
2728
2729static int __init serial8250_pci_init(void)
2730{
2731 return pci_register_driver(&serial_pci_driver);
2732}
2733
2734static void __exit serial8250_pci_exit(void)
2735{
2736 pci_unregister_driver(&serial_pci_driver);
2737}
2738
2739module_init(serial8250_pci_init);
2740module_exit(serial8250_pci_exit);
2741
2742MODULE_LICENSE("GPL");
2743MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2744MODULE_DEVICE_TABLE(pci, serial_pci_tbl);