Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file contains work-arounds for many known PCI hardware |
| 3 | * bugs. Devices present only on certain architectures (host |
| 4 | * bridges et cetera) should be handled in arch-specific code. |
| 5 | * |
| 6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. |
| 7 | * |
| 8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> |
| 9 | * |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 10 | * Init/reset quirks for USB host controllers should be in the |
| 11 | * USB quirks file, where their drivers can access reuse it. |
| 12 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | * The bridge optimization stuff has been removed. If you really |
| 14 | * have a silly BIOS which is unable to set your host bridge right, |
| 15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). |
| 16 | */ |
| 17 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/types.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/delay.h> |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 23 | #include <linux/acpi.h> |
Greg KH | bc56b9e | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 24 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
Doug Thompson | bd8481e | 2006-05-08 17:06:09 -0700 | [diff] [blame] | 26 | /* The Mellanox Tavor device gives false positive parity errors |
| 27 | * Mark this device with a broken_parity_status, to allow |
| 28 | * PCI scanning code to "skip" this now blacklisted device. |
| 29 | */ |
| 30 | static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) |
| 31 | { |
| 32 | dev->broken_parity_status = 1; /* This device gives false positives */ |
| 33 | } |
| 34 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); |
| 35 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | /* Deal with broken BIOS'es that neglect to enable passive release, |
| 38 | which can cause problems in combination with the 82441FX/PPro MTRRs */ |
| 39 | static void __devinit quirk_passive_release(struct pci_dev *dev) |
| 40 | { |
| 41 | struct pci_dev *d = NULL; |
| 42 | unsigned char dlc; |
| 43 | |
| 44 | /* We have to make sure a particular bit is set in the PIIX3 |
| 45 | ISA bridge, so we have to go out and find it. */ |
| 46 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { |
| 47 | pci_read_config_byte(d, 0x82, &dlc); |
| 48 | if (!(dlc & 1<<1)) { |
| 49 | printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); |
| 50 | dlc |= 1<<1; |
| 51 | pci_write_config_byte(d, 0x82, dlc); |
| 52 | } |
| 53 | } |
| 54 | } |
| 55 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); |
| 56 | |
| 57 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround |
| 58 | but VIA don't answer queries. If you happen to have good contacts at VIA |
| 59 | ask them for me please -- Alan |
| 60 | |
| 61 | This appears to be BIOS not version dependent. So presumably there is a |
| 62 | chipset level fix */ |
| 63 | int isa_dma_bridge_buggy; /* Exported */ |
| 64 | |
| 65 | static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) |
| 66 | { |
| 67 | if (!isa_dma_bridge_buggy) { |
| 68 | isa_dma_bridge_buggy=1; |
| 69 | printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); |
| 70 | } |
| 71 | } |
| 72 | /* |
| 73 | * Its not totally clear which chipsets are the problematic ones |
| 74 | * We know 82C586 and 82C596 variants are affected. |
| 75 | */ |
| 76 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); |
| 77 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); |
| 78 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); |
| 79 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); |
| 80 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); |
| 81 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); |
| 82 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); |
| 83 | |
| 84 | int pci_pci_problems; |
| 85 | |
| 86 | /* |
| 87 | * Chipsets where PCI->PCI transfers vanish or hang |
| 88 | */ |
| 89 | static void __devinit quirk_nopcipci(struct pci_dev *dev) |
| 90 | { |
| 91 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { |
| 92 | printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); |
| 93 | pci_pci_problems |= PCIPCI_FAIL; |
| 94 | } |
| 95 | } |
| 96 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); |
| 97 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); |
| 98 | |
| 99 | /* |
| 100 | * Triton requires workarounds to be used by the drivers |
| 101 | */ |
| 102 | static void __devinit quirk_triton(struct pci_dev *dev) |
| 103 | { |
| 104 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { |
| 105 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 106 | pci_pci_problems |= PCIPCI_TRITON; |
| 107 | } |
| 108 | } |
| 109 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); |
| 110 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); |
| 111 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); |
| 112 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); |
| 113 | |
| 114 | /* |
| 115 | * VIA Apollo KT133 needs PCI latency patch |
| 116 | * Made according to a windows driver based patch by George E. Breese |
| 117 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm |
| 118 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for |
| 119 | * the info on which Mr Breese based his work. |
| 120 | * |
| 121 | * Updated based on further information from the site and also on |
| 122 | * information provided by VIA |
| 123 | */ |
| 124 | static void __devinit quirk_vialatency(struct pci_dev *dev) |
| 125 | { |
| 126 | struct pci_dev *p; |
| 127 | u8 rev; |
| 128 | u8 busarb; |
| 129 | /* Ok we have a potential problem chipset here. Now see if we have |
| 130 | a buggy southbridge */ |
| 131 | |
| 132 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); |
| 133 | if (p!=NULL) { |
| 134 | pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); |
| 135 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
| 136 | /* Check for buggy part revisions */ |
| 137 | if (rev < 0x40 || rev > 0x42) |
| 138 | goto exit; |
| 139 | } else { |
| 140 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); |
| 141 | if (p==NULL) /* No problem parts */ |
| 142 | goto exit; |
| 143 | pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); |
| 144 | /* Check for buggy part revisions */ |
| 145 | if (rev < 0x10 || rev > 0x12) |
| 146 | goto exit; |
| 147 | } |
| 148 | |
| 149 | /* |
| 150 | * Ok we have the problem. Now set the PCI master grant to |
| 151 | * occur every master grant. The apparent bug is that under high |
| 152 | * PCI load (quite common in Linux of course) you can get data |
| 153 | * loss when the CPU is held off the bus for 3 bus master requests |
| 154 | * This happens to include the IDE controllers.... |
| 155 | * |
| 156 | * VIA only apply this fix when an SB Live! is present but under |
| 157 | * both Linux and Windows this isnt enough, and we have seen |
| 158 | * corruption without SB Live! but with things like 3 UDMA IDE |
| 159 | * controllers. So we ignore that bit of the VIA recommendation.. |
| 160 | */ |
| 161 | |
| 162 | pci_read_config_byte(dev, 0x76, &busarb); |
| 163 | /* Set bit 4 and bi 5 of byte 76 to 0x01 |
| 164 | "Master priority rotation on every PCI master grant */ |
| 165 | busarb &= ~(1<<5); |
| 166 | busarb |= (1<<4); |
| 167 | pci_write_config_byte(dev, 0x76, busarb); |
| 168 | printk(KERN_INFO "Applying VIA southbridge workaround.\n"); |
| 169 | exit: |
| 170 | pci_dev_put(p); |
| 171 | } |
| 172 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); |
| 173 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); |
| 174 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); |
| 175 | |
| 176 | /* |
| 177 | * VIA Apollo VP3 needs ETBF on BT848/878 |
| 178 | */ |
| 179 | static void __devinit quirk_viaetbf(struct pci_dev *dev) |
| 180 | { |
| 181 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { |
| 182 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 183 | pci_pci_problems |= PCIPCI_VIAETBF; |
| 184 | } |
| 185 | } |
| 186 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); |
| 187 | |
| 188 | static void __devinit quirk_vsfx(struct pci_dev *dev) |
| 189 | { |
| 190 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { |
| 191 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 192 | pci_pci_problems |= PCIPCI_VSFX; |
| 193 | } |
| 194 | } |
| 195 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); |
| 196 | |
| 197 | /* |
| 198 | * Ali Magik requires workarounds to be used by the drivers |
| 199 | * that DMA to AGP space. Latency must be set to 0xA and triton |
| 200 | * workaround applied too |
| 201 | * [Info kindly provided by ALi] |
| 202 | */ |
| 203 | static void __init quirk_alimagik(struct pci_dev *dev) |
| 204 | { |
| 205 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { |
| 206 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 207 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
| 208 | } |
| 209 | } |
| 210 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); |
| 211 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); |
| 212 | |
| 213 | /* |
| 214 | * Natoma has some interesting boundary conditions with Zoran stuff |
| 215 | * at least |
| 216 | */ |
| 217 | static void __devinit quirk_natoma(struct pci_dev *dev) |
| 218 | { |
| 219 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { |
| 220 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); |
| 221 | pci_pci_problems |= PCIPCI_NATOMA; |
| 222 | } |
| 223 | } |
| 224 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); |
| 225 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); |
| 226 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); |
| 227 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); |
| 228 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); |
| 229 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); |
| 230 | |
| 231 | /* |
| 232 | * This chip can cause PCI parity errors if config register 0xA0 is read |
| 233 | * while DMAs are occurring. |
| 234 | */ |
| 235 | static void __devinit quirk_citrine(struct pci_dev *dev) |
| 236 | { |
| 237 | dev->cfg_size = 0xA0; |
| 238 | } |
| 239 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); |
| 240 | |
| 241 | /* |
| 242 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. |
| 243 | * If it's needed, re-allocate the region. |
| 244 | */ |
| 245 | static void __devinit quirk_s3_64M(struct pci_dev *dev) |
| 246 | { |
| 247 | struct resource *r = &dev->resource[0]; |
| 248 | |
| 249 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { |
| 250 | r->start = 0; |
| 251 | r->end = 0x3ffffff; |
| 252 | } |
| 253 | } |
| 254 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); |
| 255 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); |
| 256 | |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 257 | static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, |
| 258 | unsigned size, int nr, const char *name) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | { |
| 260 | region &= ~(size-1); |
| 261 | if (region) { |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 262 | struct pci_bus_region bus_region; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | struct resource *res = dev->resource + nr; |
| 264 | |
| 265 | res->name = pci_name(dev); |
| 266 | res->start = region; |
| 267 | res->end = region + size - 1; |
| 268 | res->flags = IORESOURCE_IO; |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 269 | |
| 270 | /* Convert from PCI bus to resource space. */ |
| 271 | bus_region.start = res->start; |
| 272 | bus_region.end = res->end; |
| 273 | pcibios_bus_to_resource(dev, res, &bus_region); |
| 274 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 275 | pci_claim_resource(dev, nr); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 276 | printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | } |
| 278 | } |
| 279 | |
| 280 | /* |
| 281 | * ATI Northbridge setups MCE the processor if you even |
| 282 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 |
| 283 | */ |
| 284 | static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) |
| 285 | { |
| 286 | printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); |
| 287 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
| 288 | request_region(0x3b0, 0x0C, "RadeonIGP"); |
| 289 | request_region(0x3d3, 0x01, "RadeonIGP"); |
| 290 | } |
| 291 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); |
| 292 | |
| 293 | /* |
| 294 | * Let's make the southbridge information explicit instead |
| 295 | * of having to worry about people probing the ACPI areas, |
| 296 | * for example.. (Yes, it happens, and if you read the wrong |
| 297 | * ACPI register it will put the machine to sleep with no |
| 298 | * way of waking it up again. Bummer). |
| 299 | * |
| 300 | * ALI M7101: Two IO regions pointed to by words at |
| 301 | * 0xE0 (64 bytes of ACPI registers) |
| 302 | * 0xE2 (32 bytes of SMB registers) |
| 303 | */ |
| 304 | static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) |
| 305 | { |
| 306 | u16 region; |
| 307 | |
| 308 | pci_read_config_word(dev, 0xE0, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 309 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 310 | pci_read_config_word(dev, 0xE2, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 311 | quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | } |
| 313 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); |
| 314 | |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 315 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
| 316 | { |
| 317 | u32 devres; |
| 318 | u32 mask, size, base; |
| 319 | |
| 320 | pci_read_config_dword(dev, port, &devres); |
| 321 | if ((devres & enable) != enable) |
| 322 | return; |
| 323 | mask = (devres >> 16) & 15; |
| 324 | base = devres & 0xffff; |
| 325 | size = 16; |
| 326 | for (;;) { |
| 327 | unsigned bit = size >> 1; |
| 328 | if ((bit & mask) == bit) |
| 329 | break; |
| 330 | size = bit; |
| 331 | } |
| 332 | /* |
| 333 | * For now we only print it out. Eventually we'll want to |
| 334 | * reserve it (at least if it's in the 0x1000+ range), but |
| 335 | * let's get enough confirmation reports first. |
| 336 | */ |
| 337 | base &= -size; |
| 338 | printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); |
| 339 | } |
| 340 | |
| 341 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
| 342 | { |
| 343 | u32 devres; |
| 344 | u32 mask, size, base; |
| 345 | |
| 346 | pci_read_config_dword(dev, port, &devres); |
| 347 | if ((devres & enable) != enable) |
| 348 | return; |
| 349 | base = devres & 0xffff0000; |
| 350 | mask = (devres & 0x3f) << 16; |
| 351 | size = 128 << 16; |
| 352 | for (;;) { |
| 353 | unsigned bit = size >> 1; |
| 354 | if ((bit & mask) == bit) |
| 355 | break; |
| 356 | size = bit; |
| 357 | } |
| 358 | /* |
| 359 | * For now we only print it out. Eventually we'll want to |
| 360 | * reserve it, but let's get enough confirmation reports first. |
| 361 | */ |
| 362 | base &= -size; |
| 363 | printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
| 364 | } |
| 365 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 366 | /* |
| 367 | * PIIX4 ACPI: Two IO regions pointed to by longwords at |
| 368 | * 0x40 (64 bytes of ACPI registers) |
Linus Torvalds | 08db2a7 | 2005-10-30 14:40:07 -0800 | [diff] [blame] | 369 | * 0x90 (16 bytes of SMB registers) |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 370 | * and a few strange programmable PIIX4 device resources. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | */ |
| 372 | static void __devinit quirk_piix4_acpi(struct pci_dev *dev) |
| 373 | { |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 374 | u32 region, res_a; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | |
| 376 | pci_read_config_dword(dev, 0x40, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 377 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | pci_read_config_dword(dev, 0x90, ®ion); |
Linus Torvalds | 08db2a7 | 2005-10-30 14:40:07 -0800 | [diff] [blame] | 379 | quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 380 | |
| 381 | /* Device resource A has enables for some of the other ones */ |
| 382 | pci_read_config_dword(dev, 0x5c, &res_a); |
| 383 | |
| 384 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); |
| 385 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); |
| 386 | |
| 387 | /* Device resource D is just bitfields for static resources */ |
| 388 | |
| 389 | /* Device 12 enabled? */ |
| 390 | if (res_a & (1 << 29)) { |
| 391 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); |
| 392 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); |
| 393 | } |
| 394 | /* Device 13 enabled? */ |
| 395 | if (res_a & (1 << 30)) { |
| 396 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); |
| 397 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); |
| 398 | } |
| 399 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); |
| 400 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | } |
| 402 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); |
Linus Torvalds | c676466 | 2006-07-12 08:29:46 -0700 | [diff] [blame] | 403 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 404 | |
| 405 | /* |
| 406 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at |
| 407 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) |
| 408 | * 0x58 (64 bytes of GPIO I/O space) |
| 409 | */ |
| 410 | static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) |
| 411 | { |
| 412 | u32 region; |
| 413 | |
| 414 | pci_read_config_dword(dev, 0x40, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 415 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | |
| 417 | pci_read_config_dword(dev, 0x58, ®ion); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 418 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | } |
| 420 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); |
| 421 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); |
| 422 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); |
| 423 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); |
| 424 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); |
| 425 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); |
| 426 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); |
| 427 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); |
| 428 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); |
R.Marek@sh.cvut.cz | 3aa8c4f | 2005-04-21 10:49:06 +0000 | [diff] [blame] | 429 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 430 | |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 431 | static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) |
| 432 | { |
| 433 | u32 region; |
| 434 | |
| 435 | pci_read_config_dword(dev, 0x40, ®ion); |
| 436 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); |
| 437 | |
| 438 | pci_read_config_dword(dev, 0x48, ®ion); |
| 439 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); |
| 440 | } |
| 441 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); |
| 442 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | /* |
| 444 | * VIA ACPI: One IO region pointed to by longword at |
| 445 | * 0x48 or 0x20 (256 bytes of ACPI registers) |
| 446 | */ |
| 447 | static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) |
| 448 | { |
| 449 | u8 rev; |
| 450 | u32 region; |
| 451 | |
| 452 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
| 453 | if (rev & 0x10) { |
| 454 | pci_read_config_dword(dev, 0x48, ®ion); |
| 455 | region &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 456 | quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | } |
| 458 | } |
| 459 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); |
| 460 | |
| 461 | /* |
| 462 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at |
| 463 | * 0x48 (256 bytes of ACPI registers) |
| 464 | * 0x70 (128 bytes of hardware monitoring register) |
| 465 | * 0x90 (16 bytes of SMB registers) |
| 466 | */ |
| 467 | static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) |
| 468 | { |
| 469 | u16 hm; |
| 470 | u32 smb; |
| 471 | |
| 472 | quirk_vt82c586_acpi(dev); |
| 473 | |
| 474 | pci_read_config_word(dev, 0x70, &hm); |
| 475 | hm &= PCI_BASE_ADDRESS_IO_MASK; |
Meelis Roos | 02f313b | 2005-10-29 13:31:49 +0300 | [diff] [blame] | 476 | quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | |
| 478 | pci_read_config_dword(dev, 0x90, &smb); |
| 479 | smb &= PCI_BASE_ADDRESS_IO_MASK; |
Meelis Roos | 02f313b | 2005-10-29 13:31:49 +0300 | [diff] [blame] | 480 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | } |
| 482 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); |
| 483 | |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 484 | /* |
| 485 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at |
| 486 | * 0x88 (128 bytes of power management registers) |
| 487 | * 0xd0 (16 bytes of SMB registers) |
| 488 | */ |
| 489 | static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) |
| 490 | { |
| 491 | u16 pm, smb; |
| 492 | |
| 493 | pci_read_config_word(dev, 0x88, &pm); |
| 494 | pm &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 495 | quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 496 | |
| 497 | pci_read_config_word(dev, 0xd0, &smb); |
| 498 | smb &= PCI_BASE_ADDRESS_IO_MASK; |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 499 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 500 | } |
| 501 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); |
| 502 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | |
| 504 | #ifdef CONFIG_X86_IO_APIC |
| 505 | |
| 506 | #include <asm/io_apic.h> |
| 507 | |
| 508 | /* |
| 509 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip |
| 510 | * devices to the external APIC. |
| 511 | * |
| 512 | * TODO: When we have device-specific interrupt routers, |
| 513 | * this code will go away from quirks. |
| 514 | */ |
| 515 | static void __devinit quirk_via_ioapic(struct pci_dev *dev) |
| 516 | { |
| 517 | u8 tmp; |
| 518 | |
| 519 | if (nr_ioapics < 1) |
| 520 | tmp = 0; /* nothing routed to external APIC */ |
| 521 | else |
| 522 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ |
| 523 | |
| 524 | printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", |
| 525 | tmp == 0 ? "Disa" : "Ena"); |
| 526 | |
| 527 | /* Offset 0x58: External APIC IRQ output control */ |
| 528 | pci_write_config_byte (dev, 0x58, tmp); |
| 529 | } |
| 530 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); |
| 531 | |
| 532 | /* |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 533 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. |
| 534 | * This leads to doubled level interrupt rates. |
| 535 | * Set this bit to get rid of cycle wastage. |
| 536 | * Otherwise uncritical. |
| 537 | */ |
| 538 | static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
| 539 | { |
| 540 | u8 misc_control2; |
| 541 | #define BYPASS_APIC_DEASSERT 8 |
| 542 | |
| 543 | pci_read_config_byte(dev, 0x5B, &misc_control2); |
| 544 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { |
| 545 | printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); |
| 546 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
| 547 | } |
| 548 | } |
| 549 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
| 550 | |
| 551 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 552 | * The AMD io apic can hang the box when an apic irq is masked. |
| 553 | * We check all revs >= B0 (yet not in the pre production!) as the bug |
| 554 | * is currently marked NoFix |
| 555 | * |
| 556 | * We have multiple reports of hangs with this chipset that went away with |
| 557 | * noapic specified. For the moment we assume its the errata. We may be wrong |
| 558 | * of course. However the advice is demonstrably good even if so.. |
| 559 | */ |
| 560 | static void __devinit quirk_amd_ioapic(struct pci_dev *dev) |
| 561 | { |
| 562 | u8 rev; |
| 563 | |
| 564 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); |
| 565 | if (rev >= 0x02) { |
| 566 | printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n"); |
| 567 | printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); |
| 568 | } |
| 569 | } |
| 570 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); |
| 571 | |
| 572 | static void __init quirk_ioapic_rmw(struct pci_dev *dev) |
| 573 | { |
| 574 | if (dev->devfn == 0 && dev->bus->number == 0) |
| 575 | sis_apic_bug = 1; |
| 576 | } |
| 577 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); |
| 578 | |
| 579 | int pci_msi_quirk; |
| 580 | |
| 581 | #define AMD8131_revA0 0x01 |
| 582 | #define AMD8131_revB0 0x11 |
| 583 | #define AMD8131_MISC 0x40 |
| 584 | #define AMD8131_NIOAMODE_BIT 0 |
| 585 | static void __init quirk_amd_8131_ioapic(struct pci_dev *dev) |
| 586 | { |
| 587 | unsigned char revid, tmp; |
| 588 | |
Michael S. Tsirkin | 6e325a6 | 2006-02-14 18:52:22 +0200 | [diff] [blame] | 589 | if (dev->subordinate) { |
| 590 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
| 591 | "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n"); |
| 592 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 593 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | |
| 595 | if (nr_ioapics == 0) |
| 596 | return; |
| 597 | |
| 598 | pci_read_config_byte(dev, PCI_REVISION_ID, &revid); |
| 599 | if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { |
| 600 | printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); |
| 601 | pci_read_config_byte( dev, AMD8131_MISC, &tmp); |
| 602 | tmp &= ~(1 << AMD8131_NIOAMODE_BIT); |
| 603 | pci_write_config_byte( dev, AMD8131_MISC, tmp); |
| 604 | } |
| 605 | } |
John W. Linville | 5da594b | 2006-03-20 14:33:56 -0500 | [diff] [blame] | 606 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | |
Narendra Sankar | 1e06276 | 2005-05-06 12:00:05 -0700 | [diff] [blame] | 608 | static void __init quirk_svw_msi(struct pci_dev *dev) |
| 609 | { |
| 610 | pci_msi_quirk = 1; |
| 611 | printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n"); |
| 612 | } |
| 613 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | #endif /* CONFIG_X86_IO_APIC */ |
| 615 | |
| 616 | |
| 617 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | * FIXME: it is questionable that quirk_via_acpi |
| 619 | * is needed. It shows up as an ISA bridge, and does not |
| 620 | * support the PCI_INTERRUPT_LINE register at all. Therefore |
| 621 | * it seems like setting the pci_dev's 'irq' to the |
| 622 | * value of the ACPI SCI interrupt is only done for convenience. |
| 623 | * -jgarzik |
| 624 | */ |
| 625 | static void __devinit quirk_via_acpi(struct pci_dev *d) |
| 626 | { |
| 627 | /* |
| 628 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 |
| 629 | */ |
| 630 | u8 irq; |
| 631 | pci_read_config_byte(d, 0x42, &irq); |
| 632 | irq &= 0xf; |
| 633 | if (irq && (irq != 2)) |
| 634 | d->irq = irq; |
| 635 | } |
| 636 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); |
| 637 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); |
| 638 | |
Bjorn Helgaas | 93cffff | 2005-06-07 13:22:18 -0700 | [diff] [blame] | 639 | /* |
| 640 | * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip |
| 641 | * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature: |
| 642 | * when written, it makes an internal connection to the PIC. |
| 643 | * For these devices, this register is defined to be 4 bits wide. |
| 644 | * Normally this is fine. However for IO-APIC motherboards, or |
| 645 | * non-x86 architectures (yes Via exists on PPC among other places), |
| 646 | * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get |
| 647 | * interrupts delivered properly. |
Chris Wedgwood | a7b862f | 2006-05-15 09:43:55 -0700 | [diff] [blame] | 648 | * |
| 649 | * Some of the on-chip devices are actually '586 devices' so they are |
| 650 | * listed here. |
Bjorn Helgaas | 93cffff | 2005-06-07 13:22:18 -0700 | [diff] [blame] | 651 | */ |
| 652 | static void quirk_via_irq(struct pci_dev *dev) |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 653 | { |
| 654 | u8 irq, new_irq; |
| 655 | |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 656 | new_irq = dev->irq & 0xf; |
| 657 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
| 658 | if (new_irq != irq) { |
Chris Wedgwood | 75cf745 | 2006-04-18 23:57:09 -0700 | [diff] [blame] | 659 | printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n", |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 660 | pci_name(dev), irq, new_irq); |
| 661 | udelay(15); /* unknown if delay really needed */ |
| 662 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); |
| 663 | } |
| 664 | } |
Chris Wedgwood | a7b862f | 2006-05-15 09:43:55 -0700 | [diff] [blame] | 665 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq); |
| 666 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq); |
| 667 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq); |
| 668 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq); |
Chris Wedgwood | 75cf745 | 2006-04-18 23:57:09 -0700 | [diff] [blame] | 669 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq); |
| 670 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq); |
| 671 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq); |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 672 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 673 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 674 | * VIA VT82C598 has its device ID settable and many BIOSes |
| 675 | * set it to the ID of VT82C597 for backward compatibility. |
| 676 | * We need to switch it off to be able to recognize the real |
| 677 | * type of the chip. |
| 678 | */ |
| 679 | static void __devinit quirk_vt82c598_id(struct pci_dev *dev) |
| 680 | { |
| 681 | pci_write_config_byte(dev, 0xfc, 0); |
| 682 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); |
| 683 | } |
| 684 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); |
| 685 | |
Matthew Garrett | 709cf5e | 2006-06-30 02:31:25 -0700 | [diff] [blame] | 686 | #ifdef CONFIG_ACPI_SLEEP |
| 687 | |
| 688 | /* |
| 689 | * Some VIA systems boot with the abnormal status flag set. This can cause |
| 690 | * the BIOS to re-POST the system on resume rather than passing control |
| 691 | * back to the OS. Clear the flag on boot |
| 692 | */ |
| 693 | static void __devinit quirk_via_abnormal_poweroff(struct pci_dev *dev) |
| 694 | { |
| 695 | u32 reg; |
| 696 | |
| 697 | acpi_hw_register_read(ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS, |
| 698 | ®); |
| 699 | |
| 700 | if (reg & 0x800) { |
| 701 | printk("Clearing abnormal poweroff flag\n"); |
| 702 | acpi_hw_register_write(ACPI_MTX_DO_NOT_LOCK, |
| 703 | ACPI_REGISTER_PM1_STATUS, |
| 704 | (u16)0x800); |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_abnormal_poweroff); |
| 709 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_abnormal_poweroff); |
| 710 | |
| 711 | #endif |
| 712 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | /* |
| 714 | * CardBus controllers have a legacy base address that enables them |
| 715 | * to respond as i82365 pcmcia controllers. We don't want them to |
| 716 | * do this even if the Linux CardBus driver is not loaded, because |
| 717 | * the Linux i82365 driver does not (and should not) handle CardBus. |
| 718 | */ |
| 719 | static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) |
| 720 | { |
| 721 | if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) |
| 722 | return; |
| 723 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); |
| 724 | } |
| 725 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
| 726 | |
| 727 | /* |
| 728 | * Following the PCI ordering rules is optional on the AMD762. I'm not |
| 729 | * sure what the designers were smoking but let's not inhale... |
| 730 | * |
| 731 | * To be fair to AMD, it follows the spec by default, its BIOS people |
| 732 | * who turn it off! |
| 733 | */ |
| 734 | static void __devinit quirk_amd_ordering(struct pci_dev *dev) |
| 735 | { |
| 736 | u32 pcic; |
| 737 | pci_read_config_dword(dev, 0x4C, &pcic); |
| 738 | if ((pcic&6)!=6) { |
| 739 | pcic |= 6; |
| 740 | printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); |
| 741 | pci_write_config_dword(dev, 0x4C, pcic); |
| 742 | pci_read_config_dword(dev, 0x84, &pcic); |
| 743 | pcic |= (1<<23); /* Required in this mode */ |
| 744 | pci_write_config_dword(dev, 0x84, pcic); |
| 745 | } |
| 746 | } |
| 747 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); |
| 748 | |
| 749 | /* |
| 750 | * DreamWorks provided workaround for Dunord I-3000 problem |
| 751 | * |
| 752 | * This card decodes and responds to addresses not apparently |
| 753 | * assigned to it. We force a larger allocation to ensure that |
| 754 | * nothing gets put too close to it. |
| 755 | */ |
| 756 | static void __devinit quirk_dunord ( struct pci_dev * dev ) |
| 757 | { |
| 758 | struct resource *r = &dev->resource [1]; |
| 759 | r->start = 0; |
| 760 | r->end = 0xffffff; |
| 761 | } |
| 762 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); |
| 763 | |
| 764 | /* |
| 765 | * i82380FB mobile docking controller: its PCI-to-PCI bridge |
| 766 | * is subtractive decoding (transparent), and does indicate this |
| 767 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 |
| 768 | * instead of 0x01. |
| 769 | */ |
| 770 | static void __devinit quirk_transparent_bridge(struct pci_dev *dev) |
| 771 | { |
| 772 | dev->transparent = 1; |
| 773 | } |
| 774 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); |
| 775 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); |
| 776 | |
| 777 | /* |
| 778 | * Common misconfiguration of the MediaGX/Geode PCI master that will |
| 779 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 |
| 780 | * datasheets found at http://www.national.com/ds/GX for info on what |
| 781 | * these bits do. <christer@weinigel.se> |
| 782 | */ |
| 783 | static void __init quirk_mediagx_master(struct pci_dev *dev) |
| 784 | { |
| 785 | u8 reg; |
| 786 | pci_read_config_byte(dev, 0x41, ®); |
| 787 | if (reg & 2) { |
| 788 | reg &= ~2; |
| 789 | printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); |
| 790 | pci_write_config_byte(dev, 0x41, reg); |
| 791 | } |
| 792 | } |
| 793 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); |
| 794 | |
| 795 | /* |
| 796 | * As per PCI spec, ignore base address registers 0-3 of the IDE controllers |
| 797 | * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and |
| 798 | * secondary channels respectively). If the device reports Compatible mode |
| 799 | * but does use BAR0-3 for address decoding, we assume that firmware has |
| 800 | * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374). |
| 801 | * Exceptions (if they exist) must be handled in chip/architecture specific |
| 802 | * fixups. |
| 803 | * |
| 804 | * Note: for non x86 people. You may need an arch specific quirk to handle |
| 805 | * moving IDE devices to native mode as well. Some plug in card devices power |
| 806 | * up in compatible mode and assume the BIOS will adjust them. |
| 807 | * |
| 808 | * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as |
| 809 | * we do now ? We don't want is pci_enable_device to come along |
| 810 | * and assign new resources. Both approaches work for that. |
| 811 | */ |
| 812 | static void __devinit quirk_ide_bases(struct pci_dev *dev) |
| 813 | { |
| 814 | struct resource *res; |
| 815 | int first_bar = 2, last_bar = 0; |
| 816 | |
| 817 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) |
| 818 | return; |
| 819 | |
| 820 | res = &dev->resource[0]; |
| 821 | |
| 822 | /* primary channel: ProgIf bit 0, BAR0, BAR1 */ |
| 823 | if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { |
| 824 | res[0].start = res[0].end = res[0].flags = 0; |
| 825 | res[1].start = res[1].end = res[1].flags = 0; |
| 826 | first_bar = 0; |
| 827 | last_bar = 1; |
| 828 | } |
| 829 | |
| 830 | /* secondary channel: ProgIf bit 2, BAR2, BAR3 */ |
| 831 | if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { |
| 832 | res[2].start = res[2].end = res[2].flags = 0; |
| 833 | res[3].start = res[3].end = res[3].flags = 0; |
| 834 | last_bar = 3; |
| 835 | } |
| 836 | |
| 837 | if (!last_bar) |
| 838 | return; |
| 839 | |
| 840 | printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", |
| 841 | first_bar, last_bar, pci_name(dev)); |
| 842 | } |
| 843 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); |
| 844 | |
| 845 | /* |
| 846 | * Ensure C0 rev restreaming is off. This is normally done by |
| 847 | * the BIOS but in the odd case it is not the results are corruption |
| 848 | * hence the presence of a Linux check |
| 849 | */ |
| 850 | static void __init quirk_disable_pxb(struct pci_dev *pdev) |
| 851 | { |
| 852 | u16 config; |
| 853 | u8 rev; |
| 854 | |
| 855 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
| 856 | if (rev != 0x04) /* Only C0 requires this */ |
| 857 | return; |
| 858 | pci_read_config_word(pdev, 0x40, &config); |
| 859 | if (config & (1<<6)) { |
| 860 | config &= ~(1<<6); |
| 861 | pci_write_config_word(pdev, 0x40, config); |
| 862 | printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); |
| 863 | } |
| 864 | } |
| 865 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); |
| 866 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 867 | |
| 868 | /* |
| 869 | * Serverworks CSB5 IDE does not fully support native mode |
| 870 | */ |
| 871 | static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) |
| 872 | { |
| 873 | u8 prog; |
| 874 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 875 | if (prog & 5) { |
| 876 | prog &= ~5; |
| 877 | pdev->class &= ~5; |
| 878 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
| 879 | /* need to re-assign BARs for compat mode */ |
| 880 | quirk_ide_bases(pdev); |
| 881 | } |
| 882 | } |
| 883 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); |
| 884 | |
| 885 | /* |
| 886 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same |
| 887 | */ |
| 888 | static void __init quirk_ide_samemode(struct pci_dev *pdev) |
| 889 | { |
| 890 | u8 prog; |
| 891 | |
| 892 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 893 | |
| 894 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { |
| 895 | printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); |
| 896 | prog &= ~5; |
| 897 | pdev->class &= ~5; |
| 898 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
| 899 | /* need to re-assign BARs for compat mode */ |
| 900 | quirk_ide_bases(pdev); |
| 901 | } |
| 902 | } |
| 903 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
| 904 | |
| 905 | /* This was originally an Alpha specific thing, but it really fits here. |
| 906 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. |
| 907 | */ |
| 908 | static void __init quirk_eisa_bridge(struct pci_dev *dev) |
| 909 | { |
| 910 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; |
| 911 | } |
| 912 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); |
| 913 | |
| 914 | /* |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 915 | * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled |
| 916 | * when a PCI-Soundcard is added. The BIOS only gives Options |
| 917 | * "Disabled" and "AUTO". This Quirk Sets the corresponding |
| 918 | * Register-Value to enable the Soundcard. |
Chris Wedgwood | bd91fde | 2006-06-05 00:13:21 -0700 | [diff] [blame] | 919 | * |
| 920 | * FIXME: Presently this quirk will run on anything that has an 8237 |
| 921 | * which isn't correct, we need to check DMI tables or something in |
| 922 | * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it |
| 923 | * runs everywhere at present we suppress the printk output in most |
| 924 | * irrelevant cases. |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 925 | */ |
| 926 | static void __init k8t_sound_hostbridge(struct pci_dev *dev) |
| 927 | { |
| 928 | unsigned char val; |
| 929 | |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 930 | pci_read_config_byte(dev, 0x50, &val); |
| 931 | if (val == 0x88 || val == 0xc8) { |
Chris Wedgwood | bd91fde | 2006-06-05 00:13:21 -0700 | [diff] [blame] | 932 | /* Assume it's probably a MSI-K8T-Neo2Fir */ |
| 933 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n"); |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 934 | pci_write_config_byte(dev, 0x50, val & (~0x40)); |
| 935 | |
| 936 | /* Verify the Change for Status output */ |
| 937 | pci_read_config_byte(dev, 0x50, &val); |
| 938 | if (val & 0x40) |
Chris Wedgwood | bd91fde | 2006-06-05 00:13:21 -0700 | [diff] [blame] | 939 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n"); |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 940 | else |
Chris Wedgwood | bd91fde | 2006-06-05 00:13:21 -0700 | [diff] [blame] | 941 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n"); |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 942 | } |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 943 | } |
| 944 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); |
| 945 | |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 946 | #ifndef CONFIG_ACPI_SLEEP |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 947 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 948 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge |
| 949 | * is not activated. The myth is that Asus said that they do not want the |
| 950 | * users to be irritated by just another PCI Device in the Win98 device |
| 951 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors |
| 952 | * package 2.7.0 for details) |
| 953 | * |
| 954 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC |
| 955 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it |
| 956 | * becomes necessary to do this tweak in two steps -- I've chosen the Host |
| 957 | * bridge as trigger. |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 958 | * |
| 959 | * Actually, leaving it unhidden and not redoing the quirk over suspend2ram |
| 960 | * will cause thermal management to break down, and causing machine to |
| 961 | * overheat. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | */ |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 963 | static int __initdata asus_hides_smbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 964 | |
| 965 | static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) |
| 966 | { |
| 967 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
| 968 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) |
| 969 | switch(dev->subsystem_device) { |
Jean Delvare | a00db37 | 2005-06-29 17:04:06 +0200 | [diff] [blame] | 970 | case 0x8025: /* P4B-LX */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 971 | case 0x8070: /* P4B */ |
| 972 | case 0x8088: /* P4B533 */ |
| 973 | case 0x1626: /* L3C notebook */ |
| 974 | asus_hides_smbus = 1; |
| 975 | } |
| 976 | if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
| 977 | switch(dev->subsystem_device) { |
| 978 | case 0x80b1: /* P4GE-V */ |
| 979 | case 0x80b2: /* P4PE */ |
| 980 | case 0x8093: /* P4B533-V */ |
| 981 | asus_hides_smbus = 1; |
| 982 | } |
| 983 | if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
| 984 | switch(dev->subsystem_device) { |
| 985 | case 0x8030: /* P4T533 */ |
| 986 | asus_hides_smbus = 1; |
| 987 | } |
| 988 | if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
| 989 | switch (dev->subsystem_device) { |
| 990 | case 0x8070: /* P4G8X Deluxe */ |
| 991 | asus_hides_smbus = 1; |
| 992 | } |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame^] | 993 | if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
| 994 | switch (dev->subsystem_device) { |
| 995 | case 0x80c9: /* PU-DLS */ |
| 996 | asus_hides_smbus = 1; |
| 997 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 998 | if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
| 999 | switch (dev->subsystem_device) { |
| 1000 | case 0x1751: /* M2N notebook */ |
| 1001 | case 0x1821: /* M5N notebook */ |
| 1002 | asus_hides_smbus = 1; |
| 1003 | } |
| 1004 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1005 | switch (dev->subsystem_device) { |
| 1006 | case 0x184b: /* W1N notebook */ |
| 1007 | case 0x186a: /* M6Ne notebook */ |
| 1008 | asus_hides_smbus = 1; |
| 1009 | } |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1010 | if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { |
| 1011 | switch (dev->subsystem_device) { |
| 1012 | case 0x1882: /* M6V notebook */ |
Jean Delvare | 2d1e1c7 | 2006-04-01 16:46:35 +0200 | [diff] [blame] | 1013 | case 0x1977: /* A6VA notebook */ |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1014 | asus_hides_smbus = 1; |
| 1015 | } |
| 1016 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1017 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
| 1018 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1019 | switch(dev->subsystem_device) { |
| 1020 | case 0x088C: /* HP Compaq nc8000 */ |
| 1021 | case 0x0890: /* HP Compaq nc6000 */ |
| 1022 | asus_hides_smbus = 1; |
| 1023 | } |
| 1024 | if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
| 1025 | switch (dev->subsystem_device) { |
| 1026 | case 0x12bc: /* HP D330L */ |
Jean Delvare | e3b1bd5 | 2005-09-21 22:26:31 +0200 | [diff] [blame] | 1027 | case 0x12bd: /* HP D530 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1028 | asus_hides_smbus = 1; |
| 1029 | } |
tomek@koprowski.org | 3c0a654 | 2006-02-19 18:03:24 +0100 | [diff] [blame] | 1030 | if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) { |
| 1031 | switch (dev->subsystem_device) { |
| 1032 | case 0x099c: /* HP Compaq nx6110 */ |
| 1033 | asus_hides_smbus = 1; |
| 1034 | } |
| 1035 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1036 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { |
| 1037 | if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
| 1038 | switch(dev->subsystem_device) { |
| 1039 | case 0x0001: /* Toshiba Satellite A40 */ |
| 1040 | asus_hides_smbus = 1; |
| 1041 | } |
Daniele Gaffuri | e96e2f1 | 2005-07-29 12:15:46 -0700 | [diff] [blame] | 1042 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1043 | switch(dev->subsystem_device) { |
| 1044 | case 0x0001: /* Toshiba Tecra M2 */ |
| 1045 | asus_hides_smbus = 1; |
| 1046 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1047 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
| 1048 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1049 | switch(dev->subsystem_device) { |
| 1050 | case 0xC00C: /* Samsung P35 notebook */ |
| 1051 | asus_hides_smbus = 1; |
| 1052 | } |
Rumen Ivanov Zarev | c87f883 | 2005-09-06 13:39:32 -0700 | [diff] [blame] | 1053 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
| 1054 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1055 | switch(dev->subsystem_device) { |
| 1056 | case 0x0058: /* Compaq Evo N620c */ |
| 1057 | asus_hides_smbus = 1; |
| 1058 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1059 | } |
| 1060 | } |
| 1061 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); |
| 1062 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); |
| 1063 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); |
| 1064 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); |
| 1065 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame^] | 1066 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1067 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); |
| 1068 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1069 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1070 | |
| 1071 | static void __init asus_hides_smbus_lpc(struct pci_dev *dev) |
| 1072 | { |
| 1073 | u16 val; |
| 1074 | |
| 1075 | if (likely(!asus_hides_smbus)) |
| 1076 | return; |
| 1077 | |
| 1078 | pci_read_config_word(dev, 0xF2, &val); |
| 1079 | if (val & 0x8) { |
| 1080 | pci_write_config_word(dev, 0xF2, val & (~0x8)); |
| 1081 | pci_read_config_word(dev, 0xF2, &val); |
| 1082 | if (val & 0x8) |
| 1083 | printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); |
| 1084 | else |
| 1085 | printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); |
| 1086 | } |
| 1087 | } |
| 1088 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); |
| 1089 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame^] | 1090 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1091 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); |
| 1092 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); |
| 1093 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); |
Jean Delvare | 2d1e1c7 | 2006-04-01 16:46:35 +0200 | [diff] [blame] | 1094 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1095 | |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1096 | static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev) |
| 1097 | { |
| 1098 | u32 val, rcba; |
| 1099 | void __iomem *base; |
| 1100 | |
| 1101 | if (likely(!asus_hides_smbus)) |
| 1102 | return; |
| 1103 | pci_read_config_dword(dev, 0xF0, &rcba); |
| 1104 | base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ |
| 1105 | if (base == NULL) return; |
| 1106 | val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ |
| 1107 | writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ |
| 1108 | iounmap(base); |
| 1109 | printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); |
| 1110 | } |
| 1111 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); |
| 1112 | |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 1113 | #endif |
| 1114 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | /* |
| 1116 | * SiS 96x south bridge: BIOS typically hides SMBus device... |
| 1117 | */ |
| 1118 | static void __init quirk_sis_96x_smbus(struct pci_dev *dev) |
| 1119 | { |
| 1120 | u8 val = 0; |
| 1121 | printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); |
| 1122 | pci_read_config_byte(dev, 0x77, &val); |
| 1123 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
| 1124 | pci_read_config_byte(dev, 0x77, &val); |
| 1125 | } |
| 1126 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1127 | /* |
| 1128 | * ... This is further complicated by the fact that some SiS96x south |
| 1129 | * bridges pretend to be 85C503/5513 instead. In that case see if we |
| 1130 | * spotted a compatible north bridge to make sure. |
| 1131 | * (pci_find_device doesn't work yet) |
| 1132 | * |
| 1133 | * We can also enable the sis96x bit in the discovery register.. |
| 1134 | */ |
| 1135 | static int __devinitdata sis_96x_compatible = 0; |
| 1136 | |
| 1137 | #define SIS_DETECT_REGISTER 0x40 |
| 1138 | |
| 1139 | static void __init quirk_sis_503(struct pci_dev *dev) |
| 1140 | { |
| 1141 | u8 reg; |
| 1142 | u16 devid; |
| 1143 | |
| 1144 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); |
| 1145 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); |
| 1146 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); |
| 1147 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { |
| 1148 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); |
| 1149 | return; |
| 1150 | } |
| 1151 | |
| 1152 | /* Make people aware that we changed the config.. */ |
| 1153 | printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible); |
| 1154 | |
| 1155 | /* |
| 1156 | * Ok, it now shows up as a 96x.. The 96x quirks are after |
| 1157 | * the 503 quirk in the quirk table, so they'll automatically |
| 1158 | * run and enable things like the SMBus device |
| 1159 | */ |
| 1160 | dev->device = devid; |
| 1161 | } |
| 1162 | |
| 1163 | static void __init quirk_sis_96x_compatible(struct pci_dev *dev) |
| 1164 | { |
| 1165 | sis_96x_compatible = 1; |
| 1166 | } |
| 1167 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible ); |
| 1168 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible ); |
| 1169 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible ); |
| 1170 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible ); |
| 1171 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible ); |
| 1172 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible ); |
| 1173 | |
| 1174 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); |
Bauke Jan Douma | e5548e9 | 2006-02-28 21:44:36 +0100 | [diff] [blame] | 1175 | /* |
| 1176 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller |
| 1177 | * and MC97 modem controller are disabled when a second PCI soundcard is |
| 1178 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. |
| 1179 | * -- bjd |
| 1180 | */ |
| 1181 | static void __init asus_hides_ac97_lpc(struct pci_dev *dev) |
| 1182 | { |
| 1183 | u8 val; |
| 1184 | int asus_hides_ac97 = 0; |
| 1185 | |
| 1186 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
| 1187 | if (dev->device == PCI_DEVICE_ID_VIA_8237) |
| 1188 | asus_hides_ac97 = 1; |
| 1189 | } |
| 1190 | |
| 1191 | if (!asus_hides_ac97) |
| 1192 | return; |
| 1193 | |
| 1194 | pci_read_config_byte(dev, 0x50, &val); |
| 1195 | if (val & 0xc0) { |
| 1196 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); |
| 1197 | pci_read_config_byte(dev, 0x50, &val); |
| 1198 | if (val & 0xc0) |
| 1199 | printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); |
| 1200 | else |
| 1201 | printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); |
| 1202 | } |
| 1203 | } |
| 1204 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); |
| 1205 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1206 | |
| 1207 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); |
| 1208 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); |
| 1209 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); |
| 1210 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); |
| 1211 | |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1212 | #if defined(CONFIG_SCSI_SATA) || defined(CONFIG_SCSI_SATA_MODULE) |
| 1213 | |
| 1214 | /* |
| 1215 | * If we are using libata we can drive this chip properly but must |
| 1216 | * do this early on to make the additional device appear during |
| 1217 | * the PCI scanning. |
| 1218 | */ |
| 1219 | |
| 1220 | static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev) |
| 1221 | { |
| 1222 | u32 conf; |
| 1223 | u8 hdr; |
| 1224 | |
| 1225 | /* Only poke fn 0 */ |
| 1226 | if (PCI_FUNC(pdev->devfn)) |
| 1227 | return; |
| 1228 | |
| 1229 | switch(pdev->device) { |
| 1230 | case PCI_DEVICE_ID_JMICRON_JMB365: |
| 1231 | case PCI_DEVICE_ID_JMICRON_JMB366: |
| 1232 | /* Redirect IDE second PATA port to the right spot */ |
| 1233 | pci_read_config_dword(pdev, 0x80, &conf); |
| 1234 | conf |= (1 << 24); |
| 1235 | /* Fall through */ |
| 1236 | pci_write_config_dword(pdev, 0x80, conf); |
| 1237 | case PCI_DEVICE_ID_JMICRON_JMB361: |
| 1238 | case PCI_DEVICE_ID_JMICRON_JMB363: |
| 1239 | pci_read_config_dword(pdev, 0x40, &conf); |
| 1240 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
| 1241 | /* Set the class codes correctly and then direct IDE 0 */ |
| 1242 | conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */ |
| 1243 | conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */ |
| 1244 | pci_write_config_dword(pdev, 0x40, conf); |
| 1245 | |
| 1246 | /* Reconfigure so that the PCI scanner discovers the |
| 1247 | device is now multifunction */ |
| 1248 | |
| 1249 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); |
| 1250 | pdev->hdr_type = hdr & 0x7f; |
| 1251 | pdev->multifunction = !!(hdr & 0x80); |
| 1252 | |
| 1253 | break; |
| 1254 | } |
| 1255 | } |
| 1256 | |
| 1257 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn); |
| 1258 | |
| 1259 | #endif |
| 1260 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1261 | #ifdef CONFIG_X86_IO_APIC |
| 1262 | static void __init quirk_alder_ioapic(struct pci_dev *pdev) |
| 1263 | { |
| 1264 | int i; |
| 1265 | |
| 1266 | if ((pdev->class >> 8) != 0xff00) |
| 1267 | return; |
| 1268 | |
| 1269 | /* the first BAR is the location of the IO APIC...we must |
| 1270 | * not touch this (and it's already covered by the fixmap), so |
| 1271 | * forcibly insert it into the resource tree */ |
| 1272 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) |
| 1273 | insert_resource(&iomem_resource, &pdev->resource[0]); |
| 1274 | |
| 1275 | /* The next five BARs all seem to be rubbish, so just clean |
| 1276 | * them out */ |
| 1277 | for (i=1; i < 6; i++) { |
| 1278 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); |
| 1279 | } |
| 1280 | |
| 1281 | } |
| 1282 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); |
| 1283 | #endif |
| 1284 | |
Jesse Barnes | 2bd0fa3 | 2005-12-13 03:05:03 -0500 | [diff] [blame] | 1285 | enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 }; |
| 1286 | /* Defaults to combined */ |
| 1287 | static enum ide_combined_type combined_mode; |
| 1288 | |
| 1289 | static int __init combined_setup(char *str) |
| 1290 | { |
| 1291 | if (!strncmp(str, "ide", 3)) |
| 1292 | combined_mode = IDE; |
| 1293 | else if (!strncmp(str, "libata", 6)) |
| 1294 | combined_mode = LIBATA; |
| 1295 | else /* "combined" or anything else defaults to old behavior */ |
| 1296 | combined_mode = COMBINED; |
| 1297 | |
| 1298 | return 1; |
| 1299 | } |
| 1300 | __setup("combined_mode=", combined_setup); |
| 1301 | |
Jeff Garzik | cc67523 | 2005-10-17 13:01:57 -0400 | [diff] [blame] | 1302 | #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1303 | static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) |
| 1304 | { |
| 1305 | u8 prog, comb, tmp; |
| 1306 | int ich = 0; |
| 1307 | |
| 1308 | /* |
| 1309 | * Narrow down to Intel SATA PCI devices. |
| 1310 | */ |
| 1311 | switch (pdev->device) { |
| 1312 | /* PCI ids taken from drivers/scsi/ata_piix.c */ |
| 1313 | case 0x24d1: |
| 1314 | case 0x24df: |
| 1315 | case 0x25a3: |
| 1316 | case 0x25b0: |
| 1317 | ich = 5; |
| 1318 | break; |
| 1319 | case 0x2651: |
| 1320 | case 0x2652: |
| 1321 | case 0x2653: |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 1322 | case 0x2680: /* ESB2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1323 | ich = 6; |
| 1324 | break; |
| 1325 | case 0x27c0: |
| 1326 | case 0x27c4: |
| 1327 | ich = 7; |
| 1328 | break; |
Jason Gaston | 012b265 | 2006-01-17 12:28:48 -0800 | [diff] [blame] | 1329 | case 0x2828: /* ICH8M */ |
| 1330 | ich = 8; |
| 1331 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1332 | default: |
| 1333 | /* we do not handle this PCI device */ |
| 1334 | return; |
| 1335 | } |
| 1336 | |
| 1337 | /* |
| 1338 | * Read combined mode register. |
| 1339 | */ |
| 1340 | pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ |
| 1341 | |
| 1342 | if (ich == 5) { |
| 1343 | tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ |
| 1344 | if (tmp == 0x4) /* bits 10x */ |
| 1345 | comb = (1 << 0); /* SATA port 0, PATA port 1 */ |
| 1346 | else if (tmp == 0x6) /* bits 11x */ |
| 1347 | comb = (1 << 2); /* PATA port 0, SATA port 1 */ |
| 1348 | else |
| 1349 | return; /* not in combined mode */ |
| 1350 | } else { |
Jason Gaston | 012b265 | 2006-01-17 12:28:48 -0800 | [diff] [blame] | 1351 | WARN_ON((ich != 6) && (ich != 7) && (ich != 8)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | tmp &= 0x3; /* interesting bits 1:0 */ |
| 1353 | if (tmp & (1 << 0)) |
| 1354 | comb = (1 << 2); /* PATA port 0, SATA port 1 */ |
| 1355 | else if (tmp & (1 << 1)) |
| 1356 | comb = (1 << 0); /* SATA port 0, PATA port 1 */ |
| 1357 | else |
| 1358 | return; /* not in combined mode */ |
| 1359 | } |
| 1360 | |
| 1361 | /* |
| 1362 | * Read programming interface register. |
| 1363 | * (Tells us if it's legacy or native mode) |
| 1364 | */ |
| 1365 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 1366 | |
| 1367 | /* if SATA port is in native mode, we're ok. */ |
| 1368 | if (prog & comb) |
| 1369 | return; |
| 1370 | |
Jesse Barnes | 2bd0fa3 | 2005-12-13 03:05:03 -0500 | [diff] [blame] | 1371 | /* Don't reserve any so the IDE driver can get them (but only if |
| 1372 | * combined_mode=ide). |
| 1373 | */ |
| 1374 | if (combined_mode == IDE) |
| 1375 | return; |
| 1376 | |
| 1377 | /* Grab them both for libata if combined_mode=libata. */ |
| 1378 | if (combined_mode == LIBATA) { |
| 1379 | request_region(0x1f0, 8, "libata"); /* port 0 */ |
| 1380 | request_region(0x170, 8, "libata"); /* port 1 */ |
| 1381 | return; |
| 1382 | } |
| 1383 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1384 | /* SATA port is in legacy mode. Reserve port so that |
| 1385 | * IDE driver does not attempt to use it. If request_region |
| 1386 | * fails, it will be obvious at boot time, so we don't bother |
| 1387 | * checking return values. |
| 1388 | */ |
| 1389 | if (comb == (1 << 0)) |
| 1390 | request_region(0x1f0, 8, "libata"); /* port 0 */ |
| 1391 | else |
| 1392 | request_region(0x170, 8, "libata"); /* port 1 */ |
| 1393 | } |
| 1394 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); |
Jeff Garzik | cc67523 | 2005-10-17 13:01:57 -0400 | [diff] [blame] | 1395 | #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1396 | |
| 1397 | |
| 1398 | int pcie_mch_quirk; |
| 1399 | |
| 1400 | static void __devinit quirk_pcie_mch(struct pci_dev *pdev) |
| 1401 | { |
| 1402 | pcie_mch_quirk = 1; |
| 1403 | } |
| 1404 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); |
| 1405 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); |
| 1406 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); |
| 1407 | |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1408 | |
| 1409 | /* |
| 1410 | * It's possible for the MSI to get corrupted if shpc and acpi |
| 1411 | * are used together on certain PXH-based systems. |
| 1412 | */ |
| 1413 | static void __devinit quirk_pcie_pxh(struct pci_dev *dev) |
| 1414 | { |
| 1415 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), |
| 1416 | PCI_CAP_ID_MSI); |
| 1417 | dev->no_msi = 1; |
| 1418 | |
| 1419 | printk(KERN_WARNING "PCI: PXH quirk detected, " |
| 1420 | "disabling MSI for SHPC device\n"); |
| 1421 | } |
| 1422 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); |
| 1423 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); |
| 1424 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); |
| 1425 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); |
| 1426 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); |
| 1427 | |
Kristen Carlson Accardi | ffadcc2 | 2006-07-12 08:59:00 -0700 | [diff] [blame] | 1428 | /* |
| 1429 | * Some Intel PCI Express chipsets have trouble with downstream |
| 1430 | * device power management. |
| 1431 | */ |
| 1432 | static void quirk_intel_pcie_pm(struct pci_dev * dev) |
| 1433 | { |
| 1434 | pci_pm_d3_delay = 120; |
| 1435 | dev->no_d1d2 = 1; |
| 1436 | } |
| 1437 | |
| 1438 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); |
| 1439 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); |
| 1440 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); |
| 1441 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); |
| 1442 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); |
| 1443 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); |
| 1444 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); |
| 1445 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); |
| 1446 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); |
| 1447 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); |
| 1448 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); |
| 1449 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); |
| 1450 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); |
| 1451 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); |
| 1452 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); |
| 1453 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); |
| 1454 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); |
| 1455 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); |
| 1456 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); |
| 1457 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); |
| 1458 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1459 | |
Kristen Accardi | c408a37 | 2006-01-17 16:57:04 -0800 | [diff] [blame] | 1460 | /* |
| 1461 | * Fixup the cardbus bridges on the IBM Dock II docking station |
| 1462 | */ |
| 1463 | static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev) |
| 1464 | { |
| 1465 | u32 val; |
| 1466 | |
| 1467 | /* |
| 1468 | * tie the 2 interrupt pins to INTA, and configure the |
| 1469 | * multifunction routing register to handle this. |
| 1470 | */ |
| 1471 | if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) && |
| 1472 | (dev->subsystem_device == 0x0148)) { |
| 1473 | printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge " |
| 1474 | "applying quirk\n"); |
| 1475 | pci_read_config_dword(dev, 0x8c, &val); |
| 1476 | val = ((val & 0xffffff00) | 0x1002); |
| 1477 | pci_write_config_dword(dev, 0x8c, val); |
| 1478 | pci_read_config_dword(dev, 0x80, &val); |
| 1479 | val = ((val & 0x00ffff00) | 0x2864c077); |
| 1480 | pci_write_config_dword(dev, 0x80, val); |
| 1481 | } |
| 1482 | } |
| 1483 | |
| 1484 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, |
| 1485 | quirk_ibm_dock2_cardbus); |
| 1486 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1487 | static void __devinit quirk_netmos(struct pci_dev *dev) |
| 1488 | { |
| 1489 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; |
| 1490 | unsigned int num_serial = dev->subsystem_device & 0xf; |
| 1491 | |
| 1492 | /* |
| 1493 | * These Netmos parts are multiport serial devices with optional |
| 1494 | * parallel ports. Even when parallel ports are present, they |
| 1495 | * are identified as class SERIAL, which means the serial driver |
| 1496 | * will claim them. To prevent this, mark them as class OTHER. |
| 1497 | * These combo devices should be claimed by parport_serial. |
| 1498 | * |
| 1499 | * The subdevice ID is of the form 0x00PS, where <P> is the number |
| 1500 | * of parallel ports and <S> is the number of serial ports. |
| 1501 | */ |
| 1502 | switch (dev->device) { |
| 1503 | case PCI_DEVICE_ID_NETMOS_9735: |
| 1504 | case PCI_DEVICE_ID_NETMOS_9745: |
| 1505 | case PCI_DEVICE_ID_NETMOS_9835: |
| 1506 | case PCI_DEVICE_ID_NETMOS_9845: |
| 1507 | case PCI_DEVICE_ID_NETMOS_9855: |
| 1508 | if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && |
| 1509 | num_parallel) { |
| 1510 | printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " |
| 1511 | "%u serial); changing class SERIAL to OTHER " |
| 1512 | "(use parport_serial)\n", |
| 1513 | dev->device, num_parallel, num_serial); |
| 1514 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | |
| 1515 | (dev->class & 0xff); |
| 1516 | } |
| 1517 | } |
| 1518 | } |
| 1519 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); |
| 1520 | |
Ivan Kokshaysky | a5312e2 | 2005-11-01 01:43:56 +0300 | [diff] [blame] | 1521 | |
| 1522 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) |
| 1523 | { |
| 1524 | /* rev 1 ncr53c810 chips don't set the class at all which means |
| 1525 | * they don't get their resources remapped. Fix that here. |
| 1526 | */ |
| 1527 | |
| 1528 | if (dev->class == PCI_CLASS_NOT_DEFINED) { |
| 1529 | printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); |
| 1530 | dev->class = PCI_CLASS_STORAGE_SCSI; |
| 1531 | } |
| 1532 | } |
| 1533 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); |
| 1534 | |
| 1535 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1536 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) |
| 1537 | { |
| 1538 | while (f < end) { |
| 1539 | if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && |
| 1540 | (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { |
| 1541 | pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); |
| 1542 | f->hook(dev); |
| 1543 | } |
| 1544 | f++; |
| 1545 | } |
| 1546 | } |
| 1547 | |
| 1548 | extern struct pci_fixup __start_pci_fixups_early[]; |
| 1549 | extern struct pci_fixup __end_pci_fixups_early[]; |
| 1550 | extern struct pci_fixup __start_pci_fixups_header[]; |
| 1551 | extern struct pci_fixup __end_pci_fixups_header[]; |
| 1552 | extern struct pci_fixup __start_pci_fixups_final[]; |
| 1553 | extern struct pci_fixup __end_pci_fixups_final[]; |
| 1554 | extern struct pci_fixup __start_pci_fixups_enable[]; |
| 1555 | extern struct pci_fixup __end_pci_fixups_enable[]; |
| 1556 | |
| 1557 | |
| 1558 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) |
| 1559 | { |
| 1560 | struct pci_fixup *start, *end; |
| 1561 | |
| 1562 | switch(pass) { |
| 1563 | case pci_fixup_early: |
| 1564 | start = __start_pci_fixups_early; |
| 1565 | end = __end_pci_fixups_early; |
| 1566 | break; |
| 1567 | |
| 1568 | case pci_fixup_header: |
| 1569 | start = __start_pci_fixups_header; |
| 1570 | end = __end_pci_fixups_header; |
| 1571 | break; |
| 1572 | |
| 1573 | case pci_fixup_final: |
| 1574 | start = __start_pci_fixups_final; |
| 1575 | end = __end_pci_fixups_final; |
| 1576 | break; |
| 1577 | |
| 1578 | case pci_fixup_enable: |
| 1579 | start = __start_pci_fixups_enable; |
| 1580 | end = __end_pci_fixups_enable; |
| 1581 | break; |
| 1582 | |
| 1583 | default: |
| 1584 | /* stupid compiler warning, you would think with an enum... */ |
| 1585 | return; |
| 1586 | } |
| 1587 | pci_do_fixups(dev, start, end); |
| 1588 | } |
| 1589 | |
Daniel Yeisley | 9d26512 | 2005-12-05 07:06:43 -0500 | [diff] [blame] | 1590 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
| 1591 | static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) |
| 1592 | { |
| 1593 | u16 en1k; |
| 1594 | u8 io_base_lo, io_limit_lo; |
| 1595 | unsigned long base, limit; |
| 1596 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; |
| 1597 | |
| 1598 | pci_read_config_word(dev, 0x40, &en1k); |
| 1599 | |
| 1600 | if (en1k & 0x200) { |
| 1601 | printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); |
| 1602 | |
| 1603 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); |
| 1604 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); |
| 1605 | base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; |
| 1606 | limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; |
| 1607 | |
| 1608 | if (base <= limit) { |
| 1609 | res->start = base; |
| 1610 | res->end = limit + 0x3ff; |
| 1611 | } |
| 1612 | } |
| 1613 | } |
| 1614 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); |
| 1615 | |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1616 | /* Under some circumstances, AER is not linked with extended capabilities. |
| 1617 | * Force it to be linked by setting the corresponding control bit in the |
| 1618 | * config space. |
| 1619 | */ |
| 1620 | static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
| 1621 | { |
| 1622 | uint8_t b; |
| 1623 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { |
| 1624 | if (!(b & 0x20)) { |
| 1625 | pci_write_config_byte(dev, 0xf41, b | 0x20); |
| 1626 | printk(KERN_INFO |
| 1627 | "PCI: Linking AER extended capability on %s\n", |
| 1628 | pci_name(dev)); |
| 1629 | } |
| 1630 | } |
| 1631 | } |
| 1632 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
| 1633 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
| 1634 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1635 | EXPORT_SYMBOL(pcie_mch_quirk); |
| 1636 | #ifdef CONFIG_HOTPLUG |
| 1637 | EXPORT_SYMBOL(pci_fixup_device); |
| 1638 | #endif |