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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 393ffddae8176428814767ac42279db1f224d41b / . / arch / arm / boot / dts / dsi-v2-panel-truly-wvga-cmd.dtsi
blob: fd8d2183ecd0849fbbed19c62a1b820926bf46dc [file] [log] [blame]
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Xiaoming Zhou7004fe22013-08-01 17:54:54 -0400[diff] [blame]13&soc {
Xiaoming Zhou4ca7e9a2013-08-01 17:56:51 -0400[diff] [blame]14 qcom,dsi_v2_truly_wvga_cmd {
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]15 compatible = "qcom,dsi-panel-v2";
16 label = "Truly WVGA command mode dsi panel";
17 qcom,dsi-ctrl-phandle = <&mdss_dsi0>;
18 qcom,rst-gpio = <&msmgpio 41 0>;
19 qcom,mode-selection-gpio = <&msmgpio 7 0>;
20 qcom,te-gpio = <&msmgpio 12 0>;
21 vdda-supply = <&pm8110_l19>;
22 vddio-supply=<&pm8110_l14>;
23 qcom,mdss-pan-res = <480 800>;
24 qcom,mdss-pan-bpp = <24>;
25 qcom,mdss-pan-dest = "display_1";
26 qcom,mdss-pan-porch-values = <40 8 160 10 2 12>;
27 qcom,mdss-pan-underflow-clr = <0xff>;
28 qcom,mdss-pan-bl-levels = <1 255>;
29 qcom,mdss-pan-bl-ctrl = "bl_ctrl_wled";
30 qcom,mdss-pan-dsi-mode = <1>;
31 qcom,mdss-pan-dsi-h-pulse-mode = <0>;
32 qcom,mdss-pan-dsi-h-power-stop = <0 0 0>;
33 qcom,mdss-pan-dsi-bllp-power-stop = <1 1>;
34 qcom,mdss-pan-dsi-traffic-mode = <1>;
35 qcom,mdss-pan-dsi-dst-format = <8>;
36 qcom,mdss-pan-insert-dcs-cmd = <1>;
37 qcom,mdss-pan-wr-mem-continue = <0x3c>;
38 qcom,mdss-pan-wr-mem-start = <0x2c>;
39 qcom,mdss-pan-dsi-vc = <0>;
40 qcom,mdss-pan-dsi-rgb-swap = <0>;
41 qcom,mdss-pan-dsi-data-lanes = <1 1 0 0>;
42 qcom,mdss-pan-dsi-dlane-swap = <0>;
43 qcom,mdss-pan-dsi-t-clk = <0x1b 0x04>;
44 qcom,mdss-pan-dsi-stream = <0>;
45 qcom,mdss-pan-dsi-mdp-tr = <0x02>;
46 qcom,mdss-pan-dsi-dma-tr = <0x04>;
47 qcom,mdss-pan-dsi-frame-rate = <60>;
48 qcom,panel-phy-regulatorSettings =[02 08 05 00 20 03];
49 qcom,panel-phy-timingSettings = [5D 12 0C 00 33 38
50 10 16 1E 03 04 00];
51 qcom,panel-phy-strengthCtrl = [ff 06];
52 qcom,panel-phy-bistCtrl = [03 03 00 00 0f 00];
53 qcom,panel-phy-laneConfig =
54 [80 45 00 00 01 66 /*lane0**/
55 80 45 00 00 01 66 /*lane1*/
56 80 45 00 00 01 66 /*lane2*/
57 80 45 00 00 01 66 /*lane3*/
58 40 67 00 00 01 88]; /*Clk*/
59
60 qcom,on-cmds-dsi-state = "DSI_LP_MODE";
61 qcom,panel-on-cmds = [
62 05 01 00 00 00 02
63 01 00
64 23 01 00 00 00 02
65 b0 04
66 29 01 00 00 00 03
67 b3 02 00
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]68 29 01 00 00 00 03
69 b6 51 83
70 29 01 00 00 00 05
71 b7 00 80 15 25
72 29 01 00 00 00 14
73 b8 00 07 07 ff c8 c8 01 18 10 10
74 37 5a 87 de ff 00 00 00 00
75 29 01 00 00 00 05
76 b9 00 00 00 00
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]77 23 01 00 00 00 02
78 bd 00
79 29 01 00 00 00 03
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]80 c0 02 43
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]81 29 01 00 00 00 10
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]82 c1 43 31 99 21 20 00 10 28 0c 0c
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]83 00 00 00 21 01
84 29 01 00 00 00 07
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]85 c2 28 06 06 01 03 00
86 29 01 00 00 00 04
87 c3 40 00 03
88 29 01 00 00 00 03
89 6f 03 00
90 29 01 00 00 00 03
91 c4 00 01
92 29 01 00 00 00 03
93 c6 00 00
94 29 01 00 00 00 06
95 c7 11 8d a0 f5 27
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]96 29 01 00 00 00 19
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]97 c8 01 0a 12 1c 2b 45 3f 29 17 13
98 0f 04 01 0a 12 1c 2b 45 3f 29 17 13 0f 04
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]99 29 01 00 00 00 19
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]100 c9 01 0a 12 1c 2b 45 3f 29 17 13
101 0f 04 01 0a 12 1c 2b 45 3f 29 17 13 0f 04
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]102 29 01 00 00 00 19
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]103 ca 01 0a 12 1c 2b 45 3f 29 17 13
104 0f 04 01 0a 12 1c 2b 45 3f 29 17 13 0f 04
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]105 29 01 00 00 00 11
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]106 d0 99 03 ce a6 00 43 20 10 01 00
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]107 01 01 00 03 01 00
108 29 01 00 00 00 08
109 d1 18 0C 23 03 75 02 50
110 23 01 00 00 00 02
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]111 d3 33
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]112 29 01 00 00 00 03
113 d5 2a 2a
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]114 29 01 00 00 00 02
115 d6 28
116 29 01 00 00 00 10
117 d7 01 00 aa c0 2a 2c 22 12 71 0a 12 00 a0
118 00 03
119 29 01 00 00 00 09
120 d8 44 44 22 44 21 46 42 40
121 29 01 00 00 00 04
122 d9 cf 2d 51
123 29 01 00 00 00 02
124 da 01
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]125 29 01 00 00 00 03
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]126 de 01 4f
127 29 01 00 00 00 07
128 e1 00 00 00 00 00 00
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]129 23 01 00 00 00 02
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]130 e6 4f
131 29 01 00 00 00 06
132 f3 06 00 00 24 00
133 29 01 00 00 00 02
134 f8 00
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]135 23 01 00 00 00 02
136 fa 03
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]137 29 01 00 00 00 04
138 fb 00 00 00
139 29 01 00 00 00 06
140 fc 00 00 00 00 00
141 29 01 00 00 00 05
142 fd 00 00 70 00
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]143 39 01 00 00 00 05
144 2a 00 00 01 df
145 39 01 00 00 00 05
146 2b 00 00 03 1f
147 15 01 00 00 00 02
148 35 00
149 39 01 00 00 00 03
150 44 00 50
151 15 01 00 00 00 02
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]152 36 41
153 15 01 00 00 00 02
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]154 3a 77
155 05 01 00 00 7D 02
156 11 00
Xiaoming Zhou9fa91e62013-07-29 16:33:55 -0400[diff] [blame]157 05 01 00 00 3c 02
Xiaoming Zhou8c2c9fb2013-05-24 16:50:39 -0400[diff] [blame]158 29 00
159 ];
160 qcom,panel-off-cmds = [05 01 00 00 32 02 28 00
161 05 01 00 00 78 02 10 00];
162 qcom,off-cmds-dsi-state = "DSI_LP_MODE";
163 };
164};