blob: fad9d8631b56aa565f2436467b2a1887d50677f6 [file] [log] [blame]
Siddartha Mohanadoss6dec7cee32013-05-02 10:02:51 -07001/* Copyright (c) 2012-2013, Linux Foundation. All rights reserved.
David Collinsa2b73f22012-09-13 17:32:16 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&spmi_bus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 interrupt-controller;
17 #interrupt-cells = <3>;
18
19 qcom,pm8019@0 {
20 spmi-slave-container;
21 reg = <0x0>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24
Mohan Pallaka96865222012-09-28 10:21:49 +053025 qcom,power_on@800 {
26 compatible = "qcom,qpnp-power-on";
27 reg = <0x800 0x100>;
28 interrupts = <0x0 0x8 0x2>;
29 interrupt-names = "cblpwr";
30 qcom,pon-dbc-delay = <15625>;
31 qcom,system-reset;
32
33 qcom,pon_1 {
34 qcom,pon-type = <2>;
35 qcom,pull-up = <1>;
36 linux,code = <116>;
37 };
38 };
39
David Collinsa2b73f22012-09-13 17:32:16 -070040 clkdiv@5b00 {
41 reg = <0x5b00 0x100>;
42 compatible = "qcom,qpnp-clkdiv";
43 qcom,cxo-freq = <19200000>;
44 };
45
46 clkdiv@5c00 {
47 reg = <0x5c00 0x100>;
48 compatible = "qcom,qpnp-clkdiv";
49 qcom,cxo-freq = <19200000>;
50 };
51
52 clkdiv@5d00 {
53 reg = <0x5d00 0x100>;
54 compatible = "qcom,qpnp-clkdiv";
55 qcom,cxo-freq = <19200000>;
56 };
57
58 rtc {
59 spmi-dev-container;
60 compatible = "qcom,qpnp-rtc";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 qcom,qpnp-rtc-write = <0>;
64 qcom,qpnp-rtc-alarm-pwrup = <0>;
65
66 qcom,pm8019_rtc_rw@6000 {
67 reg = <0x6000 0x100>;
68 };
69
70 qcom,pm8019_rtc_alarm@6100 {
71 reg = <0x6100 0x100>;
72 interrupts = <0x0 0x61 0x1>;
73 };
74 };
75
76 pm8019_gpios: gpios {
77 spmi-dev-container;
78 compatible = "qcom,qpnp-pin";
79 gpio-controller;
80 #gpio-cells = <2>;
81 #address-cells = <1>;
82 #size-cells = <1>;
83 label = "pm8019-gpio";
84
85 gpio@c000 {
86 reg = <0xc000 0x100>;
87 qcom,pin-num = <1>;
88 };
89
90 gpio@c100 {
91 reg = <0xc100 0x100>;
92 qcom,pin-num = <2>;
93 };
94
95 gpio@c200 {
96 reg = <0xc200 0x100>;
97 qcom,pin-num = <3>;
98 };
99
100 gpio@c300 {
101 reg = <0xc300 0x100>;
102 qcom,pin-num = <4>;
103 };
104
105 gpio@c400 {
106 reg = <0xc400 0x100>;
107 qcom,pin-num = <5>;
108 };
109
110 gpio@c500 {
111 reg = <0xc500 0x100>;
112 qcom,pin-num = <6>;
113 };
114 };
115
116 pm8019_mpps: mpps {
117 spmi-dev-container;
118 compatible = "qcom,qpnp-pin";
119 gpio-controller;
120 #gpio-cells = <2>;
121 #address-cells = <1>;
122 #size-cells = <1>;
123 label = "pm8019-mpp";
124
125 mpp@a000 {
126 reg = <0xa000 0x100>;
127 qcom,pin-num = <1>;
128 };
129
130 mpp@a100 {
131 reg = <0xa100 0x100>;
132 qcom,pin-num = <2>;
133 };
134
135 mpp@a200 {
136 reg = <0xa200 0x100>;
137 qcom,pin-num = <3>;
138 };
139
140 mpp@a300 {
141 reg = <0xa300 0x100>;
142 qcom,pin-num = <4>;
143 };
144
145 mpp@a400 {
146 reg = <0xa400 0x100>;
147 qcom,pin-num = <5>;
148 };
149
150 mpp@a500 {
151 reg = <0xa500 0x100>;
152 qcom,pin-num = <6>;
153 };
154 };
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700155
156 pm8019_vadc: vadc@3100 {
157 compatible = "qcom,qpnp-vadc";
158 reg = <0x3100 0x100>;
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800159 #address-cells = <1>;
160 #size-cells = <0>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700161 interrupts = <0x0 0x31 0x0>;
Siddartha Mohanadossbe9f6a72013-01-31 12:09:44 -0800162 interrupt-names = "eoc-int-en-set";
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700163 qcom,adc-bit-resolution = <15>;
164 qcom,adc-vdd-reference = <1800>;
165
166 chan@8 {
167 label = "die_temp";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800168 reg = <8>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700169 qcom,decimation = <0>;
170 qcom,pre-div-channel-scaling = <0>;
171 qcom,calibration-type = "absolute";
172 qcom,scale-function = <3>;
173 qcom,hw-settle-time = <0>;
174 qcom,fast-avg-setup = <0>;
175 };
176
177 chan@9 {
178 label = "ref_625mv";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800179 reg = <9>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700180 qcom,decimation = <0>;
181 qcom,pre-div-channel-scaling = <0>;
182 qcom,calibration-type = "absolute";
183 qcom,scale-function = <0>;
184 qcom,hw-settle-time = <0>;
185 qcom,fast-avg-setup = <0>;
186 };
187
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800188 chan@a {
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700189 label = "ref_1250v";
Siddartha Mohanadoss96be0a02012-12-07 14:38:48 -0800190 reg = <0xa>;
Siddartha Mohanadossc47fcce2012-09-25 17:21:50 -0700191 qcom,decimation = <0>;
192 qcom,pre-div-channel-scaling = <0>;
193 qcom,calibration-type = "absolute";
194 qcom,scale-function = <0>;
195 qcom,hw-settle-time = <0>;
196 qcom,fast-avg-setup = <0>;
197 };
198 };
Siddartha Mohanadoss6dec7cee32013-05-02 10:02:51 -0700199
200 pm8019_adc_tm: vadc@3400 {
201 compatible = "qcom,qpnp-adc-tm";
202 reg = <0x3400 0x100>;
203 #address-cells = <1>;
204 #size-cells = <0>;
205 interrupts = <0x0 0x34 0x0>,
206 <0x0 0x34 0x3>,
207 <0x0 0x34 0x4>;
208 interrupt-names = "eoc-int-en-set",
209 "high-thr-en-set",
210 "low-thr-en-set";
211 qcom,adc-bit-resolution = <15>;
212 qcom,adc-vdd-reference = <1800>;
213 };
David Collinsa2b73f22012-09-13 17:32:16 -0700214 };
215
216 qcom,pm8019@1 {
217 spmi-slave-container;
218 reg = <0x1>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221
222 regulator@1400 {
223 regulator-name = "8019_s1";
224 spmi-dev-container;
225 #address-cells = <1>;
226 #size-cells = <1>;
227 compatible = "qcom,qpnp-regulator";
228 reg = <0x1400 0x300>;
229 status = "disabled";
230
231 qcom,ctl@1400 {
232 reg = <0x1400 0x100>;
233 };
234 qcom,ps@1500 {
235 reg = <0x1500 0x100>;
236 };
237 qcom,freq@1600 {
238 reg = <0x1600 0x100>;
239 };
240 };
241
242 regulator@1700 {
243 regulator-name = "8019_s2";
244 spmi-dev-container;
245 #address-cells = <1>;
246 #size-cells = <1>;
247 compatible = "qcom,qpnp-regulator";
248 reg = <0x1700 0x300>;
249 status = "disabled";
250
251 qcom,ctl@1700 {
252 reg = <0x1700 0x100>;
253 };
254 qcom,ps@1800 {
255 reg = <0x1800 0x100>;
256 };
257 qcom,freq@1900 {
258 reg = <0x1900 0x100>;
259 };
260 };
261
262 regulator@1a00 {
263 regulator-name = "8019_s3";
264 spmi-dev-container;
265 #address-cells = <1>;
266 #size-cells = <1>;
267 compatible = "qcom,qpnp-regulator";
268 reg = <0x1a00 0x300>;
269 status = "disabled";
270
271 qcom,ctl@1a00 {
272 reg = <0x1a00 0x100>;
273 };
274 qcom,ps@1b00 {
275 reg = <0x1b00 0x100>;
276 };
277 qcom,freq@1c00 {
278 reg = <0x1c00 0x100>;
279 };
280 };
281
282 regulator@1d00 {
283 regulator-name = "8019_s4";
284 spmi-dev-container;
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "qcom,qpnp-regulator";
288 reg = <0x1d00 0x300>;
289 status = "disabled";
290
291 qcom,ctl@1d00 {
292 reg = <0x1d00 0x100>;
293 };
294 qcom,ps@1e00 {
295 reg = <0x1e00 0x100>;
296 };
297 qcom,freq@1f00 {
298 reg = <0x1f00 0x100>;
299 };
300 };
301
302 regulator@4000 {
303 regulator-name = "8019_l1";
304 reg = <0x4000 0x100>;
305 compatible = "qcom,qpnp-regulator";
306 status = "disabled";
307 };
308
309 regulator@4100 {
310 regulator-name = "8019_l2";
311 reg = <0x4100 0x100>;
312 compatible = "qcom,qpnp-regulator";
313 status = "disabled";
314 };
315
316 regulator@4200 {
317 regulator-name = "8019_l3";
318 reg = <0x4200 0x100>;
319 compatible = "qcom,qpnp-regulator";
320 status = "disabled";
321 };
322
323 regulator@4300 {
324 regulator-name = "8019_l4";
325 reg = <0x4300 0x100>;
326 compatible = "qcom,qpnp-regulator";
327 status = "disabled";
328 };
329
330 regulator@4400 {
331 regulator-name = "8019_l5";
332 reg = <0x4400 0x100>;
333 compatible = "qcom,qpnp-regulator";
334 status = "disabled";
335 };
336
337 regulator@4500 {
338 regulator-name = "8019_l6";
339 reg = <0x4500 0x100>;
340 compatible = "qcom,qpnp-regulator";
341 status = "disabled";
342 };
343
344 regulator@4600 {
345 regulator-name = "8019_l7";
346 reg = <0x4600 0x100>;
347 compatible = "qcom,qpnp-regulator";
348 status = "disabled";
349 };
350
351 regulator@4700 {
352 regulator-name = "8019_l8";
353 reg = <0x4700 0x100>;
354 compatible = "qcom,qpnp-regulator";
355 status = "disabled";
356 };
357
358 regulator@4800 {
359 regulator-name = "8019_l9";
360 reg = <0x4800 0x100>;
361 compatible = "qcom,qpnp-regulator";
362 status = "disabled";
363 };
364
365 regulator@4900 {
366 regulator-name = "8019_l10";
367 reg = <0x4900 0x100>;
368 compatible = "qcom,qpnp-regulator";
369 status = "disabled";
370 };
371
372 regulator@4a00 {
373 regulator-name = "8019_l11";
374 reg = <0x4a00 0x100>;
375 compatible = "qcom,qpnp-regulator";
376 status = "disabled";
377 };
378
379 regulator@4b00 {
380 regulator-name = "8019_l12";
381 reg = <0x4b00 0x100>;
382 compatible = "qcom,qpnp-regulator";
383 status = "disabled";
384 };
385
386 regulator@4c00 {
387 regulator-name = "8019_l13";
388 reg = <0x4c00 0x100>;
389 compatible = "qcom,qpnp-regulator";
390 status = "disabled";
391 };
392
393 regulator@4d00 {
394 regulator-name = "8019_l14";
395 reg = <0x4d00 0x100>;
396 compatible = "qcom,qpnp-regulator";
397 status = "disabled";
398 };
399
400 regulator@4e00 {
401 regulator-name = "8019_ldo_xo";
402 reg = <0x4e00 0x100>;
403 compatible = "qcom,qpnp-regulator";
404 status = "disabled";
405 };
406
407 regulator@4f00 {
408 regulator-name = "8019_ldo_rfclk";
409 reg = <0x4f00 0x100>;
410 compatible = "qcom,qpnp-regulator";
411 status = "disabled";
412 };
413 };
414};