arch/arm/boot/dts/msmsamarium.dtsi

/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/include/ "skeleton.dtsi"

/ {
	model = "Qualcomm MSM SAMARIUM";
	compatible = "qcom,msmsamarium";
	interrupt-parent = <&intc>;
	soc: soc { };
};

/include/ "msmsamarium-ion.dtsi"
/include/ "msmsamarium-smp2p.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	intc: interrupt-controller@f9000000 {
		compatible = "qcom,msm-qgic2";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0xf9000000 0x1000>,
		      <0xf9002000 0x1000>;
	};

	msmgpio: gpio@fd510000 {
		compatible = "qcom,msm-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		reg = <0xfd510000 0x4000>;
		ngpio = <146>;
		interrupts = <0 208 0>;
		qcom,direct-connect-irqs = <8>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0 1 3 0>;
		clock-frequency = <19200000>;
	};

	uartblsp0dm2: serial@f991f000 {
		compatible = "qcom,msm-lsuart-v14";
		reg = <0xf991f000 0x1000>;
		interrupts = <0 109 0>;
		status = "disabled";
	};

	qcom,msm-imem@fe805000 {
		compatible = "qcom,msm-imem";
		reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
	};

	rmtfs_sharedmem {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0fd80000 0x00180000>;
		reg-names = "rmtfs";
	};

	dsp_sharedmem {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0fd60000 0x00020000>;
		reg-names = "rfsa_dsp";
	};

	mdm_sharedmem {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0fd60000 0x00020000>;
		reg-names = "rfsa_mdm";
	};

	sdcc1: qcom,sdcc@f9824000 {
		cell-index = <1>; /* SDC1 eMMC slot */
		compatible = "qcom,msm-sdcc";
		reg = <0xf9824000 0x800>;
		reg-names = "core_mem";
		interrupts = <0 123 0>;
		interrupt-names = "core_irq";

		qcom,bus-width = <8>;
		status = "disabled";
	};

	sdcc2: qcom,sdcc@f98a4000 {
		cell-index = <2>; /* SDC2 SD card slot */
		compatible = "qcom,msm-sdcc";
		reg = <0xf98a4000 0x800>;
		reg-names = "core_mem";
		interrupts = <0 125 0>;
		interrupt-names = "core_irq";

		qcom,bus-width = <4>;
		status = "disabled";
	};

	qcom,sps@f9980000 {
		compatible = "qcom,msm_sps";
		reg = <0xf9984000 0x15000>,
		      <0xf9999000 0xb000>;
		reg-names = "bam_mem", "core_mem";
		interrupts = <0 94 0>;
	};

	qcom,wdt@f9017000 {
		compatible = "qcom,msm-watchdog";
		reg = <0xf9017000 0x1000>;
		interrupts = <0 3 0>, <0 4 0>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <10000>;
		qcom,ipi-ping;
	};

	qcom,msm-mem-hole {
		compatible = "qcom,msm-mem-hole";
		qcom,memblock-remove = <0x07f00000 0x8000000>; /* Address and size of hole */
	};

	qcom,ipc-spinlock@fd484000 {
		compatible = "qcom,ipc-spinlock-sfpb";
		reg = <0xfd484000 0x400>;
		qcom,num-locks = <8>;
	};

	qcom,smem@fa00000 {
		compatible = "qcom,smem";
		reg = <0xfa00000 0x200000>,
			<0xf9011000 0x1000>,
			<0xfc428000 0x4000>;
		reg-names = "smem", "irq-reg-base", "aux-mem1";

		qcom,smd-modem {
			compatible = "qcom,smd";
			qcom,smd-edge = <0>;
			qcom,smd-irq-offset = <0x8>;
			qcom,smd-irq-bitmask = <0x1000>;
			qcom,pil-string = "modem";
			interrupts = <0 25 1>;
		};

		qcom,smsm-modem {
			compatible = "qcom,smsm";
			qcom,smsm-edge = <0>;
			qcom,smsm-irq-offset = <0x8>;
			qcom,smsm-irq-bitmask = <0x2000>;
			interrupts = <0 26 1>;
		};

		qcom,smd-adsp {
			compatible = "qcom,smd";
			qcom,smd-edge = <1>;
			qcom,smd-irq-offset = <0x8>;
			qcom,smd-irq-bitmask = <0x100>;
			qcom,pil-string = "adsp";
			interrupts = <0 156 1>;
		};

		qcom,smsm-adsp {
			compatible = "qcom,smsm";
			qcom,smsm-edge = <1>;
			qcom,smsm-irq-offset = <0x8>;
			qcom,smsm-irq-bitmask = <0x200>;
			interrupts = <0 157 1>;
		};

		qcom,smd-wcnss {
			compatible = "qcom,smd";
			qcom,smd-edge = <6>;
			qcom,smd-irq-offset = <0x8>;
			qcom,smd-irq-bitmask = <0x20000>;
			qcom,pil-string = "wcnss";
			interrupts = <0 142 1>;
		};

		qcom,smsm-wcnss {
			compatible = "qcom,smsm";
			qcom,smsm-edge = <6>;
			qcom,smsm-irq-offset = <0x8>;
			qcom,smsm-irq-bitmask = <0x80000>;
			interrupts = <0 144 1>;
		};

		qcom,smd-rpm {
			compatible = "qcom,smd";
			qcom,smd-edge = <15>;
			qcom,smd-irq-offset = <0x8>;
			qcom,smd-irq-bitmask = <0x1>;
			interrupts = <0 168 1>;
			qcom,irq-no-suspend;
		};
	};

	android_usb@fe8050c8 {
		compatible = "qcom,android-usb";
		reg = <0xfe8050c8 0xc8>;
		qcom,android-usb-swfi-latency = <1>;
	};

	usb_otg: usb@f9a55000 {
		compatible = "qcom,hsusb-otg";
		status = "disabled";

		reg = <0xf9a55000 0x400>;
		interrupts = <0 134 0>, <0 140 0>;
		interrupt-names = "core_irq", "async_irq";
		HSUSB_VDDCX-supply = "";
		HSUSB_1p8-supply = "";
		HSUSB_3p3-supply = "";
		qcom,vdd-voltage-level = <1 5 7>;

		qcom,hsusb-otg-phy-type = <2>;
		qcom,hsusb-otg-phy-init-seq =
			<0x44 0x80 0x68 0x81 0x24 0x82 0x13 0x83 0xffffffff>;
		qcom,hsusb-otg-mode = <1>;
		qcom,hsusb-otg-otg-control = <1>;
		qcom,hsusb-otg-disable-reset;

		qcom,msm-bus,name = "usb2";
		qcom,msm-bus,num-cases = <3>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<87 512 0 0>,
				<87 512 60000 960000>,
				<87 512 6000  6000>;
	};

	qcom,bam_dmux@fc834000 {
		compatible = "qcom,bam_dmux";
		reg = <0xfc834000 0x7000>;
		interrupts = <0 29 1>;
		qcom,rx-ring-size = <64>;
	};

	spmi_bus: qcom,spmi@fc4c0000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xfc4cf000 0x1000>,
		      <0Xfc4cb000 0x1000>,
		      <0Xfc4ca000 0x1000>;
		reg-names = "core", "intr", "cnfg";
		interrupts = <0 190 0>;
		qcom,pmic-arb-channel = <0>;
		qcom,pmic-arb-ee = <0>;
		#interrupt-cells = <3>;
		interrupt-controller;
		#address-cells = <1>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,not-wakeup;     /* Needed until MPM is fully configured. */
	};

	tsens: tsens@fc4a8000 {
		compatible = "qcom,msm-tsens";
		reg = <0xfc4a8000 0x2000>,
		      <0xfc4bc000 0x1000>;
		reg-names = "tsens_physical", "tsens_eeprom_physical";
		interrupts = <0 184 0>;
		qcom,sensors = <11>;
		qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
				3200 3200>;
		qcom,calib-mode = "fuse_map1";
	};
};

/include/ "msm-pma8084.dtsi"
/include/ "msmsamarium-regulator.dtsi"