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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 393ffddae8176428814767ac42279db1f224d41b / . / arch / arm / boot / dts / omap3.dtsi
blob: c6121357c1ebc95c29dd29e76f78d9972441e216 [file] [log] [blame]
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap3430", "ti,omap3";
15
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 };
22
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]23 cpus {
24 cpu@0 {
25 compatible = "arm,cortex-a8";
26 };
27 };
28
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]29 /*
30 * The soc node represents the soc top level view. It is uses for IPs
31 * that are not memory mapped in the MPU view or for the MPU itself.
32 */
33 soc {
34 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]35 mpu {
36 compatible = "ti,omap3-mpu";
37 ti,hwmods = "mpu";
38 };
39
40 iva {
41 compatible = "ti,iva2.2";
42 ti,hwmods = "iva";
43
44 dsp {
45 compatible = "ti,omap3-c64";
46 };
47 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]48 };
49
50 /*
51 * XXX: Use a flat representation of the OMAP3 interconnect.
52 * The real OMAP interconnect network is quite complex.
53 * Since that will not bring real advantage to represent that in DT for
54 * the moment, just use a fake OCP bus entry to represent the whole bus
55 * hierarchy.
56 */
57 ocp {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62 ti,hwmods = "l3_main";
63
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]64 intc: interrupt-controller@48200000 {
65 compatible = "ti,omap2-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]66 interrupt-controller;
67 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]68 ti,intc-size = <96>;
69 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]70 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]71
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]72 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]73 compatible = "ti,omap3-uart";
74 ti,hwmods = "uart1";
75 clock-frequency = <48000000>;
76 };
77
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]78 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]79 compatible = "ti,omap3-uart";
80 ti,hwmods = "uart2";
81 clock-frequency = <48000000>;
82 };
83
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]84 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]85 compatible = "ti,omap3-uart";
86 ti,hwmods = "uart3";
87 clock-frequency = <48000000>;
88 };
89
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]90 uart4: serial@49042000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]91 compatible = "ti,omap3-uart";
92 ti,hwmods = "uart4";
93 clock-frequency = <48000000>;
94 };
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]95
96 i2c1: i2c@48070000 {
97 compatible = "ti,omap3-i2c";
98 #address-cells = <1>;
99 #size-cells = <0>;
100 ti,hwmods = "i2c1";
101 };
102
103 i2c2: i2c@48072000 {
104 compatible = "ti,omap3-i2c";
105 #address-cells = <1>;
106 #size-cells = <0>;
107 ti,hwmods = "i2c2";
108 };
109
110 i2c3: i2c@48060000 {
111 compatible = "ti,omap3-i2c";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 ti,hwmods = "i2c3";
115 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]116 };
117};