blob: 2dcff8728e904a03dc5ba1200b633617e2c9b048 [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Peter De Schrijveradd29e62011-10-12 14:53:05 +03003/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Ventana evaluation board";
7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 memory {
10 reg = < 0x00000000 0x40000000 >;
11 };
12
Stephen Warren88950f32011-11-21 14:44:09 -070013 i2c@7000c000 {
14 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -070015
16 wm8903: wm8903@1a {
17 compatible = "wlf,wm8903";
18 reg = <0x1a>;
19 interrupt-parent = <&gpio>;
20 interrupts = < 187 0x04 >;
21
22 gpio-controller;
23 #gpio-cells = <2>;
24
25 micdet-cfg = <0>;
26 micdet-delay = <100>;
27 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
28 };
Stephen Warren88950f32011-11-21 14:44:09 -070029 };
30
31 i2c@7000c400 {
32 clock-frequency = <400000>;
33 };
34
35 i2c@7000c500 {
36 clock-frequency = <400000>;
37 };
38
39 i2c@7000d000 {
40 clock-frequency = <400000>;
41 };
42
Stephen Warren797acf72012-01-11 16:09:57 -070043 i2s@70002a00 {
44 status = "disable";
45 };
46
47 sound {
48 compatible = "nvidia,tegra-audio-wm8903-ventana",
49 "nvidia,tegra-audio-wm8903";
50 nvidia,model = "NVIDIA Tegra Ventana";
51
52 nvidia,audio-routing =
53 "Headphone Jack", "HPOUTR",
54 "Headphone Jack", "HPOUTL",
55 "Int Spk", "ROP",
56 "Int Spk", "RON",
57 "Int Spk", "LOP",
58 "Int Spk", "LON",
59 "Mic Jack", "MICBIAS",
60 "IN1L", "Mic Jack";
61
62 nvidia,i2s-controller = <&tegra_i2s1>;
63 nvidia,audio-codec = <&wm8903>;
64
65 nvidia,spkr-en-gpios = <&wm8903 2 0>;
66 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
67 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
68 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
69 };
70
Stephen Warren31c1ec92011-11-21 14:44:10 -070071 serial@70006000 {
72 status = "disable";
73 };
74
75 serial@70006040 {
76 status = "disable";
77 };
78
79 serial@70006200 {
80 status = "disable";
81 };
82
Peter De Schrijveradd29e62011-10-12 14:53:05 +030083 serial@70006300 {
84 clock-frequency = < 216000000 >;
85 };
86
Stephen Warren31c1ec92011-11-21 14:44:10 -070087 serial@70006400 {
88 status = "disable";
89 };
90
Stephen Warren1292c122011-11-21 14:44:11 -070091 sdhci@c8000000 {
92 status = "disable";
93 };
94
95 sdhci@c8000200 {
96 status = "disable";
97 };
98
Peter De Schrijveradd29e62011-10-12 14:53:05 +030099 sdhci@c8000400 {
100 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
101 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
Stephen Warrenc406eeb2011-10-19 06:53:57 +0000102 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300103 };
104
105 sdhci@c8000600 {
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300106 support-8bit;
107 };
108};