blob: a80a3a4744abf8b549199d8dccf93876de088ca1 [file] [log] [blame]
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
46#include <linux/if.h>
47#include <linux/netdevice.h>
48#include <linux/cache.h>
49#include <linux/pci.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52
53#include <net/ieee80211_radiotap.h>
54
55#include <asm/unaligned.h>
56
57#include "base.h"
58#include "reg.h"
59#include "debug.h"
60
Jiri Slabyfa1c1142007-08-12 17:33:16 +020061static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
62
63
64/******************\
65* Internal defines *
66\******************/
67
68/* Module info */
69MODULE_AUTHOR("Jiri Slaby");
70MODULE_AUTHOR("Nick Kossifidis");
71MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
72MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
73MODULE_LICENSE("Dual BSD/GPL");
Luis R. Rodriguez400ec452008-02-03 21:51:49 -050074MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
Jiri Slabyfa1c1142007-08-12 17:33:16 +020075
76
77/* Known PCI ids */
78static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
79 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
80 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
81 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
82 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
83 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
84 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
85 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
86 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
88 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
94 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
95 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
96 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
97 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
98 { 0 }
99};
100MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
101
102/* Known SREVs */
103static struct ath5k_srev_name srev_names[] = {
104 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
105 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
106 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
107 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
108 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
109 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
110 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
111 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
Nick Kossifidisbb0c9dc2008-03-07 11:52:51 -0500112 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
113 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200114 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
115 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
116 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
117 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
118 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
119 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300120 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200121 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
124 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
125 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
126 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
127 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
128 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
Nick Kossifidisbb0c9dc2008-03-07 11:52:51 -0500129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
131 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
133 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
134};
135
136/*
137 * Prototypes - PCI stack related functions
138 */
139static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
140 const struct pci_device_id *id);
141static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
142#ifdef CONFIG_PM
143static int ath5k_pci_suspend(struct pci_dev *pdev,
144 pm_message_t state);
145static int ath5k_pci_resume(struct pci_dev *pdev);
146#else
147#define ath5k_pci_suspend NULL
148#define ath5k_pci_resume NULL
149#endif /* CONFIG_PM */
150
John W. Linville04a9e452008-02-01 16:03:45 -0500151static struct pci_driver ath5k_pci_driver = {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200152 .name = "ath5k_pci",
153 .id_table = ath5k_pci_id_table,
154 .probe = ath5k_pci_probe,
155 .remove = __devexit_p(ath5k_pci_remove),
156 .suspend = ath5k_pci_suspend,
157 .resume = ath5k_pci_resume,
158};
159
160
161
162/*
163 * Prototypes - MAC 802.11 stack related functions
164 */
Johannes Berge039fa42008-05-15 12:55:29 +0200165static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200166static int ath5k_reset(struct ieee80211_hw *hw);
167static int ath5k_start(struct ieee80211_hw *hw);
168static void ath5k_stop(struct ieee80211_hw *hw);
169static int ath5k_add_interface(struct ieee80211_hw *hw,
170 struct ieee80211_if_init_conf *conf);
171static void ath5k_remove_interface(struct ieee80211_hw *hw,
172 struct ieee80211_if_init_conf *conf);
173static int ath5k_config(struct ieee80211_hw *hw,
174 struct ieee80211_conf *conf);
Johannes Berg32bfd352007-12-19 01:31:26 +0100175static int ath5k_config_interface(struct ieee80211_hw *hw,
176 struct ieee80211_vif *vif,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200177 struct ieee80211_if_conf *conf);
178static void ath5k_configure_filter(struct ieee80211_hw *hw,
179 unsigned int changed_flags,
180 unsigned int *new_flags,
181 int mc_count, struct dev_mc_list *mclist);
182static int ath5k_set_key(struct ieee80211_hw *hw,
183 enum set_key_cmd cmd,
184 const u8 *local_addr, const u8 *addr,
185 struct ieee80211_key_conf *key);
186static int ath5k_get_stats(struct ieee80211_hw *hw,
187 struct ieee80211_low_level_stats *stats);
188static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
189 struct ieee80211_tx_queue_stats *stats);
190static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
191static void ath5k_reset_tsf(struct ieee80211_hw *hw);
192static int ath5k_beacon_update(struct ieee80211_hw *hw,
Johannes Berge039fa42008-05-15 12:55:29 +0200193 struct sk_buff *skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200194
195static struct ieee80211_ops ath5k_hw_ops = {
196 .tx = ath5k_tx,
197 .start = ath5k_start,
198 .stop = ath5k_stop,
199 .add_interface = ath5k_add_interface,
200 .remove_interface = ath5k_remove_interface,
201 .config = ath5k_config,
202 .config_interface = ath5k_config_interface,
203 .configure_filter = ath5k_configure_filter,
204 .set_key = ath5k_set_key,
205 .get_stats = ath5k_get_stats,
206 .conf_tx = NULL,
207 .get_tx_stats = ath5k_get_tx_stats,
208 .get_tsf = ath5k_get_tsf,
209 .reset_tsf = ath5k_reset_tsf,
210 .beacon_update = ath5k_beacon_update,
211};
212
213/*
214 * Prototypes - Internal functions
215 */
216/* Attach detach */
217static int ath5k_attach(struct pci_dev *pdev,
218 struct ieee80211_hw *hw);
219static void ath5k_detach(struct pci_dev *pdev,
220 struct ieee80211_hw *hw);
221/* Channel/mode setup */
222static inline short ath5k_ieee2mhz(short chan);
223static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
224 const struct ath5k_rate_table *rt,
225 unsigned int max);
226static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
227 struct ieee80211_channel *channels,
228 unsigned int mode,
229 unsigned int max);
230static int ath5k_getchannels(struct ieee80211_hw *hw);
231static int ath5k_chan_set(struct ath5k_softc *sc,
232 struct ieee80211_channel *chan);
233static void ath5k_setcurmode(struct ath5k_softc *sc,
234 unsigned int mode);
235static void ath5k_mode_setup(struct ath5k_softc *sc);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500236static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
237
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200238/* Descriptor setup */
239static int ath5k_desc_alloc(struct ath5k_softc *sc,
240 struct pci_dev *pdev);
241static void ath5k_desc_free(struct ath5k_softc *sc,
242 struct pci_dev *pdev);
243/* Buffers setup */
244static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
245 struct ath5k_buf *bf);
246static int ath5k_txbuf_setup(struct ath5k_softc *sc,
Johannes Berge039fa42008-05-15 12:55:29 +0200247 struct ath5k_buf *bf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200248static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
249 struct ath5k_buf *bf)
250{
251 BUG_ON(!bf);
252 if (!bf->skb)
253 return;
254 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
255 PCI_DMA_TODEVICE);
256 dev_kfree_skb(bf->skb);
257 bf->skb = NULL;
258}
259
260/* Queues setup */
261static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
262 int qtype, int subtype);
263static int ath5k_beaconq_setup(struct ath5k_hw *ah);
264static int ath5k_beaconq_config(struct ath5k_softc *sc);
265static void ath5k_txq_drainq(struct ath5k_softc *sc,
266 struct ath5k_txq *txq);
267static void ath5k_txq_cleanup(struct ath5k_softc *sc);
268static void ath5k_txq_release(struct ath5k_softc *sc);
269/* Rx handling */
270static int ath5k_rx_start(struct ath5k_softc *sc);
271static void ath5k_rx_stop(struct ath5k_softc *sc);
272static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
273 struct ath5k_desc *ds,
Bruno Randolfb47f4072008-03-05 18:35:45 +0900274 struct sk_buff *skb,
275 struct ath5k_rx_status *rs);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200276static void ath5k_tasklet_rx(unsigned long data);
277/* Tx handling */
278static void ath5k_tx_processq(struct ath5k_softc *sc,
279 struct ath5k_txq *txq);
280static void ath5k_tasklet_tx(unsigned long data);
281/* Beacon handling */
282static int ath5k_beacon_setup(struct ath5k_softc *sc,
Johannes Berge039fa42008-05-15 12:55:29 +0200283 struct ath5k_buf *bf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200284static void ath5k_beacon_send(struct ath5k_softc *sc);
285static void ath5k_beacon_config(struct ath5k_softc *sc);
Bruno Randolf9804b982008-01-19 18:17:59 +0900286static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200287
288static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
289{
290 u64 tsf = ath5k_hw_get_tsf64(ah);
291
292 if ((tsf & 0x7fff) < rstamp)
293 tsf -= 0x8000;
294
295 return (tsf & ~0x7fff) | rstamp;
296}
297
298/* Interrupt handling */
299static int ath5k_init(struct ath5k_softc *sc);
300static int ath5k_stop_locked(struct ath5k_softc *sc);
301static int ath5k_stop_hw(struct ath5k_softc *sc);
302static irqreturn_t ath5k_intr(int irq, void *dev_id);
303static void ath5k_tasklet_reset(unsigned long data);
304
305static void ath5k_calibrate(unsigned long data);
306/* LED functions */
Bob Copeland3a078872008-06-25 22:35:28 -0400307static int ath5k_init_leds(struct ath5k_softc *sc);
308static void ath5k_led_enable(struct ath5k_softc *sc);
309static void ath5k_led_off(struct ath5k_softc *sc);
310static void ath5k_unregister_leds(struct ath5k_softc *sc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200311
312/*
313 * Module init/exit functions
314 */
315static int __init
316init_ath5k_pci(void)
317{
318 int ret;
319
320 ath5k_debug_init();
321
John W. Linville04a9e452008-02-01 16:03:45 -0500322 ret = pci_register_driver(&ath5k_pci_driver);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200323 if (ret) {
324 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
325 return ret;
326 }
327
328 return 0;
329}
330
331static void __exit
332exit_ath5k_pci(void)
333{
John W. Linville04a9e452008-02-01 16:03:45 -0500334 pci_unregister_driver(&ath5k_pci_driver);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200335
336 ath5k_debug_finish();
337}
338
339module_init(init_ath5k_pci);
340module_exit(exit_ath5k_pci);
341
342
343/********************\
344* PCI Initialization *
345\********************/
346
347static const char *
348ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
349{
350 const char *name = "xxxxx";
351 unsigned int i;
352
353 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
354 if (srev_names[i].sr_type != type)
355 continue;
356 if ((val & 0xff) < srev_names[i + 1].sr_val) {
357 name = srev_names[i].sr_name;
358 break;
359 }
360 }
361
362 return name;
363}
364
365static int __devinit
366ath5k_pci_probe(struct pci_dev *pdev,
367 const struct pci_device_id *id)
368{
369 void __iomem *mem;
370 struct ath5k_softc *sc;
371 struct ieee80211_hw *hw;
372 int ret;
373 u8 csz;
374
375 ret = pci_enable_device(pdev);
376 if (ret) {
377 dev_err(&pdev->dev, "can't enable device\n");
378 goto err;
379 }
380
381 /* XXX 32-bit addressing only */
382 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
383 if (ret) {
384 dev_err(&pdev->dev, "32-bit DMA not available\n");
385 goto err_dis;
386 }
387
388 /*
389 * Cache line size is used to size and align various
390 * structures used to communicate with the hardware.
391 */
392 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
393 if (csz == 0) {
394 /*
395 * Linux 2.4.18 (at least) writes the cache line size
396 * register as a 16-bit wide register which is wrong.
397 * We must have this setup properly for rx buffer
398 * DMA to work so force a reasonable value here if it
399 * comes up zero.
400 */
401 csz = L1_CACHE_BYTES / sizeof(u32);
402 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
403 }
404 /*
405 * The default setting of latency timer yields poor results,
406 * set it to the value used by other systems. It may be worth
407 * tweaking this setting more.
408 */
409 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
410
411 /* Enable bus mastering */
412 pci_set_master(pdev);
413
414 /*
415 * Disable the RETRY_TIMEOUT register (0x41) to keep
416 * PCI Tx retries from interfering with C3 CPU state.
417 */
418 pci_write_config_byte(pdev, 0x41, 0);
419
420 ret = pci_request_region(pdev, 0, "ath5k");
421 if (ret) {
422 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
423 goto err_dis;
424 }
425
426 mem = pci_iomap(pdev, 0, 0);
427 if (!mem) {
428 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
429 ret = -EIO;
430 goto err_reg;
431 }
432
433 /*
434 * Allocate hw (mac80211 main struct)
435 * and hw->priv (driver private data)
436 */
437 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
438 if (hw == NULL) {
439 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
440 ret = -ENOMEM;
441 goto err_map;
442 }
443
444 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
445
446 /* Initialize driver private data */
447 SET_IEEE80211_DEV(hw, &pdev->dev);
Bruno Randolf566bfe52008-05-08 19:15:40 +0200448 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
449 IEEE80211_HW_SIGNAL_DBM |
450 IEEE80211_HW_NOISE_DBM;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200451 hw->extra_tx_headroom = 2;
452 hw->channel_change_time = 5000;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200453 sc = hw->priv;
454 sc->hw = hw;
455 sc->pdev = pdev;
456
457 ath5k_debug_init_device(sc);
458
459 /*
460 * Mark the device as detached to avoid processing
461 * interrupts until setup is complete.
462 */
463 __set_bit(ATH_STAT_INVALID, sc->status);
464
465 sc->iobase = mem; /* So we can unmap it on detach */
466 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
467 sc->opmode = IEEE80211_IF_TYPE_STA;
468 mutex_init(&sc->lock);
469 spin_lock_init(&sc->rxbuflock);
470 spin_lock_init(&sc->txbuflock);
471
472 /* Set private data */
473 pci_set_drvdata(pdev, hw);
474
475 /* Enable msi for devices that support it */
476 pci_enable_msi(pdev);
477
478 /* Setup interrupt handler */
479 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
480 if (ret) {
481 ATH5K_ERR(sc, "request_irq failed\n");
482 goto err_free;
483 }
484
485 /* Initialize device */
486 sc->ah = ath5k_hw_attach(sc, id->driver_data);
487 if (IS_ERR(sc->ah)) {
488 ret = PTR_ERR(sc->ah);
489 goto err_irq;
490 }
491
492 /* Finish private driver data initialization */
493 ret = ath5k_attach(pdev, hw);
494 if (ret)
495 goto err_ah;
496
497 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
498 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
499 sc->ah->ah_mac_srev,
500 sc->ah->ah_phy_revision);
501
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500502 if (!sc->ah->ah_single_chip) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200503 /* Single chip radio (!RF5111) */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500504 if (sc->ah->ah_radio_5ghz_revision &&
505 !sc->ah->ah_radio_2ghz_revision) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200506 /* No 5GHz support -> report 2GHz radio */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500507 if (!test_bit(AR5K_MODE_11A,
508 sc->ah->ah_capabilities.cap_mode)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200509 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500510 ath5k_chip_name(AR5K_VERSION_RAD,
511 sc->ah->ah_radio_5ghz_revision),
512 sc->ah->ah_radio_5ghz_revision);
513 /* No 2GHz support (5110 and some
514 * 5Ghz only cards) -> report 5Ghz radio */
515 } else if (!test_bit(AR5K_MODE_11B,
516 sc->ah->ah_capabilities.cap_mode)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200517 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500518 ath5k_chip_name(AR5K_VERSION_RAD,
519 sc->ah->ah_radio_5ghz_revision),
520 sc->ah->ah_radio_5ghz_revision);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200521 /* Multiband radio */
522 } else {
523 ATH5K_INFO(sc, "RF%s multiband radio found"
524 " (0x%x)\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500525 ath5k_chip_name(AR5K_VERSION_RAD,
526 sc->ah->ah_radio_5ghz_revision),
527 sc->ah->ah_radio_5ghz_revision);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200528 }
529 }
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500530 /* Multi chip radio (RF5111 - RF2111) ->
531 * report both 2GHz/5GHz radios */
532 else if (sc->ah->ah_radio_5ghz_revision &&
533 sc->ah->ah_radio_2ghz_revision){
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200534 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500535 ath5k_chip_name(AR5K_VERSION_RAD,
536 sc->ah->ah_radio_5ghz_revision),
537 sc->ah->ah_radio_5ghz_revision);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200538 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500539 ath5k_chip_name(AR5K_VERSION_RAD,
540 sc->ah->ah_radio_2ghz_revision),
541 sc->ah->ah_radio_2ghz_revision);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200542 }
543 }
544
545
546 /* ready to process interrupts */
547 __clear_bit(ATH_STAT_INVALID, sc->status);
548
549 return 0;
550err_ah:
551 ath5k_hw_detach(sc->ah);
552err_irq:
553 free_irq(pdev->irq, sc);
554err_free:
555 pci_disable_msi(pdev);
556 ieee80211_free_hw(hw);
557err_map:
558 pci_iounmap(pdev, mem);
559err_reg:
560 pci_release_region(pdev, 0);
561err_dis:
562 pci_disable_device(pdev);
563err:
564 return ret;
565}
566
567static void __devexit
568ath5k_pci_remove(struct pci_dev *pdev)
569{
570 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
571 struct ath5k_softc *sc = hw->priv;
572
573 ath5k_debug_finish_device(sc);
574 ath5k_detach(pdev, hw);
575 ath5k_hw_detach(sc->ah);
576 free_irq(pdev->irq, sc);
577 pci_disable_msi(pdev);
578 pci_iounmap(pdev, sc->iobase);
579 pci_release_region(pdev, 0);
580 pci_disable_device(pdev);
581 ieee80211_free_hw(hw);
582}
583
584#ifdef CONFIG_PM
585static int
586ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
587{
588 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
589 struct ath5k_softc *sc = hw->priv;
590
Bob Copeland3a078872008-06-25 22:35:28 -0400591 ath5k_led_off(sc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200592
593 ath5k_stop_hw(sc);
594 pci_save_state(pdev);
595 pci_disable_device(pdev);
596 pci_set_power_state(pdev, PCI_D3hot);
597
598 return 0;
599}
600
601static int
602ath5k_pci_resume(struct pci_dev *pdev)
603{
604 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
605 struct ath5k_softc *sc = hw->priv;
John W. Linville247ae442008-01-21 15:36:05 -0500606 struct ath5k_hw *ah = sc->ah;
607 int i, err;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200608
609 err = pci_set_power_state(pdev, PCI_D0);
610 if (err)
611 return err;
612
613 err = pci_enable_device(pdev);
614 if (err)
615 return err;
616
617 pci_restore_state(pdev);
618 /*
619 * Suspend/Resume resets the PCI configuration space, so we have to
620 * re-disable the RETRY_TIMEOUT register (0x41) to keep
621 * PCI Tx retries from interfering with C3 CPU state
622 */
623 pci_write_config_byte(pdev, 0x41, 0);
624
625 ath5k_init(sc);
Bob Copeland3a078872008-06-25 22:35:28 -0400626 ath5k_led_enable(sc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200627
John W. Linville247ae442008-01-21 15:36:05 -0500628 /*
629 * Reset the key cache since some parts do not
630 * reset the contents on initial power up or resume.
631 *
632 * FIXME: This may need to be revisited when mac80211 becomes
633 * aware of suspend/resume.
634 */
635 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
636 ath5k_hw_reset_key(ah, i);
637
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200638 return 0;
639}
640#endif /* CONFIG_PM */
641
642
643
644/***********************\
645* Driver Initialization *
646\***********************/
647
648static int
649ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
650{
651 struct ath5k_softc *sc = hw->priv;
652 struct ath5k_hw *ah = sc->ah;
653 u8 mac[ETH_ALEN];
654 unsigned int i;
655 int ret;
656
657 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
658
659 /*
660 * Check if the MAC has multi-rate retry support.
661 * We do this by trying to setup a fake extended
662 * descriptor. MAC's that don't have support will
663 * return false w/o doing anything. MAC's that do
664 * support it will return true w/o doing anything.
665 */
Jiri Slabyb9887632008-02-15 21:58:52 +0100666 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
667 if (ret < 0)
668 goto err;
669 if (ret > 0)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200670 __set_bit(ATH_STAT_MRRETRY, sc->status);
671
672 /*
673 * Reset the key cache since some parts do not
674 * reset the contents on initial power up.
675 */
John W. Linvillec65638a2008-01-21 15:36:04 -0500676 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200677 ath5k_hw_reset_key(ah, i);
678
679 /*
680 * Collect the channel list. The 802.11 layer
681 * is resposible for filtering this list based
682 * on settings like the phy mode and regulatory
683 * domain restrictions.
684 */
685 ret = ath5k_getchannels(hw);
686 if (ret) {
687 ATH5K_ERR(sc, "can't get channels\n");
688 goto err;
689 }
690
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500691 /* Set *_rates so we can map hw rate index */
692 ath5k_set_total_hw_rates(sc);
693
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200694 /* NB: setup here so ath5k_rate_update is happy */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500695 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
696 ath5k_setcurmode(sc, AR5K_MODE_11A);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200697 else
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500698 ath5k_setcurmode(sc, AR5K_MODE_11B);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200699
700 /*
701 * Allocate tx+rx descriptors and populate the lists.
702 */
703 ret = ath5k_desc_alloc(sc, pdev);
704 if (ret) {
705 ATH5K_ERR(sc, "can't allocate descriptors\n");
706 goto err;
707 }
708
709 /*
710 * Allocate hardware transmit queues: one queue for
711 * beacon frames and one data queue for each QoS
712 * priority. Note that hw functions handle reseting
713 * these queues at the needed time.
714 */
715 ret = ath5k_beaconq_setup(ah);
716 if (ret < 0) {
717 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
718 goto err_desc;
719 }
720 sc->bhalq = ret;
721
722 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
723 if (IS_ERR(sc->txq)) {
724 ATH5K_ERR(sc, "can't setup xmit queue\n");
725 ret = PTR_ERR(sc->txq);
726 goto err_bhal;
727 }
728
729 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
730 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
731 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
732 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200733
734 ath5k_hw_get_lladdr(ah, mac);
735 SET_IEEE80211_PERM_ADDR(hw, mac);
736 /* All MAC address bits matter for ACKs */
737 memset(sc->bssidmask, 0xff, ETH_ALEN);
738 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
739
740 ret = ieee80211_register_hw(hw);
741 if (ret) {
742 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
743 goto err_queues;
744 }
745
Bob Copeland3a078872008-06-25 22:35:28 -0400746 ath5k_init_leds(sc);
747
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200748 return 0;
749err_queues:
750 ath5k_txq_release(sc);
751err_bhal:
752 ath5k_hw_release_tx_queue(ah, sc->bhalq);
753err_desc:
754 ath5k_desc_free(sc, pdev);
755err:
756 return ret;
757}
758
759static void
760ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
761{
762 struct ath5k_softc *sc = hw->priv;
763
764 /*
765 * NB: the order of these is important:
766 * o call the 802.11 layer before detaching ath5k_hw to
767 * insure callbacks into the driver to delete global
768 * key cache entries can be handled
769 * o reclaim the tx queue data structures after calling
770 * the 802.11 layer as we'll get called back to reclaim
771 * node state and potentially want to use them
772 * o to cleanup the tx queues the hal is called, so detach
773 * it last
774 * XXX: ??? detach ath5k_hw ???
775 * Other than that, it's straightforward...
776 */
777 ieee80211_unregister_hw(hw);
778 ath5k_desc_free(sc, pdev);
779 ath5k_txq_release(sc);
780 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
Bob Copeland3a078872008-06-25 22:35:28 -0400781 ath5k_unregister_leds(sc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200782
783 /*
784 * NB: can't reclaim these until after ieee80211_ifdetach
785 * returns because we'll get called back to reclaim node
786 * state and potentially want to use them.
787 */
788}
789
790
791
792
793/********************\
794* Channel/mode setup *
795\********************/
796
797/*
798 * Convert IEEE channel number to MHz frequency.
799 */
800static inline short
801ath5k_ieee2mhz(short chan)
802{
803 if (chan <= 14 || chan >= 27)
804 return ieee80211chan2mhz(chan);
805 else
806 return 2212 + chan * 20;
807}
808
809static unsigned int
810ath5k_copy_rates(struct ieee80211_rate *rates,
811 const struct ath5k_rate_table *rt,
812 unsigned int max)
813{
814 unsigned int i, count;
815
816 if (rt == NULL)
817 return 0;
818
819 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500820 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
821 rates[count].hw_value = rt->rates[i].rate_code;
822 rates[count].flags = rt->rates[i].modulation;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200823 count++;
824 max--;
825 }
826
827 return count;
828}
829
830static unsigned int
831ath5k_copy_channels(struct ath5k_hw *ah,
832 struct ieee80211_channel *channels,
833 unsigned int mode,
834 unsigned int max)
835{
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500836 unsigned int i, count, size, chfreq, freq, ch;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200837
838 if (!test_bit(mode, ah->ah_modes))
839 return 0;
840
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200841 switch (mode) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500842 case AR5K_MODE_11A:
843 case AR5K_MODE_11A_TURBO:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200844 /* 1..220, but 2GHz frequencies are filtered by check_channel */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500845 size = 220 ;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200846 chfreq = CHANNEL_5GHZ;
847 break;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500848 case AR5K_MODE_11B:
849 case AR5K_MODE_11G:
850 case AR5K_MODE_11G_TURBO:
851 size = 26;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200852 chfreq = CHANNEL_2GHZ;
853 break;
854 default:
855 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
856 return 0;
857 }
858
859 for (i = 0, count = 0; i < size && max > 0; i++) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500860 ch = i + 1 ;
861 freq = ath5k_ieee2mhz(ch);
862
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200863 /* Check if channel is supported by the chipset */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500864 if (!ath5k_channel_ok(ah, freq, chfreq))
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200865 continue;
866
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500867 /* Write channel info and increment counter */
868 channels[count].center_freq = freq;
Luis R. Rodrigueza3f4b912008-02-03 21:52:10 -0500869 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
870 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500871 switch (mode) {
872 case AR5K_MODE_11A:
873 case AR5K_MODE_11G:
874 channels[count].hw_value = chfreq | CHANNEL_OFDM;
875 break;
876 case AR5K_MODE_11A_TURBO:
877 case AR5K_MODE_11G_TURBO:
878 channels[count].hw_value = chfreq |
879 CHANNEL_OFDM | CHANNEL_TURBO;
880 break;
881 case AR5K_MODE_11B:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500882 channels[count].hw_value = CHANNEL_B;
883 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200884
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200885 count++;
886 max--;
887 }
888
889 return count;
890}
891
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200892static int
893ath5k_getchannels(struct ieee80211_hw *hw)
894{
895 struct ath5k_softc *sc = hw->priv;
896 struct ath5k_hw *ah = sc->ah;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500897 struct ieee80211_supported_band *sbands = sc->sbands;
898 const struct ath5k_rate_table *hw_rates;
899 unsigned int max_r, max_c, count_r, count_c;
900 int mode2g = AR5K_MODE_11G;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200901
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500902 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200903
904 max_r = ARRAY_SIZE(sc->rates);
905 max_c = ARRAY_SIZE(sc->channels);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500906 count_r = count_c = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200907
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500908 /* 2GHz band */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500909 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500910 mode2g = AR5K_MODE_11B;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500911 if (!test_bit(AR5K_MODE_11B,
912 sc->ah->ah_capabilities.cap_mode))
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500913 mode2g = -1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200914 }
915
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500916 if (mode2g > 0) {
917 struct ieee80211_supported_band *sband =
918 &sbands[IEEE80211_BAND_2GHZ];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200919
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500920 sband->bitrates = sc->rates;
921 sband->channels = sc->channels;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200922
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500923 sband->band = IEEE80211_BAND_2GHZ;
924 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
925 mode2g, max_c);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200926
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500927 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
928 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500929 hw_rates, max_r);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500930
931 count_c = sband->n_channels;
932 count_r = sband->n_bitrates;
933
934 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
935
936 max_r -= count_r;
937 max_c -= count_c;
938
939 }
940
941 /* 5GHz band */
942
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500943 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
944 struct ieee80211_supported_band *sband =
945 &sbands[IEEE80211_BAND_5GHZ];
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500946
947 sband->bitrates = &sc->rates[count_r];
948 sband->channels = &sc->channels[count_c];
949
950 sband->band = IEEE80211_BAND_5GHZ;
951 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
952 AR5K_MODE_11A, max_c);
953
954 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
955 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500956 hw_rates, max_r);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500957
958 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
959 }
960
Luis R. Rodriguezb4461972008-02-04 10:03:54 -0500961 ath5k_debug_dump_bands(sc);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500962
963 return 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200964}
965
966/*
967 * Set/change channels. If the channel is really being changed,
968 * it's done by reseting the chip. To accomplish this we must
969 * first cleanup any pending DMA, then restart stuff after a la
970 * ath5k_init.
971 */
972static int
973ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
974{
975 struct ath5k_hw *ah = sc->ah;
976 int ret;
977
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500978 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
979 sc->curchan->center_freq, chan->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200980
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500981 if (chan->center_freq != sc->curchan->center_freq ||
982 chan->hw_value != sc->curchan->hw_value) {
983
984 sc->curchan = chan;
985 sc->curband = &sc->sbands[chan->band];
986
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200987 /*
988 * To switch channels clear any pending DMA operations;
989 * wait long enough for the RX fifo to drain, reset the
990 * hardware at the new frequency, and then re-enable
991 * the relevant bits of the h/w.
992 */
993 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
994 ath5k_txq_cleanup(sc); /* clear pending tx frames */
995 ath5k_rx_stop(sc); /* turn off frame recv */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500996 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200997 if (ret) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500998 ATH5K_ERR(sc, "%s: unable to reset channel "
999 "(%u Mhz)\n", __func__, chan->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001000 return ret;
1001 }
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001002
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001003 ath5k_hw_set_txpower_limit(sc->ah, 0);
1004
1005 /*
1006 * Re-enable rx framework.
1007 */
1008 ret = ath5k_rx_start(sc);
1009 if (ret) {
1010 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1011 __func__);
1012 return ret;
1013 }
1014
1015 /*
1016 * Change channels and update the h/w rate map
1017 * if we're switching; e.g. 11a to 11b/g.
1018 *
1019 * XXX needed?
1020 */
1021/* ath5k_chan_change(sc, chan); */
1022
1023 ath5k_beacon_config(sc);
1024 /*
1025 * Re-enable interrupts.
1026 */
1027 ath5k_hw_set_intr(ah, sc->imask);
1028 }
1029
1030 return 0;
1031}
1032
1033static void
1034ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1035{
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001036 sc->curmode = mode;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001037
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001038 if (mode == AR5K_MODE_11A) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001039 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1040 } else {
1041 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1042 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001043}
1044
1045static void
1046ath5k_mode_setup(struct ath5k_softc *sc)
1047{
1048 struct ath5k_hw *ah = sc->ah;
1049 u32 rfilt;
1050
1051 /* configure rx filter */
1052 rfilt = sc->filter_flags;
1053 ath5k_hw_set_rx_filter(ah, rfilt);
1054
1055 if (ath5k_hw_hasbssidmask(ah))
1056 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1057
1058 /* configure operational mode */
1059 ath5k_hw_set_opmode(ah);
1060
1061 ath5k_hw_set_mcast_filter(ah, 0, 0);
1062 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1063}
1064
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001065/*
1066 * Match the hw provided rate index (through descriptors)
1067 * to an index for sc->curband->bitrates, so it can be used
1068 * by the stack.
1069 *
1070 * This one is a little bit tricky but i think i'm right
1071 * about this...
1072 *
1073 * We have 4 rate tables in the following order:
1074 * XR (4 rates)
1075 * 802.11a (8 rates)
1076 * 802.11b (4 rates)
1077 * 802.11g (12 rates)
1078 * that make the hw rate table.
1079 *
1080 * Lets take a 5211 for example that supports a and b modes only.
1081 * First comes the 802.11a table and then 802.11b (total 12 rates).
1082 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1083 * if it returns 2 it points to the second 802.11a rate etc.
1084 *
1085 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1086 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1087 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1088 */
1089static void
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001090ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001091
1092 struct ath5k_hw *ah = sc->ah;
1093
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001094 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001095 sc->a_rates = 8;
1096
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001097 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001098 sc->b_rates = 4;
1099
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001100 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001101 sc->g_rates = 12;
1102
1103 /* XXX: Need to see what what happens when
1104 xr disable bits in eeprom are set */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001105 if (ah->ah_version >= AR5K_AR5212)
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001106 sc->xr_rates = 4;
1107
1108}
1109
1110static inline int
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001111ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001112
1113 int mac80211_rix;
1114
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001115 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001116 /* We setup a g ratetable for both b/g modes */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001117 mac80211_rix =
1118 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001119 } else {
1120 mac80211_rix = hw_rix - sc->xr_rates;
1121 }
1122
1123 /* Something went wrong, fallback to basic rate for this band */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001124 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1125 (mac80211_rix <= 0 ))
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001126 mac80211_rix = 1;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001127
1128 return mac80211_rix;
1129}
1130
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001131
1132
1133
1134/***************\
1135* Buffers setup *
1136\***************/
1137
1138static int
1139ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1140{
1141 struct ath5k_hw *ah = sc->ah;
1142 struct sk_buff *skb = bf->skb;
1143 struct ath5k_desc *ds;
1144
1145 if (likely(skb == NULL)) {
1146 unsigned int off;
1147
1148 /*
1149 * Allocate buffer with headroom_needed space for the
1150 * fake physical layer header at the start.
1151 */
1152 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1153 if (unlikely(skb == NULL)) {
1154 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1155 sc->rxbufsize + sc->cachelsz - 1);
1156 return -ENOMEM;
1157 }
1158 /*
1159 * Cache-line-align. This is important (for the
1160 * 5210 at least) as not doing so causes bogus data
1161 * in rx'd frames.
1162 */
1163 off = ((unsigned long)skb->data) % sc->cachelsz;
1164 if (off != 0)
1165 skb_reserve(skb, sc->cachelsz - off);
1166
1167 bf->skb = skb;
1168 bf->skbaddr = pci_map_single(sc->pdev,
1169 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1170 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1171 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1172 dev_kfree_skb(skb);
1173 bf->skb = NULL;
1174 return -ENOMEM;
1175 }
1176 }
1177
1178 /*
1179 * Setup descriptors. For receive we always terminate
1180 * the descriptor list with a self-linked entry so we'll
1181 * not get overrun under high load (as can happen with a
1182 * 5212 when ANI processing enables PHY error frames).
1183 *
1184 * To insure the last descriptor is self-linked we create
1185 * each descriptor as self-linked and add it to the end. As
1186 * each additional descriptor is added the previous self-linked
1187 * entry is ``fixed'' naturally. This should be safe even
1188 * if DMA is happening. When processing RX interrupts we
1189 * never remove/process the last, self-linked, entry on the
1190 * descriptor list. This insures the hardware always has
1191 * someplace to write a new frame.
1192 */
1193 ds = bf->desc;
1194 ds->ds_link = bf->daddr; /* link to self */
1195 ds->ds_data = bf->skbaddr;
1196 ath5k_hw_setup_rx_desc(ah, ds,
1197 skb_tailroom(skb), /* buffer size */
1198 0);
1199
1200 if (sc->rxlink != NULL)
1201 *sc->rxlink = bf->daddr;
1202 sc->rxlink = &ds->ds_link;
1203 return 0;
1204}
1205
1206static int
Johannes Berge039fa42008-05-15 12:55:29 +02001207ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001208{
1209 struct ath5k_hw *ah = sc->ah;
1210 struct ath5k_txq *txq = sc->txq;
1211 struct ath5k_desc *ds = bf->desc;
1212 struct sk_buff *skb = bf->skb;
Johannes Berga888d522008-05-26 16:43:39 +02001213 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001214 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1215 int ret;
1216
1217 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
Johannes Berge039fa42008-05-15 12:55:29 +02001218
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001219 /* XXX endianness */
1220 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1221 PCI_DMA_TODEVICE);
1222
Johannes Berge039fa42008-05-15 12:55:29 +02001223 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001224 flags |= AR5K_TXDESC_NOACK;
1225
Bruno Randolf281c56d2008-02-05 18:44:55 +09001226 pktlen = skb->len;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001227
Johannes Berge039fa42008-05-15 12:55:29 +02001228 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
1229 keyidx = info->control.hw_key->hw_key_idx;
1230 pktlen += info->control.icv_len;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001231 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001232 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1233 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
Johannes Berg2e92e6f2008-05-15 12:55:27 +02001234 (sc->power_level * 2),
Johannes Berge039fa42008-05-15 12:55:29 +02001235 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1236 info->control.retry_limit, keyidx, 0, flags, 0, 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001237 if (ret)
1238 goto err_unmap;
1239
1240 ds->ds_link = 0;
1241 ds->ds_data = bf->skbaddr;
1242
1243 spin_lock_bh(&txq->lock);
1244 list_add_tail(&bf->list, &txq->q);
Johannes Berg57ffc582008-04-29 17:18:59 +02001245 sc->tx_stats[txq->qnum].len++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001246 if (txq->link == NULL) /* is this first packet? */
1247 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1248 else /* no, so only link it */
1249 *txq->link = bf->daddr;
1250
1251 txq->link = &ds->ds_link;
1252 ath5k_hw_tx_start(ah, txq->qnum);
1253 spin_unlock_bh(&txq->lock);
1254
1255 return 0;
1256err_unmap:
1257 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1258 return ret;
1259}
1260
1261/*******************\
1262* Descriptors setup *
1263\*******************/
1264
1265static int
1266ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1267{
1268 struct ath5k_desc *ds;
1269 struct ath5k_buf *bf;
1270 dma_addr_t da;
1271 unsigned int i;
1272 int ret;
1273
1274 /* allocate descriptors */
1275 sc->desc_len = sizeof(struct ath5k_desc) *
1276 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1277 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1278 if (sc->desc == NULL) {
1279 ATH5K_ERR(sc, "can't allocate descriptors\n");
1280 ret = -ENOMEM;
1281 goto err;
1282 }
1283 ds = sc->desc;
1284 da = sc->desc_daddr;
1285 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1286 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1287
1288 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1289 sizeof(struct ath5k_buf), GFP_KERNEL);
1290 if (bf == NULL) {
1291 ATH5K_ERR(sc, "can't allocate bufptr\n");
1292 ret = -ENOMEM;
1293 goto err_free;
1294 }
1295 sc->bufptr = bf;
1296
1297 INIT_LIST_HEAD(&sc->rxbuf);
1298 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1299 bf->desc = ds;
1300 bf->daddr = da;
1301 list_add_tail(&bf->list, &sc->rxbuf);
1302 }
1303
1304 INIT_LIST_HEAD(&sc->txbuf);
1305 sc->txbuf_len = ATH_TXBUF;
1306 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1307 da += sizeof(*ds)) {
1308 bf->desc = ds;
1309 bf->daddr = da;
1310 list_add_tail(&bf->list, &sc->txbuf);
1311 }
1312
1313 /* beacon buffer */
1314 bf->desc = ds;
1315 bf->daddr = da;
1316 sc->bbuf = bf;
1317
1318 return 0;
1319err_free:
1320 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1321err:
1322 sc->desc = NULL;
1323 return ret;
1324}
1325
1326static void
1327ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1328{
1329 struct ath5k_buf *bf;
1330
1331 ath5k_txbuf_free(sc, sc->bbuf);
1332 list_for_each_entry(bf, &sc->txbuf, list)
1333 ath5k_txbuf_free(sc, bf);
1334 list_for_each_entry(bf, &sc->rxbuf, list)
1335 ath5k_txbuf_free(sc, bf);
1336
1337 /* Free memory associated with all descriptors */
1338 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1339
1340 kfree(sc->bufptr);
1341 sc->bufptr = NULL;
1342}
1343
1344
1345
1346
1347
1348/**************\
1349* Queues setup *
1350\**************/
1351
1352static struct ath5k_txq *
1353ath5k_txq_setup(struct ath5k_softc *sc,
1354 int qtype, int subtype)
1355{
1356 struct ath5k_hw *ah = sc->ah;
1357 struct ath5k_txq *txq;
1358 struct ath5k_txq_info qi = {
1359 .tqi_subtype = subtype,
1360 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1361 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1362 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1363 };
1364 int qnum;
1365
1366 /*
1367 * Enable interrupts only for EOL and DESC conditions.
1368 * We mark tx descriptors to receive a DESC interrupt
1369 * when a tx queue gets deep; otherwise waiting for the
1370 * EOL to reap descriptors. Note that this is done to
1371 * reduce interrupt load and this only defers reaping
1372 * descriptors, never transmitting frames. Aside from
1373 * reducing interrupts this also permits more concurrency.
1374 * The only potential downside is if the tx queue backs
1375 * up in which case the top half of the kernel may backup
1376 * due to a lack of tx descriptors.
1377 */
1378 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1379 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1380 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1381 if (qnum < 0) {
1382 /*
1383 * NB: don't print a message, this happens
1384 * normally on parts with too few tx queues
1385 */
1386 return ERR_PTR(qnum);
1387 }
1388 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1389 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1390 qnum, ARRAY_SIZE(sc->txqs));
1391 ath5k_hw_release_tx_queue(ah, qnum);
1392 return ERR_PTR(-EINVAL);
1393 }
1394 txq = &sc->txqs[qnum];
1395 if (!txq->setup) {
1396 txq->qnum = qnum;
1397 txq->link = NULL;
1398 INIT_LIST_HEAD(&txq->q);
1399 spin_lock_init(&txq->lock);
1400 txq->setup = true;
1401 }
1402 return &sc->txqs[qnum];
1403}
1404
1405static int
1406ath5k_beaconq_setup(struct ath5k_hw *ah)
1407{
1408 struct ath5k_txq_info qi = {
1409 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1410 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1411 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1412 /* NB: for dynamic turbo, don't enable any other interrupts */
1413 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1414 };
1415
1416 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1417}
1418
1419static int
1420ath5k_beaconq_config(struct ath5k_softc *sc)
1421{
1422 struct ath5k_hw *ah = sc->ah;
1423 struct ath5k_txq_info qi;
1424 int ret;
1425
1426 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1427 if (ret)
1428 return ret;
Bruno Randolf6d91e1d2008-01-19 18:18:41 +09001429 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001430 /*
1431 * Always burst out beacon and CAB traffic
1432 * (aifs = cwmin = cwmax = 0)
1433 */
1434 qi.tqi_aifs = 0;
1435 qi.tqi_cw_min = 0;
1436 qi.tqi_cw_max = 0;
Bruno Randolf6d91e1d2008-01-19 18:18:41 +09001437 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1438 /*
1439 * Adhoc mode; backoff between 0 and (2 * cw_min).
1440 */
1441 qi.tqi_aifs = 0;
1442 qi.tqi_cw_min = 0;
1443 qi.tqi_cw_max = 2 * ah->ah_cw_min;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001444 }
1445
Bruno Randolf6d91e1d2008-01-19 18:18:41 +09001446 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1447 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1448 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1449
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001450 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1451 if (ret) {
1452 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1453 "hardware queue!\n", __func__);
1454 return ret;
1455 }
1456
1457 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1458}
1459
1460static void
1461ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1462{
1463 struct ath5k_buf *bf, *bf0;
1464
1465 /*
1466 * NB: this assumes output has been stopped and
1467 * we do not need to block ath5k_tx_tasklet
1468 */
1469 spin_lock_bh(&txq->lock);
1470 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
Bruno Randolfb47f4072008-03-05 18:35:45 +09001471 ath5k_debug_printtxbuf(sc, bf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001472
1473 ath5k_txbuf_free(sc, bf);
1474
1475 spin_lock_bh(&sc->txbuflock);
Johannes Berg57ffc582008-04-29 17:18:59 +02001476 sc->tx_stats[txq->qnum].len--;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001477 list_move_tail(&bf->list, &sc->txbuf);
1478 sc->txbuf_len++;
1479 spin_unlock_bh(&sc->txbuflock);
1480 }
1481 txq->link = NULL;
1482 spin_unlock_bh(&txq->lock);
1483}
1484
1485/*
1486 * Drain the transmit queues and reclaim resources.
1487 */
1488static void
1489ath5k_txq_cleanup(struct ath5k_softc *sc)
1490{
1491 struct ath5k_hw *ah = sc->ah;
1492 unsigned int i;
1493
1494 /* XXX return value */
1495 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1496 /* don't touch the hardware if marked invalid */
1497 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1498 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1499 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1500 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1501 if (sc->txqs[i].setup) {
1502 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1503 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1504 "link %p\n",
1505 sc->txqs[i].qnum,
1506 ath5k_hw_get_tx_buf(ah,
1507 sc->txqs[i].qnum),
1508 sc->txqs[i].link);
1509 }
1510 }
Johannes Berg36d68252008-05-15 12:55:26 +02001511 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001512
1513 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1514 if (sc->txqs[i].setup)
1515 ath5k_txq_drainq(sc, &sc->txqs[i]);
1516}
1517
1518static void
1519ath5k_txq_release(struct ath5k_softc *sc)
1520{
1521 struct ath5k_txq *txq = sc->txqs;
1522 unsigned int i;
1523
1524 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1525 if (txq->setup) {
1526 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1527 txq->setup = false;
1528 }
1529}
1530
1531
1532
1533
1534/*************\
1535* RX Handling *
1536\*************/
1537
1538/*
1539 * Enable the receive h/w following a reset.
1540 */
1541static int
1542ath5k_rx_start(struct ath5k_softc *sc)
1543{
1544 struct ath5k_hw *ah = sc->ah;
1545 struct ath5k_buf *bf;
1546 int ret;
1547
1548 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1549
1550 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1551 sc->cachelsz, sc->rxbufsize);
1552
1553 sc->rxlink = NULL;
1554
1555 spin_lock_bh(&sc->rxbuflock);
1556 list_for_each_entry(bf, &sc->rxbuf, list) {
1557 ret = ath5k_rxbuf_setup(sc, bf);
1558 if (ret != 0) {
1559 spin_unlock_bh(&sc->rxbuflock);
1560 goto err;
1561 }
1562 }
1563 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1564 spin_unlock_bh(&sc->rxbuflock);
1565
1566 ath5k_hw_put_rx_buf(ah, bf->daddr);
1567 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1568 ath5k_mode_setup(sc); /* set filters, etc. */
1569 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1570
1571 return 0;
1572err:
1573 return ret;
1574}
1575
1576/*
1577 * Disable the receive h/w in preparation for a reset.
1578 */
1579static void
1580ath5k_rx_stop(struct ath5k_softc *sc)
1581{
1582 struct ath5k_hw *ah = sc->ah;
1583
1584 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1585 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1586 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1587 mdelay(3); /* 3ms is long enough for 1 frame */
1588
1589 ath5k_debug_printrxbuffs(sc, ah);
1590
1591 sc->rxlink = NULL; /* just in case */
1592}
1593
1594static unsigned int
1595ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
Bruno Randolfb47f4072008-03-05 18:35:45 +09001596 struct sk_buff *skb, struct ath5k_rx_status *rs)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001597{
1598 struct ieee80211_hdr *hdr = (void *)skb->data;
1599 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1600
Bruno Randolfb47f4072008-03-05 18:35:45 +09001601 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1602 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001603 return RX_FLAG_DECRYPTED;
1604
1605 /* Apparently when a default key is used to decrypt the packet
1606 the hw does not set the index used to decrypt. In such cases
1607 get the index from the packet. */
Harvey Harrison24b56e72008-06-14 23:33:38 -07001608 if (ieee80211_has_protected(hdr->frame_control) &&
1609 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1610 skb->len >= hlen + 4) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001611 keyix = skb->data[hlen + 3] >> 6;
1612
1613 if (test_bit(keyix, sc->keymap))
1614 return RX_FLAG_DECRYPTED;
1615 }
1616
1617 return 0;
1618}
1619
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001620
1621static void
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001622ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1623 struct ieee80211_rx_status *rxs)
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001624{
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001625 u64 tsf, bc_tstamp;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001626 u32 hw_tu;
1627 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1628
Harvey Harrison24b56e72008-06-14 23:33:38 -07001629 if (ieee80211_is_beacon(mgmt->frame_control) &&
Pavel Roskin38c07b42008-02-26 17:59:14 -05001630 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001631 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1632 /*
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001633 * Received an IBSS beacon with the same BSSID. Hardware *must*
1634 * have updated the local TSF. We have to work around various
1635 * hardware bugs, though...
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001636 */
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001637 tsf = ath5k_hw_get_tsf64(sc->ah);
1638 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1639 hw_tu = TSF_TO_TU(tsf);
1640
1641 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1642 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
John W. Linville06501d22008-04-01 17:38:47 -04001643 (unsigned long long)bc_tstamp,
1644 (unsigned long long)rxs->mactime,
1645 (unsigned long long)(rxs->mactime - bc_tstamp),
1646 (unsigned long long)tsf);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001647
1648 /*
1649 * Sometimes the HW will give us a wrong tstamp in the rx
1650 * status, causing the timestamp extension to go wrong.
1651 * (This seems to happen especially with beacon frames bigger
1652 * than 78 byte (incl. FCS))
1653 * But we know that the receive timestamp must be later than the
1654 * timestamp of the beacon since HW must have synced to that.
1655 *
1656 * NOTE: here we assume mactime to be after the frame was
1657 * received, not like mac80211 which defines it at the start.
1658 */
1659 if (bc_tstamp > rxs->mactime) {
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001660 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001661 "fixing mactime from %llx to %llx\n",
John W. Linville06501d22008-04-01 17:38:47 -04001662 (unsigned long long)rxs->mactime,
1663 (unsigned long long)tsf);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001664 rxs->mactime = tsf;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001665 }
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001666
1667 /*
1668 * Local TSF might have moved higher than our beacon timers,
1669 * in that case we have to update them to continue sending
1670 * beacons. This also takes care of synchronizing beacon sending
1671 * times with other stations.
1672 */
1673 if (hw_tu >= sc->nexttbtt)
1674 ath5k_beacon_update_timers(sc, bc_tstamp);
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001675 }
1676}
1677
1678
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001679static void
1680ath5k_tasklet_rx(unsigned long data)
1681{
1682 struct ieee80211_rx_status rxs = {};
Bruno Randolfb47f4072008-03-05 18:35:45 +09001683 struct ath5k_rx_status rs = {};
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001684 struct sk_buff *skb;
1685 struct ath5k_softc *sc = (void *)data;
1686 struct ath5k_buf *bf;
1687 struct ath5k_desc *ds;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001688 int ret;
1689 int hdrlen;
1690 int pad;
1691
1692 spin_lock(&sc->rxbuflock);
1693 do {
Bob Copelandd6894b52008-05-12 21:16:44 -04001694 rxs.flag = 0;
1695
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001696 if (unlikely(list_empty(&sc->rxbuf))) {
1697 ATH5K_WARN(sc, "empty rx buf pool\n");
1698 break;
1699 }
1700 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1701 BUG_ON(bf->skb == NULL);
1702 skb = bf->skb;
1703 ds = bf->desc;
1704
1705 /* TODO only one segment */
1706 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1707 sc->desc_len, PCI_DMA_FROMDEVICE);
1708
1709 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1710 break;
1711
Bruno Randolfb47f4072008-03-05 18:35:45 +09001712 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001713 if (unlikely(ret == -EINPROGRESS))
1714 break;
1715 else if (unlikely(ret)) {
1716 ATH5K_ERR(sc, "error in processing rx descriptor\n");
Jiri Slaby65872e62008-02-15 21:58:51 +01001717 spin_unlock(&sc->rxbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001718 return;
1719 }
1720
Bruno Randolfb47f4072008-03-05 18:35:45 +09001721 if (unlikely(rs.rs_more)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001722 ATH5K_WARN(sc, "unsupported jumbo\n");
1723 goto next;
1724 }
1725
Bruno Randolfb47f4072008-03-05 18:35:45 +09001726 if (unlikely(rs.rs_status)) {
1727 if (rs.rs_status & AR5K_RXERR_PHY)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001728 goto next;
Bruno Randolfb47f4072008-03-05 18:35:45 +09001729 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001730 /*
1731 * Decrypt error. If the error occurred
1732 * because there was no hardware key, then
1733 * let the frame through so the upper layers
1734 * can process it. This is necessary for 5210
1735 * parts which have no way to setup a ``clear''
1736 * key cache entry.
1737 *
1738 * XXX do key cache faulting
1739 */
Bruno Randolfb47f4072008-03-05 18:35:45 +09001740 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1741 !(rs.rs_status & AR5K_RXERR_CRC))
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001742 goto accept;
1743 }
Bruno Randolfb47f4072008-03-05 18:35:45 +09001744 if (rs.rs_status & AR5K_RXERR_MIC) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001745 rxs.flag |= RX_FLAG_MMIC_ERROR;
1746 goto accept;
1747 }
1748
1749 /* let crypto-error packets fall through in MNTR */
Bruno Randolfb47f4072008-03-05 18:35:45 +09001750 if ((rs.rs_status &
1751 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001752 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1753 goto next;
1754 }
1755accept:
Bruno Randolfb47f4072008-03-05 18:35:45 +09001756 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr,
1757 rs.rs_datalen, PCI_DMA_FROMDEVICE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001758 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1759 PCI_DMA_FROMDEVICE);
1760 bf->skb = NULL;
1761
Bruno Randolfb47f4072008-03-05 18:35:45 +09001762 skb_put(skb, rs.rs_datalen);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001763
1764 /*
1765 * the hardware adds a padding to 4 byte boundaries between
1766 * the header and the payload data if the header length is
1767 * not multiples of 4 - remove it
1768 */
1769 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1770 if (hdrlen & 3) {
1771 pad = hdrlen % 4;
1772 memmove(skb->data + pad, skb->data, hdrlen);
1773 skb_pull(skb, pad);
1774 }
1775
Bruno Randolfc0e18992008-01-21 11:09:46 +09001776 /*
1777 * always extend the mac timestamp, since this information is
1778 * also needed for proper IBSS merging.
1779 *
1780 * XXX: it might be too late to do it here, since rs_tstamp is
1781 * 15bit only. that means TSF extension has to be done within
1782 * 32768usec (about 32ms). it might be necessary to move this to
1783 * the interrupt handler, like it is done in madwifi.
Bruno Randolfe14296c2008-03-05 18:36:05 +09001784 *
1785 * Unfortunately we don't know when the hardware takes the rx
1786 * timestamp (beginning of phy frame, data frame, end of rx?).
1787 * The only thing we know is that it is hardware specific...
1788 * On AR5213 it seems the rx timestamp is at the end of the
1789 * frame, but i'm not sure.
1790 *
1791 * NOTE: mac80211 defines mactime at the beginning of the first
1792 * data symbol. Since we don't have any time references it's
1793 * impossible to comply to that. This affects IBSS merge only
1794 * right now, so it's not too bad...
Bruno Randolfc0e18992008-01-21 11:09:46 +09001795 */
Bruno Randolfb47f4072008-03-05 18:35:45 +09001796 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
Bruno Randolfc0e18992008-01-21 11:09:46 +09001797 rxs.flag |= RX_FLAG_TSFT;
1798
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001799 rxs.freq = sc->curchan->center_freq;
1800 rxs.band = sc->curband->band;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001801
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001802 rxs.noise = sc->ah->ah_noise_floor;
Bruno Randolf566bfe52008-05-08 19:15:40 +02001803 rxs.signal = rxs.noise + rs.rs_rssi;
1804 rxs.qual = rs.rs_rssi * 100 / 64;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001805
Bruno Randolfb47f4072008-03-05 18:35:45 +09001806 rxs.antenna = rs.rs_antenna;
1807 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1808 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001809
1810 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1811
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001812 /* check beacons in IBSS mode */
1813 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001814 ath5k_check_ibss_tsf(sc, skb, &rxs);
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001815
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001816 __ieee80211_rx(sc->hw, skb, &rxs);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001817next:
1818 list_move_tail(&bf->list, &sc->rxbuf);
1819 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1820 spin_unlock(&sc->rxbuflock);
1821}
1822
1823
1824
1825
1826/*************\
1827* TX Handling *
1828\*************/
1829
1830static void
1831ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1832{
Bruno Randolfb47f4072008-03-05 18:35:45 +09001833 struct ath5k_tx_status ts = {};
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001834 struct ath5k_buf *bf, *bf0;
1835 struct ath5k_desc *ds;
1836 struct sk_buff *skb;
Johannes Berge039fa42008-05-15 12:55:29 +02001837 struct ieee80211_tx_info *info;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001838 int ret;
1839
1840 spin_lock(&txq->lock);
1841 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1842 ds = bf->desc;
1843
1844 /* TODO only one segment */
1845 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1846 sc->desc_len, PCI_DMA_FROMDEVICE);
Bruno Randolfb47f4072008-03-05 18:35:45 +09001847 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001848 if (unlikely(ret == -EINPROGRESS))
1849 break;
1850 else if (unlikely(ret)) {
1851 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1852 ret, txq->qnum);
1853 break;
1854 }
1855
1856 skb = bf->skb;
Johannes Berga888d522008-05-26 16:43:39 +02001857 info = IEEE80211_SKB_CB(skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001858 bf->skb = NULL;
Johannes Berge039fa42008-05-15 12:55:29 +02001859
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001860 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1861 PCI_DMA_TODEVICE);
1862
Johannes Berge039fa42008-05-15 12:55:29 +02001863 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
Bruno Randolfb47f4072008-03-05 18:35:45 +09001864 if (unlikely(ts.ts_status)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001865 sc->ll_stats.dot11ACKFailureCount++;
Bruno Randolfb47f4072008-03-05 18:35:45 +09001866 if (ts.ts_status & AR5K_TXERR_XRETRY)
Johannes Berge039fa42008-05-15 12:55:29 +02001867 info->status.excessive_retries = 1;
Bruno Randolfb47f4072008-03-05 18:35:45 +09001868 else if (ts.ts_status & AR5K_TXERR_FILT)
Johannes Berge039fa42008-05-15 12:55:29 +02001869 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001870 } else {
Johannes Berge039fa42008-05-15 12:55:29 +02001871 info->flags |= IEEE80211_TX_STAT_ACK;
1872 info->status.ack_signal = ts.ts_rssi;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001873 }
1874
Johannes Berge039fa42008-05-15 12:55:29 +02001875 ieee80211_tx_status(sc->hw, skb);
Johannes Berg57ffc582008-04-29 17:18:59 +02001876 sc->tx_stats[txq->qnum].count++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001877
1878 spin_lock(&sc->txbuflock);
Johannes Berg57ffc582008-04-29 17:18:59 +02001879 sc->tx_stats[txq->qnum].len--;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001880 list_move_tail(&bf->list, &sc->txbuf);
1881 sc->txbuf_len++;
1882 spin_unlock(&sc->txbuflock);
1883 }
1884 if (likely(list_empty(&txq->q)))
1885 txq->link = NULL;
1886 spin_unlock(&txq->lock);
1887 if (sc->txbuf_len > ATH_TXBUF / 5)
1888 ieee80211_wake_queues(sc->hw);
1889}
1890
1891static void
1892ath5k_tasklet_tx(unsigned long data)
1893{
1894 struct ath5k_softc *sc = (void *)data;
1895
1896 ath5k_tx_processq(sc, sc->txq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001897}
1898
1899
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001900/*****************\
1901* Beacon handling *
1902\*****************/
1903
1904/*
1905 * Setup the beacon frame for transmit.
1906 */
1907static int
Johannes Berge039fa42008-05-15 12:55:29 +02001908ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001909{
1910 struct sk_buff *skb = bf->skb;
Johannes Berga888d522008-05-26 16:43:39 +02001911 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001912 struct ath5k_hw *ah = sc->ah;
1913 struct ath5k_desc *ds;
1914 int ret, antenna = 0;
1915 u32 flags;
1916
1917 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1918 PCI_DMA_TODEVICE);
1919 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1920 "skbaddr %llx\n", skb, skb->data, skb->len,
1921 (unsigned long long)bf->skbaddr);
1922 if (pci_dma_mapping_error(bf->skbaddr)) {
1923 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1924 return -EIO;
1925 }
1926
1927 ds = bf->desc;
1928
1929 flags = AR5K_TXDESC_NOACK;
1930 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1931 ds->ds_link = bf->daddr; /* self-linked */
1932 flags |= AR5K_TXDESC_VEOL;
1933 /*
1934 * Let hardware handle antenna switching if txantenna is not set
1935 */
1936 } else {
1937 ds->ds_link = 0;
1938 /*
1939 * Switch antenna every 4 beacons if txantenna is not set
1940 * XXX assumes two antennas
1941 */
1942 if (antenna == 0)
1943 antenna = sc->bsent & 4 ? 2 : 1;
1944 }
1945
1946 ds->ds_data = bf->skbaddr;
Bruno Randolf281c56d2008-02-05 18:44:55 +09001947 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001948 ieee80211_get_hdrlen_from_skb(skb),
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001949 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
Johannes Berge039fa42008-05-15 12:55:29 +02001950 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
Johannes Berg2e92e6f2008-05-15 12:55:27 +02001951 1, AR5K_TXKEYIX_INVALID,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001952 antenna, flags, 0, 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001953 if (ret)
1954 goto err_unmap;
1955
1956 return 0;
1957err_unmap:
1958 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1959 return ret;
1960}
1961
1962/*
1963 * Transmit a beacon frame at SWBA. Dynamic updates to the
1964 * frame contents are done as needed and the slot time is
1965 * also adjusted based on current state.
1966 *
1967 * this is usually called from interrupt context (ath5k_intr())
1968 * but also from ath5k_beacon_config() in IBSS mode which in turn
1969 * can be called from a tasklet and user context
1970 */
1971static void
1972ath5k_beacon_send(struct ath5k_softc *sc)
1973{
1974 struct ath5k_buf *bf = sc->bbuf;
1975 struct ath5k_hw *ah = sc->ah;
1976
Bruno Randolfbe9b7252008-01-23 10:27:51 +09001977 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001978
1979 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1980 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1981 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1982 return;
1983 }
1984 /*
1985 * Check if the previous beacon has gone out. If
1986 * not don't don't try to post another, skip this
1987 * period and wait for the next. Missed beacons
1988 * indicate a problem and should not occur. If we
1989 * miss too many consecutive beacons reset the device.
1990 */
1991 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1992 sc->bmisscount++;
Bruno Randolfbe9b7252008-01-23 10:27:51 +09001993 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001994 "missed %u consecutive beacons\n", sc->bmisscount);
1995 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
Bruno Randolfbe9b7252008-01-23 10:27:51 +09001996 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001997 "stuck beacon time (%u missed)\n",
1998 sc->bmisscount);
1999 tasklet_schedule(&sc->restq);
2000 }
2001 return;
2002 }
2003 if (unlikely(sc->bmisscount != 0)) {
Bruno Randolfbe9b7252008-01-23 10:27:51 +09002004 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002005 "resume beacon xmit after %u misses\n",
2006 sc->bmisscount);
2007 sc->bmisscount = 0;
2008 }
2009
2010 /*
2011 * Stop any current dma and put the new frame on the queue.
2012 * This should never fail since we check above that no frames
2013 * are still pending on the queue.
2014 */
2015 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2016 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2017 /* NB: hw still stops DMA, so proceed */
2018 }
2019 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2020 PCI_DMA_TODEVICE);
2021
2022 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2023 ath5k_hw_tx_start(ah, sc->bhalq);
Bruno Randolfbe9b7252008-01-23 10:27:51 +09002024 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002025 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2026
2027 sc->bsent++;
2028}
2029
2030
Bruno Randolf9804b982008-01-19 18:17:59 +09002031/**
2032 * ath5k_beacon_update_timers - update beacon timers
2033 *
2034 * @sc: struct ath5k_softc pointer we are operating on
2035 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2036 * beacon timer update based on the current HW TSF.
2037 *
2038 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2039 * of a received beacon or the current local hardware TSF and write it to the
2040 * beacon timer registers.
2041 *
2042 * This is called in a variety of situations, e.g. when a beacon is received,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09002043 * when a TSF update has been detected, but also when an new IBSS is created or
Bruno Randolf9804b982008-01-19 18:17:59 +09002044 * when we otherwise know we have to update the timers, but we keep it in this
2045 * function to have it all together in one place.
2046 */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002047static void
Bruno Randolf9804b982008-01-19 18:17:59 +09002048ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002049{
2050 struct ath5k_hw *ah = sc->ah;
Bruno Randolf9804b982008-01-19 18:17:59 +09002051 u32 nexttbtt, intval, hw_tu, bc_tu;
2052 u64 hw_tsf;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002053
2054 intval = sc->bintval & AR5K_BEACON_PERIOD;
2055 if (WARN_ON(!intval))
2056 return;
2057
Bruno Randolf9804b982008-01-19 18:17:59 +09002058 /* beacon TSF converted to TU */
2059 bc_tu = TSF_TO_TU(bc_tsf);
2060
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002061 /* current TSF converted to TU */
Bruno Randolf9804b982008-01-19 18:17:59 +09002062 hw_tsf = ath5k_hw_get_tsf64(ah);
2063 hw_tu = TSF_TO_TU(hw_tsf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002064
Bruno Randolf9804b982008-01-19 18:17:59 +09002065#define FUDGE 3
2066 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2067 if (bc_tsf == -1) {
2068 /*
2069 * no beacons received, called internally.
2070 * just need to refresh timers based on HW TSF.
2071 */
2072 nexttbtt = roundup(hw_tu + FUDGE, intval);
2073 } else if (bc_tsf == 0) {
2074 /*
2075 * no beacon received, probably called by ath5k_reset_tsf().
2076 * reset TSF to start with 0.
2077 */
2078 nexttbtt = intval;
2079 intval |= AR5K_BEACON_RESET_TSF;
2080 } else if (bc_tsf > hw_tsf) {
2081 /*
2082 * beacon received, SW merge happend but HW TSF not yet updated.
2083 * not possible to reconfigure timers yet, but next time we
2084 * receive a beacon with the same BSSID, the hardware will
2085 * automatically update the TSF and then we need to reconfigure
2086 * the timers.
2087 */
2088 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2089 "need to wait for HW TSF sync\n");
2090 return;
2091 } else {
2092 /*
2093 * most important case for beacon synchronization between STA.
2094 *
2095 * beacon received and HW TSF has been already updated by HW.
2096 * update next TBTT based on the TSF of the beacon, but make
2097 * sure it is ahead of our local TSF timer.
2098 */
2099 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2100 }
2101#undef FUDGE
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002102
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002103 sc->nexttbtt = nexttbtt;
2104
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002105 intval |= AR5K_BEACON_ENA;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002106 ath5k_hw_init_beacon(ah, nexttbtt, intval);
Bruno Randolf9804b982008-01-19 18:17:59 +09002107
2108 /*
2109 * debugging output last in order to preserve the time critical aspect
2110 * of this function
2111 */
2112 if (bc_tsf == -1)
2113 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2114 "reconfigured timers based on HW TSF\n");
2115 else if (bc_tsf == 0)
2116 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2117 "reset HW TSF and timers\n");
2118 else
2119 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2120 "updated timers based on beacon TSF\n");
2121
2122 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
David Miller04f93a82008-02-15 16:08:59 -08002123 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2124 (unsigned long long) bc_tsf,
2125 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
Bruno Randolf9804b982008-01-19 18:17:59 +09002126 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2127 intval & AR5K_BEACON_PERIOD,
2128 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2129 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002130}
2131
2132
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002133/**
2134 * ath5k_beacon_config - Configure the beacon queues and interrupts
2135 *
2136 * @sc: struct ath5k_softc pointer we are operating on
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002137 *
2138 * When operating in station mode we want to receive a BMISS interrupt when we
2139 * stop seeing beacons from the AP we've associated with so we can look for
2140 * another AP to associate with.
2141 *
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002142 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
Bruno Randolf6ba81c22008-03-05 18:36:26 +09002143 * interrupts to detect TSF updates only.
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002144 *
2145 * AP mode is missing.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002146 */
2147static void
2148ath5k_beacon_config(struct ath5k_softc *sc)
2149{
2150 struct ath5k_hw *ah = sc->ah;
2151
2152 ath5k_hw_set_intr(ah, 0);
2153 sc->bmisscount = 0;
2154
2155 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2156 sc->imask |= AR5K_INT_BMISS;
2157 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2158 /*
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002159 * In IBSS mode we use a self-linked tx descriptor and let the
2160 * hardware send the beacons automatically. We have to load it
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002161 * only once here.
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002162 * We use the SWBA interrupt only to keep track of the beacon
Bruno Randolf6ba81c22008-03-05 18:36:26 +09002163 * timers in order to detect automatic TSF updates.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002164 */
2165 ath5k_beaconq_config(sc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002166
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002167 sc->imask |= AR5K_INT_SWBA;
2168
2169 if (ath5k_hw_hasveol(ah))
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002170 ath5k_beacon_send(sc);
2171 }
2172 /* TODO else AP */
2173
2174 ath5k_hw_set_intr(ah, sc->imask);
2175}
2176
2177
2178/********************\
2179* Interrupt handling *
2180\********************/
2181
2182static int
2183ath5k_init(struct ath5k_softc *sc)
2184{
2185 int ret;
2186
2187 mutex_lock(&sc->lock);
2188
2189 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2190
2191 /*
2192 * Stop anything previously setup. This is safe
2193 * no matter this is the first time through or not.
2194 */
2195 ath5k_stop_locked(sc);
2196
2197 /*
2198 * The basic interface to setting the hardware in a good
2199 * state is ``reset''. On return the hardware is known to
2200 * be powered up and with interrupts disabled. This must
2201 * be followed by initialization of the appropriate bits
2202 * and then setup of the interrupt mask.
2203 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002204 sc->curchan = sc->hw->conf.channel;
2205 sc->curband = &sc->sbands[sc->curchan->band];
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002206 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2207 if (ret) {
2208 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2209 goto done;
2210 }
2211 /*
2212 * This is needed only to setup initial state
2213 * but it's best done after a reset.
2214 */
2215 ath5k_hw_set_txpower_limit(sc->ah, 0);
2216
2217 /*
2218 * Setup the hardware after reset: the key cache
2219 * is filled as needed and the receive engine is
2220 * set going. Frame transmit is handled entirely
2221 * in the frame output path; there's nothing to do
2222 * here except setup the interrupt mask.
2223 */
2224 ret = ath5k_rx_start(sc);
2225 if (ret)
2226 goto done;
2227
2228 /*
2229 * Enable interrupts.
2230 */
2231 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
Nick Kossifidis194828a2008-04-16 18:49:02 +03002232 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2233 AR5K_INT_MIB;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002234
2235 ath5k_hw_set_intr(sc->ah, sc->imask);
2236 /* Set ack to be sent at low bit-rates */
2237 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2238
2239 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2240 msecs_to_jiffies(ath5k_calinterval * 1000)));
2241
2242 ret = 0;
2243done:
2244 mutex_unlock(&sc->lock);
2245 return ret;
2246}
2247
2248static int
2249ath5k_stop_locked(struct ath5k_softc *sc)
2250{
2251 struct ath5k_hw *ah = sc->ah;
2252
2253 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2254 test_bit(ATH_STAT_INVALID, sc->status));
2255
2256 /*
2257 * Shutdown the hardware and driver:
2258 * stop output from above
2259 * disable interrupts
2260 * turn off timers
2261 * turn off the radio
2262 * clear transmit machinery
2263 * clear receive machinery
2264 * drain and release tx queues
2265 * reclaim beacon resources
2266 * power down hardware
2267 *
2268 * Note that some of this work is not possible if the
2269 * hardware is gone (invalid).
2270 */
2271 ieee80211_stop_queues(sc->hw);
2272
2273 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
Bob Copeland3a078872008-06-25 22:35:28 -04002274 ath5k_led_off(sc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002275 ath5k_hw_set_intr(ah, 0);
2276 }
2277 ath5k_txq_cleanup(sc);
2278 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2279 ath5k_rx_stop(sc);
2280 ath5k_hw_phy_disable(ah);
2281 } else
2282 sc->rxlink = NULL;
2283
2284 return 0;
2285}
2286
2287/*
2288 * Stop the device, grabbing the top-level lock to protect
2289 * against concurrent entry through ath5k_init (which can happen
2290 * if another thread does a system call and the thread doing the
2291 * stop is preempted).
2292 */
2293static int
2294ath5k_stop_hw(struct ath5k_softc *sc)
2295{
2296 int ret;
2297
2298 mutex_lock(&sc->lock);
2299 ret = ath5k_stop_locked(sc);
2300 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2301 /*
2302 * Set the chip in full sleep mode. Note that we are
2303 * careful to do this only when bringing the interface
2304 * completely to a stop. When the chip is in this state
2305 * it must be carefully woken up or references to
2306 * registers in the PCI clock domain may freeze the bus
2307 * (and system). This varies by chip and is mostly an
2308 * issue with newer parts that go to sleep more quickly.
2309 */
2310 if (sc->ah->ah_mac_srev >= 0x78) {
2311 /*
2312 * XXX
2313 * don't put newer MAC revisions > 7.8 to sleep because
2314 * of the above mentioned problems
2315 */
2316 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2317 "not putting device to sleep\n");
2318 } else {
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2320 "putting device to full sleep\n");
2321 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2322 }
2323 }
2324 ath5k_txbuf_free(sc, sc->bbuf);
2325 mutex_unlock(&sc->lock);
2326
2327 del_timer_sync(&sc->calib_tim);
2328
2329 return ret;
2330}
2331
2332static irqreturn_t
2333ath5k_intr(int irq, void *dev_id)
2334{
2335 struct ath5k_softc *sc = dev_id;
2336 struct ath5k_hw *ah = sc->ah;
2337 enum ath5k_int status;
2338 unsigned int counter = 1000;
2339
2340 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2341 !ath5k_hw_is_intr_pending(ah)))
2342 return IRQ_NONE;
2343
2344 do {
2345 /*
2346 * Figure out the reason(s) for the interrupt. Note
2347 * that get_isr returns a pseudo-ISR that may include
2348 * bits we haven't explicitly enabled so we mask the
2349 * value to insure we only process bits we requested.
2350 */
2351 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2352 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2353 status, sc->imask);
2354 status &= sc->imask; /* discard unasked for bits */
2355 if (unlikely(status & AR5K_INT_FATAL)) {
2356 /*
2357 * Fatal errors are unrecoverable.
2358 * Typically these are caused by DMA errors.
2359 */
2360 tasklet_schedule(&sc->restq);
2361 } else if (unlikely(status & AR5K_INT_RXORN)) {
2362 tasklet_schedule(&sc->restq);
2363 } else {
2364 if (status & AR5K_INT_SWBA) {
2365 /*
2366 * Software beacon alert--time to send a beacon.
2367 * Handle beacon transmission directly; deferring
2368 * this is too slow to meet timing constraints
2369 * under load.
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002370 *
2371 * In IBSS mode we use this interrupt just to
2372 * keep track of the next TBTT (target beacon
Bruno Randolf6ba81c22008-03-05 18:36:26 +09002373 * transmission time) in order to detect wether
2374 * automatic TSF updates happened.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002375 */
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002376 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2377 /* XXX: only if VEOL suppported */
2378 u64 tsf = ath5k_hw_get_tsf64(ah);
2379 sc->nexttbtt += sc->bintval;
2380 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
David Miller04f93a82008-02-15 16:08:59 -08002381 "SWBA nexttbtt: %x hw_tu: %x "
2382 "TSF: %llx\n",
2383 sc->nexttbtt,
2384 TSF_TO_TU(tsf),
2385 (unsigned long long) tsf);
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002386 } else {
2387 ath5k_beacon_send(sc);
2388 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002389 }
2390 if (status & AR5K_INT_RXEOL) {
2391 /*
2392 * NB: the hardware should re-read the link when
2393 * RXE bit is written, but it doesn't work at
2394 * least on older hardware revs.
2395 */
2396 sc->rxlink = NULL;
2397 }
2398 if (status & AR5K_INT_TXURN) {
2399 /* bump tx trigger level */
2400 ath5k_hw_update_tx_triglevel(ah, true);
2401 }
2402 if (status & AR5K_INT_RX)
2403 tasklet_schedule(&sc->rxtq);
2404 if (status & AR5K_INT_TX)
2405 tasklet_schedule(&sc->txtq);
2406 if (status & AR5K_INT_BMISS) {
2407 }
2408 if (status & AR5K_INT_MIB) {
Nick Kossifidis194828a2008-04-16 18:49:02 +03002409 /*
2410 * These stats are also used for ANI i think
2411 * so how about updating them more often ?
2412 */
2413 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002414 }
2415 }
2416 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2417
2418 if (unlikely(!counter))
2419 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2420
2421 return IRQ_HANDLED;
2422}
2423
2424static void
2425ath5k_tasklet_reset(unsigned long data)
2426{
2427 struct ath5k_softc *sc = (void *)data;
2428
2429 ath5k_reset(sc->hw);
2430}
2431
2432/*
2433 * Periodically recalibrate the PHY to account
2434 * for temperature/environment changes.
2435 */
2436static void
2437ath5k_calibrate(unsigned long data)
2438{
2439 struct ath5k_softc *sc = (void *)data;
2440 struct ath5k_hw *ah = sc->ah;
2441
2442 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05002443 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2444 sc->curchan->hw_value);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002445
2446 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2447 /*
2448 * Rfgain is out of bounds, reset the chip
2449 * to load new gain values.
2450 */
2451 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2452 ath5k_reset(sc->hw);
2453 }
2454 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2455 ATH5K_ERR(sc, "calibration of channel %u failed\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05002456 ieee80211_frequency_to_channel(
2457 sc->curchan->center_freq));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002458
2459 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2460 msecs_to_jiffies(ath5k_calinterval * 1000)));
2461}
2462
2463
2464
2465/***************\
2466* LED functions *
2467\***************/
2468
2469static void
Bob Copeland3a078872008-06-25 22:35:28 -04002470ath5k_led_enable(struct ath5k_softc *sc)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002471{
Bob Copeland3a078872008-06-25 22:35:28 -04002472 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2473 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2474 ath5k_led_off(sc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002475 }
2476}
2477
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002478static void
Bob Copeland3a078872008-06-25 22:35:28 -04002479ath5k_led_on(struct ath5k_softc *sc)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002480{
Bob Copeland3a078872008-06-25 22:35:28 -04002481 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002482 return;
Bob Copeland3a078872008-06-25 22:35:28 -04002483 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2484}
2485
2486static void
2487ath5k_led_off(struct ath5k_softc *sc)
2488{
2489 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2490 return;
2491 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2492}
2493
2494static void
2495ath5k_led_brightness_set(struct led_classdev *led_dev,
2496 enum led_brightness brightness)
2497{
2498 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2499 led_dev);
2500
2501 if (brightness == LED_OFF)
2502 ath5k_led_off(led->sc);
2503 else
2504 ath5k_led_on(led->sc);
2505}
2506
2507static int
2508ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2509 const char *name, char *trigger)
2510{
2511 int err;
2512
2513 led->sc = sc;
2514 strncpy(led->name, name, sizeof(led->name));
2515 led->led_dev.name = led->name;
2516 led->led_dev.default_trigger = trigger;
2517 led->led_dev.brightness_set = ath5k_led_brightness_set;
2518
2519 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2520 if (err)
2521 {
2522 ATH5K_WARN(sc, "could not register LED %s\n", name);
2523 led->sc = NULL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002524 }
Bob Copeland3a078872008-06-25 22:35:28 -04002525 return err;
2526}
2527
2528static void
2529ath5k_unregister_led(struct ath5k_led *led)
2530{
2531 if (!led->sc)
2532 return;
2533 led_classdev_unregister(&led->led_dev);
2534 ath5k_led_off(led->sc);
2535 led->sc = NULL;
2536}
2537
2538static void
2539ath5k_unregister_leds(struct ath5k_softc *sc)
2540{
2541 ath5k_unregister_led(&sc->rx_led);
2542 ath5k_unregister_led(&sc->tx_led);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002543}
2544
2545
Bob Copeland3a078872008-06-25 22:35:28 -04002546static int
2547ath5k_init_leds(struct ath5k_softc *sc)
2548{
2549 int ret = 0;
2550 struct ieee80211_hw *hw = sc->hw;
2551 struct pci_dev *pdev = sc->pdev;
2552 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2553
2554 sc->led_on = 0; /* active low */
2555
2556 /*
2557 * Auto-enable soft led processing for IBM cards and for
2558 * 5211 minipci cards.
2559 */
2560 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2561 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2562 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2563 sc->led_pin = 0;
2564 }
2565 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2566 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2567 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2568 sc->led_pin = 1;
2569 }
2570 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2571 goto out;
2572
2573 ath5k_led_enable(sc);
2574
2575 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2576 ret = ath5k_register_led(sc, &sc->rx_led, name,
2577 ieee80211_get_rx_led_name(hw));
2578 if (ret)
2579 goto out;
2580
2581 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2582 ret = ath5k_register_led(sc, &sc->tx_led, name,
2583 ieee80211_get_tx_led_name(hw));
2584out:
2585 return ret;
2586}
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002587
2588
2589/********************\
2590* Mac80211 functions *
2591\********************/
2592
2593static int
Johannes Berge039fa42008-05-15 12:55:29 +02002594ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002595{
2596 struct ath5k_softc *sc = hw->priv;
2597 struct ath5k_buf *bf;
Johannes Berga888d522008-05-26 16:43:39 +02002598 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002599 unsigned long flags;
2600 int hdrlen;
2601 int pad;
2602
2603 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2604
2605 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2606 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2607
2608 /*
2609 * the hardware expects the header padded to 4 byte boundaries
2610 * if this is not the case we add the padding after the header
2611 */
2612 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2613 if (hdrlen & 3) {
2614 pad = hdrlen % 4;
2615 if (skb_headroom(skb) < pad) {
2616 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2617 " headroom to pad %d\n", hdrlen, pad);
2618 return -1;
2619 }
2620 skb_push(skb, pad);
2621 memmove(skb->data, skb->data+pad, hdrlen);
2622 }
2623
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002624 spin_lock_irqsave(&sc->txbuflock, flags);
2625 if (list_empty(&sc->txbuf)) {
2626 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2627 spin_unlock_irqrestore(&sc->txbuflock, flags);
Johannes Berge2530082008-05-17 00:57:14 +02002628 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002629 return -1;
2630 }
2631 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2632 list_del(&bf->list);
2633 sc->txbuf_len--;
2634 if (list_empty(&sc->txbuf))
2635 ieee80211_stop_queues(hw);
2636 spin_unlock_irqrestore(&sc->txbuflock, flags);
2637
2638 bf->skb = skb;
2639
Johannes Berge039fa42008-05-15 12:55:29 +02002640 if (ath5k_txbuf_setup(sc, bf)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002641 bf->skb = NULL;
2642 spin_lock_irqsave(&sc->txbuflock, flags);
2643 list_add_tail(&bf->list, &sc->txbuf);
2644 sc->txbuf_len++;
2645 spin_unlock_irqrestore(&sc->txbuflock, flags);
2646 dev_kfree_skb_any(skb);
2647 return 0;
2648 }
2649
2650 return 0;
2651}
2652
2653static int
2654ath5k_reset(struct ieee80211_hw *hw)
2655{
2656 struct ath5k_softc *sc = hw->priv;
2657 struct ath5k_hw *ah = sc->ah;
2658 int ret;
2659
2660 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002661
2662 ath5k_hw_set_intr(ah, 0);
2663 ath5k_txq_cleanup(sc);
2664 ath5k_rx_stop(sc);
2665
2666 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2667 if (unlikely(ret)) {
2668 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2669 goto err;
2670 }
2671 ath5k_hw_set_txpower_limit(sc->ah, 0);
2672
2673 ret = ath5k_rx_start(sc);
2674 if (unlikely(ret)) {
2675 ATH5K_ERR(sc, "can't start recv logic\n");
2676 goto err;
2677 }
2678 /*
2679 * We may be doing a reset in response to an ioctl
2680 * that changes the channel so update any state that
2681 * might change as a result.
2682 *
2683 * XXX needed?
2684 */
2685/* ath5k_chan_change(sc, c); */
2686 ath5k_beacon_config(sc);
2687 /* intrs are started by ath5k_beacon_config */
2688
2689 ieee80211_wake_queues(hw);
2690
2691 return 0;
2692err:
2693 return ret;
2694}
2695
2696static int ath5k_start(struct ieee80211_hw *hw)
2697{
2698 return ath5k_init(hw->priv);
2699}
2700
2701static void ath5k_stop(struct ieee80211_hw *hw)
2702{
2703 ath5k_stop_hw(hw->priv);
2704}
2705
2706static int ath5k_add_interface(struct ieee80211_hw *hw,
2707 struct ieee80211_if_init_conf *conf)
2708{
2709 struct ath5k_softc *sc = hw->priv;
2710 int ret;
2711
2712 mutex_lock(&sc->lock);
Johannes Berg32bfd352007-12-19 01:31:26 +01002713 if (sc->vif) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002714 ret = 0;
2715 goto end;
2716 }
2717
Johannes Berg32bfd352007-12-19 01:31:26 +01002718 sc->vif = conf->vif;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002719
2720 switch (conf->type) {
2721 case IEEE80211_IF_TYPE_STA:
2722 case IEEE80211_IF_TYPE_IBSS:
2723 case IEEE80211_IF_TYPE_MNTR:
2724 sc->opmode = conf->type;
2725 break;
2726 default:
2727 ret = -EOPNOTSUPP;
2728 goto end;
2729 }
2730 ret = 0;
2731end:
2732 mutex_unlock(&sc->lock);
2733 return ret;
2734}
2735
2736static void
2737ath5k_remove_interface(struct ieee80211_hw *hw,
2738 struct ieee80211_if_init_conf *conf)
2739{
2740 struct ath5k_softc *sc = hw->priv;
2741
2742 mutex_lock(&sc->lock);
Johannes Berg32bfd352007-12-19 01:31:26 +01002743 if (sc->vif != conf->vif)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002744 goto end;
2745
Johannes Berg32bfd352007-12-19 01:31:26 +01002746 sc->vif = NULL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002747end:
2748 mutex_unlock(&sc->lock);
2749}
2750
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002751/*
2752 * TODO: Phy disable/diversity etc
2753 */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002754static int
2755ath5k_config(struct ieee80211_hw *hw,
2756 struct ieee80211_conf *conf)
2757{
2758 struct ath5k_softc *sc = hw->priv;
2759
Bruno Randolfe535c1a2008-01-18 21:51:40 +09002760 sc->bintval = conf->beacon_int;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002761 sc->power_level = conf->power_level;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002762
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05002763 return ath5k_chan_set(sc, conf->channel);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002764}
2765
2766static int
Johannes Berg32bfd352007-12-19 01:31:26 +01002767ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002768 struct ieee80211_if_conf *conf)
2769{
2770 struct ath5k_softc *sc = hw->priv;
2771 struct ath5k_hw *ah = sc->ah;
2772 int ret;
2773
2774 /* Set to a reasonable value. Note that this will
2775 * be set to mac80211's value at ath5k_config(). */
Bruno Randolfe535c1a2008-01-18 21:51:40 +09002776 sc->bintval = 1000;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002777 mutex_lock(&sc->lock);
Johannes Berg32bfd352007-12-19 01:31:26 +01002778 if (sc->vif != vif) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002779 ret = -EIO;
2780 goto unlock;
2781 }
2782 if (conf->bssid) {
2783 /* Cache for later use during resets */
2784 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2785 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2786 * a clean way of letting us retrieve this yet. */
2787 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2788 }
2789 mutex_unlock(&sc->lock);
2790
2791 return ath5k_reset(hw);
2792unlock:
2793 mutex_unlock(&sc->lock);
2794 return ret;
2795}
2796
2797#define SUPPORTED_FIF_FLAGS \
2798 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2799 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2800 FIF_BCN_PRBRESP_PROMISC
2801/*
2802 * o always accept unicast, broadcast, and multicast traffic
2803 * o multicast traffic for all BSSIDs will be enabled if mac80211
2804 * says it should be
2805 * o maintain current state of phy ofdm or phy cck error reception.
2806 * If the hardware detects any of these type of errors then
2807 * ath5k_hw_get_rx_filter() will pass to us the respective
2808 * hardware filters to be able to receive these type of frames.
2809 * o probe request frames are accepted only when operating in
2810 * hostap, adhoc, or monitor modes
2811 * o enable promiscuous mode according to the interface state
2812 * o accept beacons:
2813 * - when operating in adhoc mode so the 802.11 layer creates
2814 * node table entries for peers,
2815 * - when operating in station mode for collecting rssi data when
2816 * the station is otherwise quiet, or
2817 * - when scanning
2818 */
2819static void ath5k_configure_filter(struct ieee80211_hw *hw,
2820 unsigned int changed_flags,
2821 unsigned int *new_flags,
2822 int mc_count, struct dev_mc_list *mclist)
2823{
2824 struct ath5k_softc *sc = hw->priv;
2825 struct ath5k_hw *ah = sc->ah;
2826 u32 mfilt[2], val, rfilt;
2827 u8 pos;
2828 int i;
2829
2830 mfilt[0] = 0;
2831 mfilt[1] = 0;
2832
2833 /* Only deal with supported flags */
2834 changed_flags &= SUPPORTED_FIF_FLAGS;
2835 *new_flags &= SUPPORTED_FIF_FLAGS;
2836
2837 /* If HW detects any phy or radar errors, leave those filters on.
2838 * Also, always enable Unicast, Broadcasts and Multicast
2839 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2840 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2841 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2842 AR5K_RX_FILTER_MCAST);
2843
2844 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2845 if (*new_flags & FIF_PROMISC_IN_BSS) {
2846 rfilt |= AR5K_RX_FILTER_PROM;
2847 __set_bit(ATH_STAT_PROMISC, sc->status);
2848 }
2849 else
2850 __clear_bit(ATH_STAT_PROMISC, sc->status);
2851 }
2852
2853 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2854 if (*new_flags & FIF_ALLMULTI) {
2855 mfilt[0] = ~0;
2856 mfilt[1] = ~0;
2857 } else {
2858 for (i = 0; i < mc_count; i++) {
2859 if (!mclist)
2860 break;
2861 /* calculate XOR of eight 6-bit values */
Harvey Harrison533dd1b2008-04-29 01:03:36 -07002862 val = get_unaligned_le32(mclist->dmi_addr + 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002863 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
Harvey Harrison533dd1b2008-04-29 01:03:36 -07002864 val = get_unaligned_le32(mclist->dmi_addr + 3);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002865 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2866 pos &= 0x3f;
2867 mfilt[pos / 32] |= (1 << (pos % 32));
2868 /* XXX: we might be able to just do this instead,
2869 * but not sure, needs testing, if we do use this we'd
2870 * neet to inform below to not reset the mcast */
2871 /* ath5k_hw_set_mcast_filterindex(ah,
2872 * mclist->dmi_addr[5]); */
2873 mclist = mclist->next;
2874 }
2875 }
2876
2877 /* This is the best we can do */
2878 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2879 rfilt |= AR5K_RX_FILTER_PHYERR;
2880
2881 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2882 * and probes for any BSSID, this needs testing */
2883 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2884 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2885
2886 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2887 * set we should only pass on control frames for this
2888 * station. This needs testing. I believe right now this
2889 * enables *all* control frames, which is OK.. but
2890 * but we should see if we can improve on granularity */
2891 if (*new_flags & FIF_CONTROL)
2892 rfilt |= AR5K_RX_FILTER_CONTROL;
2893
2894 /* Additional settings per mode -- this is per ath5k */
2895
2896 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2897
2898 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2899 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2900 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2901 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2902 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2903 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2904 test_bit(ATH_STAT_PROMISC, sc->status))
2905 rfilt |= AR5K_RX_FILTER_PROM;
2906 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2907 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2908 rfilt |= AR5K_RX_FILTER_BEACON;
2909 }
2910
2911 /* Set filters */
2912 ath5k_hw_set_rx_filter(ah,rfilt);
2913
2914 /* Set multicast bits */
2915 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2916 /* Set the cached hw filter flags, this will alter actually
2917 * be set in HW */
2918 sc->filter_flags = rfilt;
2919}
2920
2921static int
2922ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2923 const u8 *local_addr, const u8 *addr,
2924 struct ieee80211_key_conf *key)
2925{
2926 struct ath5k_softc *sc = hw->priv;
2927 int ret = 0;
2928
2929 switch(key->alg) {
2930 case ALG_WEP:
Luis R. Rodriguez6844e632008-02-03 21:53:20 -05002931 /* XXX: fix hardware encryption, its not working. For now
2932 * allow software encryption */
2933 /* break; */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002934 case ALG_TKIP:
2935 case ALG_CCMP:
2936 return -EOPNOTSUPP;
2937 default:
2938 WARN_ON(1);
2939 return -EINVAL;
2940 }
2941
2942 mutex_lock(&sc->lock);
2943
2944 switch (cmd) {
2945 case SET_KEY:
2946 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2947 if (ret) {
2948 ATH5K_ERR(sc, "can't set the key\n");
2949 goto unlock;
2950 }
2951 __set_bit(key->keyidx, sc->keymap);
2952 key->hw_key_idx = key->keyidx;
2953 break;
2954 case DISABLE_KEY:
2955 ath5k_hw_reset_key(sc->ah, key->keyidx);
2956 __clear_bit(key->keyidx, sc->keymap);
2957 break;
2958 default:
2959 ret = -EINVAL;
2960 goto unlock;
2961 }
2962
2963unlock:
2964 mutex_unlock(&sc->lock);
2965 return ret;
2966}
2967
2968static int
2969ath5k_get_stats(struct ieee80211_hw *hw,
2970 struct ieee80211_low_level_stats *stats)
2971{
2972 struct ath5k_softc *sc = hw->priv;
Nick Kossifidis194828a2008-04-16 18:49:02 +03002973 struct ath5k_hw *ah = sc->ah;
2974
2975 /* Force update */
2976 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002977
2978 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2979
2980 return 0;
2981}
2982
2983static int
2984ath5k_get_tx_stats(struct ieee80211_hw *hw,
2985 struct ieee80211_tx_queue_stats *stats)
2986{
2987 struct ath5k_softc *sc = hw->priv;
2988
2989 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2990
2991 return 0;
2992}
2993
2994static u64
2995ath5k_get_tsf(struct ieee80211_hw *hw)
2996{
2997 struct ath5k_softc *sc = hw->priv;
2998
2999 return ath5k_hw_get_tsf64(sc->ah);
3000}
3001
3002static void
3003ath5k_reset_tsf(struct ieee80211_hw *hw)
3004{
3005 struct ath5k_softc *sc = hw->priv;
3006
Bruno Randolf9804b982008-01-19 18:17:59 +09003007 /*
3008 * in IBSS mode we need to update the beacon timers too.
3009 * this will also reset the TSF if we call it with 0
3010 */
3011 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3012 ath5k_beacon_update_timers(sc, 0);
3013 else
3014 ath5k_hw_reset_tsf(sc->ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003015}
3016
3017static int
Johannes Berge039fa42008-05-15 12:55:29 +02003018ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003019{
3020 struct ath5k_softc *sc = hw->priv;
3021 int ret;
3022
3023 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3024
3025 mutex_lock(&sc->lock);
3026
3027 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3028 ret = -EIO;
3029 goto end;
3030 }
3031
3032 ath5k_txbuf_free(sc, sc->bbuf);
3033 sc->bbuf->skb = skb;
Johannes Berge039fa42008-05-15 12:55:29 +02003034 ret = ath5k_beacon_setup(sc, sc->bbuf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02003035 if (ret)
3036 sc->bbuf->skb = NULL;
3037 else
3038 ath5k_beacon_config(sc);
3039
3040end:
3041 mutex_unlock(&sc->lock);
3042 return ret;
3043}
3044