Glenn Streiff | 3c2d774 | 2008-02-04 20:20:45 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006 - 2008 NetEffect, Inc. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | */ |
| 32 | |
| 33 | #ifndef __NES_HW_H |
| 34 | #define __NES_HW_H |
| 35 | |
| 36 | #define NES_PHY_TYPE_1G 2 |
| 37 | #define NES_PHY_TYPE_IRIS 3 |
| 38 | #define NES_PHY_TYPE_PUMA_10G 6 |
| 39 | |
| 40 | #define NES_MULTICAST_PF_MAX 8 |
| 41 | |
| 42 | enum pci_regs { |
| 43 | NES_INT_STAT = 0x0000, |
| 44 | NES_INT_MASK = 0x0004, |
| 45 | NES_INT_PENDING = 0x0008, |
| 46 | NES_INTF_INT_STAT = 0x000C, |
| 47 | NES_INTF_INT_MASK = 0x0010, |
| 48 | NES_TIMER_STAT = 0x0014, |
| 49 | NES_PERIODIC_CONTROL = 0x0018, |
| 50 | NES_ONE_SHOT_CONTROL = 0x001C, |
| 51 | NES_EEPROM_COMMAND = 0x0020, |
| 52 | NES_EEPROM_DATA = 0x0024, |
| 53 | NES_FLASH_COMMAND = 0x0028, |
| 54 | NES_FLASH_DATA = 0x002C, |
| 55 | NES_SOFTWARE_RESET = 0x0030, |
| 56 | NES_CQ_ACK = 0x0034, |
| 57 | NES_WQE_ALLOC = 0x0040, |
| 58 | NES_CQE_ALLOC = 0x0044, |
| 59 | }; |
| 60 | |
| 61 | enum indexed_regs { |
| 62 | NES_IDX_CREATE_CQP_LOW = 0x0000, |
| 63 | NES_IDX_CREATE_CQP_HIGH = 0x0004, |
| 64 | NES_IDX_QP_CONTROL = 0x0040, |
| 65 | NES_IDX_FLM_CONTROL = 0x0080, |
| 66 | NES_IDX_INT_CPU_STATUS = 0x00a0, |
| 67 | NES_IDX_GPIO_CONTROL = 0x00f0, |
| 68 | NES_IDX_GPIO_DATA = 0x00f4, |
| 69 | NES_IDX_TCP_CONFIG0 = 0x01e4, |
| 70 | NES_IDX_TCP_TIMER_CONFIG = 0x01ec, |
| 71 | NES_IDX_TCP_NOW = 0x01f0, |
| 72 | NES_IDX_QP_MAX_CFG_SIZES = 0x0200, |
| 73 | NES_IDX_QP_CTX_SIZE = 0x0218, |
| 74 | NES_IDX_TCP_TIMER_SIZE0 = 0x0238, |
| 75 | NES_IDX_TCP_TIMER_SIZE1 = 0x0240, |
| 76 | NES_IDX_ARP_CACHE_SIZE = 0x0258, |
| 77 | NES_IDX_CQ_CTX_SIZE = 0x0260, |
| 78 | NES_IDX_MRT_SIZE = 0x0278, |
| 79 | NES_IDX_PBL_REGION_SIZE = 0x0280, |
| 80 | NES_IDX_IRRQ_COUNT = 0x02b0, |
| 81 | NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0, |
| 82 | NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300, |
| 83 | NES_IDX_DST_IP_ADDR = 0x0400, |
| 84 | NES_IDX_PCIX_DIAG = 0x08e8, |
| 85 | NES_IDX_MPP_DEBUG = 0x0a00, |
| 86 | NES_IDX_PORT_RX_DISCARDS = 0x0a30, |
| 87 | NES_IDX_PORT_TX_DISCARDS = 0x0a34, |
| 88 | NES_IDX_MPP_LB_DEBUG = 0x0b00, |
| 89 | NES_IDX_DENALI_CTL_22 = 0x1058, |
| 90 | NES_IDX_MAC_TX_CONTROL = 0x2000, |
| 91 | NES_IDX_MAC_TX_CONFIG = 0x2004, |
| 92 | NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008, |
| 93 | NES_IDX_MAC_RX_CONTROL = 0x200c, |
| 94 | NES_IDX_MAC_RX_CONFIG = 0x2010, |
| 95 | NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c, |
| 96 | NES_IDX_MAC_MDIO_CONTROL = 0x2084, |
| 97 | NES_IDX_MAC_TX_OCTETS_LOW = 0x2100, |
| 98 | NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104, |
| 99 | NES_IDX_MAC_TX_FRAMES_LOW = 0x2108, |
| 100 | NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c, |
| 101 | NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118, |
| 102 | NES_IDX_MAC_TX_ERRORS = 0x2138, |
| 103 | NES_IDX_MAC_RX_OCTETS_LOW = 0x213c, |
| 104 | NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140, |
| 105 | NES_IDX_MAC_RX_FRAMES_LOW = 0x2144, |
| 106 | NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148, |
| 107 | NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c, |
| 108 | NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150, |
| 109 | NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154, |
| 110 | NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174, |
| 111 | NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178, |
| 112 | NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c, |
| 113 | NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180, |
| 114 | NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184, |
| 115 | NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188, |
| 116 | NES_IDX_MAC_INT_STATUS = 0x21f0, |
| 117 | NES_IDX_MAC_INT_MASK = 0x21f4, |
| 118 | NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800, |
| 119 | NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00, |
| 120 | NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808, |
| 121 | NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08, |
| 122 | NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c, |
| 123 | NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c, |
| 124 | NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810, |
| 125 | NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10, |
| 126 | NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814, |
| 127 | NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14, |
| 128 | NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818, |
| 129 | NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18, |
| 130 | NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c, |
| 131 | NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c, |
| 132 | NES_IDX_ETH_SERDES_BYPASS0 = 0x2820, |
| 133 | NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20, |
| 134 | NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824, |
| 135 | NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24, |
| 136 | NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828, |
| 137 | NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28, |
| 138 | NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c, |
| 139 | NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c, |
| 140 | NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830, |
| 141 | NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30, |
| 142 | NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834, |
| 143 | NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34, |
| 144 | NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838, |
| 145 | NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38, |
| 146 | NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080, |
| 147 | NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000, |
| 148 | NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004, |
| 149 | NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008, |
| 150 | NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c, |
| 151 | NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000, |
| 152 | NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004, |
| 153 | NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008, |
| 154 | NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c, |
| 155 | NES_IDX_CM_CONFIG = 0x5100, |
| 156 | NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000, |
| 157 | NES_IDX_NIC_PHYPORT_TO_USW = 0x6008, |
| 158 | NES_IDX_NIC_ACTIVE = 0x6010, |
| 159 | NES_IDX_NIC_UNICAST_ALL = 0x6018, |
| 160 | NES_IDX_NIC_MULTICAST_ALL = 0x6020, |
| 161 | NES_IDX_NIC_MULTICAST_ENABLE = 0x6028, |
| 162 | NES_IDX_NIC_BROADCAST_ON = 0x6030, |
| 163 | NES_IDX_USED_CHUNKS_TX = 0x60b0, |
| 164 | NES_IDX_TX_POOL_SIZE = 0x60b8, |
| 165 | NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148, |
| 166 | NES_IDX_PERFECT_FILTER_LOW = 0x6200, |
| 167 | NES_IDX_PERFECT_FILTER_HIGH = 0x6204, |
| 168 | NES_IDX_IPV4_TCP_REXMITS = 0x7080, |
| 169 | NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c, |
| 170 | NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140, |
| 171 | NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144, |
| 172 | NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148, |
| 173 | NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c, |
| 174 | NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150, |
| 175 | NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154, |
| 176 | }; |
| 177 | |
| 178 | #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE 1 |
| 179 | #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17) |
| 180 | |
| 181 | enum nes_cqp_opcodes { |
| 182 | NES_CQP_CREATE_QP = 0x00, |
| 183 | NES_CQP_MODIFY_QP = 0x01, |
| 184 | NES_CQP_DESTROY_QP = 0x02, |
| 185 | NES_CQP_CREATE_CQ = 0x03, |
| 186 | NES_CQP_MODIFY_CQ = 0x04, |
| 187 | NES_CQP_DESTROY_CQ = 0x05, |
| 188 | NES_CQP_ALLOCATE_STAG = 0x09, |
| 189 | NES_CQP_REGISTER_STAG = 0x0a, |
| 190 | NES_CQP_QUERY_STAG = 0x0b, |
| 191 | NES_CQP_REGISTER_SHARED_STAG = 0x0c, |
| 192 | NES_CQP_DEALLOCATE_STAG = 0x0d, |
| 193 | NES_CQP_MANAGE_ARP_CACHE = 0x0f, |
| 194 | NES_CQP_SUSPEND_QPS = 0x11, |
| 195 | NES_CQP_UPLOAD_CONTEXT = 0x13, |
| 196 | NES_CQP_CREATE_CEQ = 0x16, |
| 197 | NES_CQP_DESTROY_CEQ = 0x18, |
| 198 | NES_CQP_CREATE_AEQ = 0x19, |
| 199 | NES_CQP_DESTROY_AEQ = 0x1b, |
| 200 | NES_CQP_LMI_ACCESS = 0x20, |
| 201 | NES_CQP_FLUSH_WQES = 0x22, |
| 202 | NES_CQP_MANAGE_APBVT = 0x23 |
| 203 | }; |
| 204 | |
| 205 | enum nes_cqp_wqe_word_idx { |
| 206 | NES_CQP_WQE_OPCODE_IDX = 0, |
| 207 | NES_CQP_WQE_ID_IDX = 1, |
| 208 | NES_CQP_WQE_COMP_CTX_LOW_IDX = 2, |
| 209 | NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3, |
| 210 | NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4, |
| 211 | NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5, |
| 212 | }; |
| 213 | |
| 214 | enum nes_cqp_cq_wqeword_idx { |
| 215 | NES_CQP_CQ_WQE_PBL_LOW_IDX = 6, |
| 216 | NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7, |
| 217 | NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8, |
| 218 | NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9, |
| 219 | NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10, |
| 220 | }; |
| 221 | |
| 222 | enum nes_cqp_stag_wqeword_idx { |
| 223 | NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1, |
| 224 | NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6, |
| 225 | NES_CQP_STAG_WQE_LEN_LOW_IDX = 7, |
| 226 | NES_CQP_STAG_WQE_STAG_IDX = 8, |
| 227 | NES_CQP_STAG_WQE_VA_LOW_IDX = 10, |
| 228 | NES_CQP_STAG_WQE_VA_HIGH_IDX = 11, |
| 229 | NES_CQP_STAG_WQE_PA_LOW_IDX = 12, |
| 230 | NES_CQP_STAG_WQE_PA_HIGH_IDX = 13, |
| 231 | NES_CQP_STAG_WQE_PBL_LEN_IDX = 14 |
| 232 | }; |
| 233 | |
| 234 | #define NES_CQP_OP_IWARP_STATE_SHIFT 28 |
| 235 | |
| 236 | enum nes_cqp_qp_bits { |
| 237 | NES_CQP_QP_ARP_VALID = (1<<8), |
| 238 | NES_CQP_QP_WINBUF_VALID = (1<<9), |
| 239 | NES_CQP_QP_CONTEXT_VALID = (1<<10), |
| 240 | NES_CQP_QP_ORD_VALID = (1<<11), |
| 241 | NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12), |
| 242 | NES_CQP_QP_VIRT_WQS = (1<<13), |
| 243 | NES_CQP_QP_DEL_HTE = (1<<14), |
| 244 | NES_CQP_QP_CQS_VALID = (1<<15), |
| 245 | NES_CQP_QP_TYPE_TSA = 0, |
| 246 | NES_CQP_QP_TYPE_IWARP = (1<<16), |
| 247 | NES_CQP_QP_TYPE_CQP = (4<<16), |
| 248 | NES_CQP_QP_TYPE_NIC = (5<<16), |
| 249 | NES_CQP_QP_MSS_CHG = (1<<20), |
| 250 | NES_CQP_QP_STATIC_RESOURCES = (1<<21), |
| 251 | NES_CQP_QP_IGNORE_MW_BOUND = (1<<22), |
| 252 | NES_CQP_QP_VWQ_USE_LMI = (1<<23), |
| 253 | NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT), |
| 254 | NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT), |
| 255 | NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT), |
| 256 | NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT), |
| 257 | NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT), |
| 258 | NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT), |
| 259 | NES_CQP_QP_RESET = (1<<31), |
| 260 | }; |
| 261 | |
| 262 | enum nes_cqp_qp_wqe_word_idx { |
| 263 | NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6, |
| 264 | NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7, |
| 265 | NES_CQP_QP_WQE_NEW_MSS_IDX = 15, |
| 266 | }; |
| 267 | |
| 268 | enum nes_nic_ctx_bits { |
| 269 | NES_NIC_CTX_RQ_SIZE_32 = (3<<8), |
| 270 | NES_NIC_CTX_RQ_SIZE_512 = (3<<8), |
| 271 | NES_NIC_CTX_SQ_SIZE_32 = (1<<10), |
| 272 | NES_NIC_CTX_SQ_SIZE_512 = (3<<10), |
| 273 | }; |
| 274 | |
| 275 | enum nes_nic_qp_ctx_word_idx { |
| 276 | NES_NIC_CTX_MISC_IDX = 0, |
| 277 | NES_NIC_CTX_SQ_LOW_IDX = 2, |
| 278 | NES_NIC_CTX_SQ_HIGH_IDX = 3, |
| 279 | NES_NIC_CTX_RQ_LOW_IDX = 4, |
| 280 | NES_NIC_CTX_RQ_HIGH_IDX = 5, |
| 281 | }; |
| 282 | |
| 283 | enum nes_cqp_cq_bits { |
| 284 | NES_CQP_CQ_CEQE_MASK = (1<<9), |
| 285 | NES_CQP_CQ_CEQ_VALID = (1<<10), |
| 286 | NES_CQP_CQ_RESIZE = (1<<11), |
| 287 | NES_CQP_CQ_CHK_OVERFLOW = (1<<12), |
| 288 | NES_CQP_CQ_4KB_CHUNK = (1<<14), |
| 289 | NES_CQP_CQ_VIRT = (1<<15), |
| 290 | }; |
| 291 | |
| 292 | enum nes_cqp_stag_bits { |
| 293 | NES_CQP_STAG_VA_TO = (1<<9), |
| 294 | NES_CQP_STAG_DEALLOC_PBLS = (1<<10), |
| 295 | NES_CQP_STAG_PBL_BLK_SIZE = (1<<11), |
| 296 | NES_CQP_STAG_MR = (1<<13), |
| 297 | NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16), |
| 298 | NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17), |
| 299 | NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18), |
| 300 | NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19), |
| 301 | NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20), |
| 302 | NES_CQP_STAG_REM_ACC_EN = (1<<21), |
| 303 | NES_CQP_STAG_LEAVE_PENDING = (1<<31), |
| 304 | }; |
| 305 | |
| 306 | enum nes_cqp_ceq_wqeword_idx { |
| 307 | NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1, |
| 308 | NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6, |
| 309 | NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7, |
| 310 | }; |
| 311 | |
| 312 | enum nes_cqp_ceq_bits { |
| 313 | NES_CQP_CEQ_4KB_CHUNK = (1<<14), |
| 314 | NES_CQP_CEQ_VIRT = (1<<15), |
| 315 | }; |
| 316 | |
| 317 | enum nes_cqp_aeq_wqeword_idx { |
| 318 | NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1, |
| 319 | NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6, |
| 320 | NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7, |
| 321 | }; |
| 322 | |
| 323 | enum nes_cqp_aeq_bits { |
| 324 | NES_CQP_AEQ_4KB_CHUNK = (1<<14), |
| 325 | NES_CQP_AEQ_VIRT = (1<<15), |
| 326 | }; |
| 327 | |
| 328 | enum nes_cqp_lmi_wqeword_idx { |
| 329 | NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1, |
| 330 | NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8, |
| 331 | NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9, |
| 332 | NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10, |
| 333 | }; |
| 334 | |
| 335 | enum nes_cqp_arp_wqeword_idx { |
| 336 | NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6, |
| 337 | NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7, |
| 338 | NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1, |
| 339 | }; |
| 340 | |
| 341 | enum nes_cqp_upload_wqeword_idx { |
| 342 | NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6, |
| 343 | NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7, |
| 344 | NES_CQP_UPLOAD_WQE_HTE_IDX = 8, |
| 345 | }; |
| 346 | |
| 347 | enum nes_cqp_arp_bits { |
| 348 | NES_CQP_ARP_VALID = (1<<8), |
| 349 | NES_CQP_ARP_PERM = (1<<9), |
| 350 | }; |
| 351 | |
| 352 | enum nes_cqp_flush_bits { |
| 353 | NES_CQP_FLUSH_SQ = (1<<30), |
| 354 | NES_CQP_FLUSH_RQ = (1<<31), |
| 355 | }; |
| 356 | |
| 357 | enum nes_cqe_opcode_bits { |
| 358 | NES_CQE_STAG_VALID = (1<<6), |
| 359 | NES_CQE_ERROR = (1<<7), |
| 360 | NES_CQE_SQ = (1<<8), |
| 361 | NES_CQE_SE = (1<<9), |
| 362 | NES_CQE_PSH = (1<<29), |
| 363 | NES_CQE_FIN = (1<<30), |
| 364 | NES_CQE_VALID = (1<<31), |
| 365 | }; |
| 366 | |
| 367 | |
| 368 | enum nes_cqe_word_idx { |
| 369 | NES_CQE_PAYLOAD_LENGTH_IDX = 0, |
| 370 | NES_CQE_COMP_COMP_CTX_LOW_IDX = 2, |
| 371 | NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3, |
| 372 | NES_CQE_INV_STAG_IDX = 4, |
| 373 | NES_CQE_QP_ID_IDX = 5, |
| 374 | NES_CQE_ERROR_CODE_IDX = 6, |
| 375 | NES_CQE_OPCODE_IDX = 7, |
| 376 | }; |
| 377 | |
| 378 | enum nes_ceqe_word_idx { |
| 379 | NES_CEQE_CQ_CTX_LOW_IDX = 0, |
| 380 | NES_CEQE_CQ_CTX_HIGH_IDX = 1, |
| 381 | }; |
| 382 | |
| 383 | enum nes_ceqe_status_bit { |
| 384 | NES_CEQE_VALID = (1<<31), |
| 385 | }; |
| 386 | |
| 387 | enum nes_int_bits { |
| 388 | NES_INT_CEQ0 = (1<<0), |
| 389 | NES_INT_CEQ1 = (1<<1), |
| 390 | NES_INT_CEQ2 = (1<<2), |
| 391 | NES_INT_CEQ3 = (1<<3), |
| 392 | NES_INT_CEQ4 = (1<<4), |
| 393 | NES_INT_CEQ5 = (1<<5), |
| 394 | NES_INT_CEQ6 = (1<<6), |
| 395 | NES_INT_CEQ7 = (1<<7), |
| 396 | NES_INT_CEQ8 = (1<<8), |
| 397 | NES_INT_CEQ9 = (1<<9), |
| 398 | NES_INT_CEQ10 = (1<<10), |
| 399 | NES_INT_CEQ11 = (1<<11), |
| 400 | NES_INT_CEQ12 = (1<<12), |
| 401 | NES_INT_CEQ13 = (1<<13), |
| 402 | NES_INT_CEQ14 = (1<<14), |
| 403 | NES_INT_CEQ15 = (1<<15), |
| 404 | NES_INT_AEQ0 = (1<<16), |
| 405 | NES_INT_AEQ1 = (1<<17), |
| 406 | NES_INT_AEQ2 = (1<<18), |
| 407 | NES_INT_AEQ3 = (1<<19), |
| 408 | NES_INT_AEQ4 = (1<<20), |
| 409 | NES_INT_AEQ5 = (1<<21), |
| 410 | NES_INT_AEQ6 = (1<<22), |
| 411 | NES_INT_AEQ7 = (1<<23), |
| 412 | NES_INT_MAC0 = (1<<24), |
| 413 | NES_INT_MAC1 = (1<<25), |
| 414 | NES_INT_MAC2 = (1<<26), |
| 415 | NES_INT_MAC3 = (1<<27), |
| 416 | NES_INT_TSW = (1<<28), |
| 417 | NES_INT_TIMER = (1<<29), |
| 418 | NES_INT_INTF = (1<<30), |
| 419 | }; |
| 420 | |
| 421 | enum nes_intf_int_bits { |
| 422 | NES_INTF_INT_PCIERR = (1<<0), |
| 423 | NES_INTF_PERIODIC_TIMER = (1<<2), |
| 424 | NES_INTF_ONE_SHOT_TIMER = (1<<3), |
| 425 | NES_INTF_INT_CRITERR = (1<<14), |
| 426 | NES_INTF_INT_AEQ0_OFLOW = (1<<16), |
| 427 | NES_INTF_INT_AEQ1_OFLOW = (1<<17), |
| 428 | NES_INTF_INT_AEQ2_OFLOW = (1<<18), |
| 429 | NES_INTF_INT_AEQ3_OFLOW = (1<<19), |
| 430 | NES_INTF_INT_AEQ4_OFLOW = (1<<20), |
| 431 | NES_INTF_INT_AEQ5_OFLOW = (1<<21), |
| 432 | NES_INTF_INT_AEQ6_OFLOW = (1<<22), |
| 433 | NES_INTF_INT_AEQ7_OFLOW = (1<<23), |
| 434 | NES_INTF_INT_AEQ_OFLOW = (0xff<<16), |
| 435 | }; |
| 436 | |
| 437 | enum nes_mac_int_bits { |
| 438 | NES_MAC_INT_LINK_STAT_CHG = (1<<1), |
| 439 | NES_MAC_INT_XGMII_EXT = (1<<2), |
| 440 | NES_MAC_INT_TX_UNDERFLOW = (1<<6), |
| 441 | NES_MAC_INT_TX_ERROR = (1<<7), |
| 442 | }; |
| 443 | |
| 444 | enum nes_cqe_allocate_bits { |
| 445 | NES_CQE_ALLOC_INC_SELECT = (1<<28), |
| 446 | NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29), |
| 447 | NES_CQE_ALLOC_NOTIFY_SE = (1<<30), |
| 448 | NES_CQE_ALLOC_RESET = (1<<31), |
| 449 | }; |
| 450 | |
| 451 | enum nes_nic_rq_wqe_word_idx { |
| 452 | NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0, |
| 453 | NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1, |
| 454 | NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2, |
| 455 | NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3, |
| 456 | NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4, |
| 457 | NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5, |
| 458 | NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6, |
| 459 | NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7, |
| 460 | NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8, |
| 461 | NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9, |
| 462 | }; |
| 463 | |
| 464 | enum nes_nic_sq_wqe_word_idx { |
| 465 | NES_NIC_SQ_WQE_MISC_IDX = 0, |
| 466 | NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1, |
| 467 | NES_NIC_SQ_WQE_LSO_INFO_IDX = 2, |
| 468 | NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3, |
| 469 | NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4, |
| 470 | NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5, |
| 471 | NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6, |
| 472 | NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7, |
| 473 | NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8, |
| 474 | NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9, |
| 475 | NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10, |
| 476 | NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11, |
| 477 | NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12, |
| 478 | NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13, |
| 479 | NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14, |
| 480 | NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15, |
| 481 | }; |
| 482 | |
| 483 | enum nes_iwarp_sq_wqe_word_idx { |
| 484 | NES_IWARP_SQ_WQE_MISC_IDX = 0, |
| 485 | NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1, |
| 486 | NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2, |
| 487 | NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3, |
| 488 | NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4, |
| 489 | NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5, |
| 490 | NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7, |
| 491 | NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8, |
| 492 | NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9, |
| 493 | NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10, |
| 494 | NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11, |
| 495 | NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12, |
| 496 | NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16, |
| 497 | NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17, |
| 498 | NES_IWARP_SQ_WQE_LENGTH0_IDX = 18, |
| 499 | NES_IWARP_SQ_WQE_STAG0_IDX = 19, |
| 500 | NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20, |
| 501 | NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21, |
| 502 | NES_IWARP_SQ_WQE_LENGTH1_IDX = 22, |
| 503 | NES_IWARP_SQ_WQE_STAG1_IDX = 23, |
| 504 | NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24, |
| 505 | NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25, |
| 506 | NES_IWARP_SQ_WQE_LENGTH2_IDX = 26, |
| 507 | NES_IWARP_SQ_WQE_STAG2_IDX = 27, |
| 508 | NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28, |
| 509 | NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29, |
| 510 | NES_IWARP_SQ_WQE_LENGTH3_IDX = 30, |
| 511 | NES_IWARP_SQ_WQE_STAG3_IDX = 31, |
| 512 | }; |
| 513 | |
| 514 | enum nes_iwarp_sq_bind_wqe_word_idx { |
| 515 | NES_IWARP_SQ_BIND_WQE_MR_IDX = 6, |
| 516 | NES_IWARP_SQ_BIND_WQE_MW_IDX = 7, |
| 517 | NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8, |
| 518 | NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9, |
| 519 | NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10, |
| 520 | NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11, |
| 521 | }; |
| 522 | |
| 523 | enum nes_iwarp_sq_fmr_wqe_word_idx { |
| 524 | NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7, |
| 525 | NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8, |
| 526 | NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9, |
| 527 | NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10, |
| 528 | NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11, |
| 529 | NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12, |
| 530 | NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13, |
| 531 | NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14, |
| 532 | }; |
| 533 | |
| 534 | enum nes_iwarp_sq_locinv_wqe_word_idx { |
| 535 | NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6, |
| 536 | }; |
| 537 | |
| 538 | |
| 539 | enum nes_iwarp_rq_wqe_word_idx { |
| 540 | NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1, |
| 541 | NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2, |
| 542 | NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3, |
| 543 | NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4, |
| 544 | NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5, |
| 545 | NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8, |
| 546 | NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9, |
| 547 | NES_IWARP_RQ_WQE_LENGTH0_IDX = 10, |
| 548 | NES_IWARP_RQ_WQE_STAG0_IDX = 11, |
| 549 | NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12, |
| 550 | NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13, |
| 551 | NES_IWARP_RQ_WQE_LENGTH1_IDX = 14, |
| 552 | NES_IWARP_RQ_WQE_STAG1_IDX = 15, |
| 553 | NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16, |
| 554 | NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17, |
| 555 | NES_IWARP_RQ_WQE_LENGTH2_IDX = 18, |
| 556 | NES_IWARP_RQ_WQE_STAG2_IDX = 19, |
| 557 | NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20, |
| 558 | NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21, |
| 559 | NES_IWARP_RQ_WQE_LENGTH3_IDX = 22, |
| 560 | NES_IWARP_RQ_WQE_STAG3_IDX = 23, |
| 561 | }; |
| 562 | |
| 563 | enum nes_nic_sq_wqe_bits { |
| 564 | NES_NIC_SQ_WQE_PHDR_CS_READY = (1<<21), |
| 565 | NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22), |
| 566 | NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23), |
| 567 | NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30), |
| 568 | NES_NIC_SQ_WQE_COMPLETION = (1<<31), |
| 569 | }; |
| 570 | |
| 571 | enum nes_nic_cqe_word_idx { |
| 572 | NES_NIC_CQE_ACCQP_ID_IDX = 0, |
| 573 | NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2, |
| 574 | NES_NIC_CQE_MISC_IDX = 3, |
| 575 | }; |
| 576 | |
| 577 | #define NES_PKT_TYPE_APBVT_BITS 0xC112 |
| 578 | #define NES_PKT_TYPE_APBVT_MASK 0xff3e |
| 579 | |
| 580 | #define NES_PKT_TYPE_PVALID_BITS 0x10000000 |
| 581 | #define NES_PKT_TYPE_PVALID_MASK 0x30000000 |
| 582 | |
| 583 | #define NES_PKT_TYPE_TCPV4_BITS 0x0110 |
| 584 | #define NES_PKT_TYPE_TCPV4_MASK 0x3f30 |
| 585 | |
| 586 | #define NES_PKT_TYPE_UDPV4_BITS 0x0210 |
| 587 | #define NES_PKT_TYPE_UDPV4_MASK 0x3f30 |
| 588 | |
| 589 | #define NES_PKT_TYPE_IPV4_BITS 0x0010 |
| 590 | #define NES_PKT_TYPE_IPV4_MASK 0x3f30 |
| 591 | |
| 592 | #define NES_PKT_TYPE_OTHER_BITS 0x0000 |
| 593 | #define NES_PKT_TYPE_OTHER_MASK 0x0030 |
| 594 | |
| 595 | #define NES_NIC_CQE_ERRV_SHIFT 16 |
| 596 | enum nes_nic_ev_bits { |
| 597 | NES_NIC_ERRV_BITS_MODE = (1<<0), |
| 598 | NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1), |
| 599 | NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2), |
| 600 | NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3), |
| 601 | NES_NIC_ERRV_BITS_IPH_ERR = (1<<4), |
| 602 | }; |
| 603 | |
| 604 | enum nes_nic_cqe_bits { |
| 605 | NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT), |
| 606 | NES_NIC_CQE_SQ = (1<<24), |
| 607 | NES_NIC_CQE_ACCQP_PORT = (1<<28), |
| 608 | NES_NIC_CQE_ACCQP_VALID = (1<<29), |
| 609 | NES_NIC_CQE_TAG_VALID = (1<<30), |
| 610 | NES_NIC_CQE_VALID = (1<<31), |
| 611 | }; |
| 612 | |
| 613 | enum nes_aeqe_word_idx { |
| 614 | NES_AEQE_COMP_CTXT_LOW_IDX = 0, |
| 615 | NES_AEQE_COMP_CTXT_HIGH_IDX = 1, |
| 616 | NES_AEQE_COMP_QP_CQ_ID_IDX = 2, |
| 617 | NES_AEQE_MISC_IDX = 3, |
| 618 | }; |
| 619 | |
| 620 | enum nes_aeqe_bits { |
| 621 | NES_AEQE_QP = (1<<16), |
| 622 | NES_AEQE_CQ = (1<<17), |
| 623 | NES_AEQE_SQ = (1<<18), |
| 624 | NES_AEQE_INBOUND_RDMA = (1<<19), |
| 625 | NES_AEQE_IWARP_STATE_MASK = (7<<20), |
| 626 | NES_AEQE_TCP_STATE_MASK = (0xf<<24), |
| 627 | NES_AEQE_VALID = (1<<31), |
| 628 | }; |
| 629 | |
| 630 | #define NES_AEQE_IWARP_STATE_SHIFT 20 |
| 631 | #define NES_AEQE_TCP_STATE_SHIFT 24 |
| 632 | |
| 633 | enum nes_aeqe_iwarp_state { |
| 634 | NES_AEQE_IWARP_STATE_NON_EXISTANT = 0, |
| 635 | NES_AEQE_IWARP_STATE_IDLE = 1, |
| 636 | NES_AEQE_IWARP_STATE_RTS = 2, |
| 637 | NES_AEQE_IWARP_STATE_CLOSING = 3, |
| 638 | NES_AEQE_IWARP_STATE_TERMINATE = 5, |
| 639 | NES_AEQE_IWARP_STATE_ERROR = 6 |
| 640 | }; |
| 641 | |
| 642 | enum nes_aeqe_tcp_state { |
| 643 | NES_AEQE_TCP_STATE_NON_EXISTANT = 0, |
| 644 | NES_AEQE_TCP_STATE_CLOSED = 1, |
| 645 | NES_AEQE_TCP_STATE_LISTEN = 2, |
| 646 | NES_AEQE_TCP_STATE_SYN_SENT = 3, |
| 647 | NES_AEQE_TCP_STATE_SYN_RCVD = 4, |
| 648 | NES_AEQE_TCP_STATE_ESTABLISHED = 5, |
| 649 | NES_AEQE_TCP_STATE_CLOSE_WAIT = 6, |
| 650 | NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7, |
| 651 | NES_AEQE_TCP_STATE_CLOSING = 8, |
| 652 | NES_AEQE_TCP_STATE_LAST_ACK = 9, |
| 653 | NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10, |
| 654 | NES_AEQE_TCP_STATE_TIME_WAIT = 11 |
| 655 | }; |
| 656 | |
| 657 | enum nes_aeqe_aeid { |
| 658 | NES_AEQE_AEID_AMP_UNALLOCATED_STAG = 0x0102, |
| 659 | NES_AEQE_AEID_AMP_INVALID_STAG = 0x0103, |
| 660 | NES_AEQE_AEID_AMP_BAD_QP = 0x0104, |
| 661 | NES_AEQE_AEID_AMP_BAD_PD = 0x0105, |
| 662 | NES_AEQE_AEID_AMP_BAD_STAG_KEY = 0x0106, |
| 663 | NES_AEQE_AEID_AMP_BAD_STAG_INDEX = 0x0107, |
| 664 | NES_AEQE_AEID_AMP_BOUNDS_VIOLATION = 0x0108, |
| 665 | NES_AEQE_AEID_AMP_RIGHTS_VIOLATION = 0x0109, |
| 666 | NES_AEQE_AEID_AMP_TO_WRAP = 0x010a, |
| 667 | NES_AEQE_AEID_AMP_FASTREG_SHARED = 0x010b, |
| 668 | NES_AEQE_AEID_AMP_FASTREG_VALID_STAG = 0x010c, |
| 669 | NES_AEQE_AEID_AMP_FASTREG_MW_STAG = 0x010d, |
| 670 | NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS = 0x010e, |
| 671 | NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW = 0x010f, |
| 672 | NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH = 0x0110, |
| 673 | NES_AEQE_AEID_AMP_INVALIDATE_SHARED = 0x0111, |
| 674 | NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS = 0x0112, |
| 675 | NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS = 0x0113, |
| 676 | NES_AEQE_AEID_AMP_MWBIND_VALID_STAG = 0x0114, |
| 677 | NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG = 0x0115, |
| 678 | NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG = 0x0116, |
| 679 | NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG = 0x0117, |
| 680 | NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS = 0x0118, |
| 681 | NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS = 0x0119, |
| 682 | NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT = 0x011a, |
| 683 | NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED = 0x011b, |
| 684 | NES_AEQE_AEID_BAD_CLOSE = 0x0201, |
| 685 | NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE = 0x0202, |
| 686 | NES_AEQE_AEID_CQ_OPERATION_ERROR = 0x0203, |
| 687 | NES_AEQE_AEID_PRIV_OPERATION_DENIED = 0x0204, |
| 688 | NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO = 0x0205, |
| 689 | NES_AEQE_AEID_STAG_ZERO_INVALID = 0x0206, |
| 690 | NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN = 0x0301, |
| 691 | NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID = 0x0302, |
| 692 | NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303, |
| 693 | NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION = 0x0304, |
| 694 | NES_AEQE_AEID_DDP_UBE_INVALID_MO = 0x0305, |
| 695 | NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE = 0x0306, |
| 696 | NES_AEQE_AEID_DDP_UBE_INVALID_QN = 0x0307, |
| 697 | NES_AEQE_AEID_DDP_NO_L_BIT = 0x0308, |
| 698 | NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION = 0x0311, |
| 699 | NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE = 0x0312, |
| 700 | NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST = 0x0313, |
| 701 | NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP = 0x0314, |
| 702 | NES_AEQE_AEID_INVALID_ARP_ENTRY = 0x0401, |
| 703 | NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD = 0x0402, |
| 704 | NES_AEQE_AEID_STALE_ARP_ENTRY = 0x0403, |
| 705 | NES_AEQE_AEID_LLP_CLOSE_COMPLETE = 0x0501, |
| 706 | NES_AEQE_AEID_LLP_CONNECTION_RESET = 0x0502, |
| 707 | NES_AEQE_AEID_LLP_FIN_RECEIVED = 0x0503, |
| 708 | NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH = 0x0504, |
| 709 | NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR = 0x0505, |
| 710 | NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE = 0x0506, |
| 711 | NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL = 0x0507, |
| 712 | NES_AEQE_AEID_LLP_SYN_RECEIVED = 0x0508, |
| 713 | NES_AEQE_AEID_LLP_TERMINATE_RECEIVED = 0x0509, |
| 714 | NES_AEQE_AEID_LLP_TOO_MANY_RETRIES = 0x050a, |
| 715 | NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES = 0x050b, |
| 716 | NES_AEQE_AEID_RESET_SENT = 0x0601, |
| 717 | NES_AEQE_AEID_TERMINATE_SENT = 0x0602, |
| 718 | NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC = 0x0700 |
| 719 | }; |
| 720 | |
| 721 | enum nes_iwarp_sq_opcodes { |
| 722 | NES_IWARP_SQ_WQE_WRPDU = (1<<15), |
| 723 | NES_IWARP_SQ_WQE_PSH = (1<<21), |
| 724 | NES_IWARP_SQ_WQE_STREAMING = (1<<23), |
| 725 | NES_IWARP_SQ_WQE_IMM_DATA = (1<<28), |
| 726 | NES_IWARP_SQ_WQE_READ_FENCE = (1<<29), |
| 727 | NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30), |
| 728 | NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31), |
| 729 | }; |
| 730 | |
| 731 | enum nes_iwarp_sq_wqe_bits { |
| 732 | NES_IWARP_SQ_OP_RDMAW = 0, |
| 733 | NES_IWARP_SQ_OP_RDMAR = 1, |
| 734 | NES_IWARP_SQ_OP_SEND = 3, |
| 735 | NES_IWARP_SQ_OP_SENDINV = 4, |
| 736 | NES_IWARP_SQ_OP_SENDSE = 5, |
| 737 | NES_IWARP_SQ_OP_SENDSEINV = 6, |
| 738 | NES_IWARP_SQ_OP_BIND = 8, |
| 739 | NES_IWARP_SQ_OP_FAST_REG = 9, |
| 740 | NES_IWARP_SQ_OP_LOCINV = 10, |
| 741 | NES_IWARP_SQ_OP_RDMAR_LOCINV = 11, |
| 742 | NES_IWARP_SQ_OP_NOP = 12, |
| 743 | }; |
| 744 | |
| 745 | #define NES_EEPROM_READ_REQUEST (1<<16) |
| 746 | #define NES_MAC_ADDR_VALID (1<<20) |
| 747 | |
| 748 | /* |
| 749 | * NES index registers init values. |
| 750 | */ |
| 751 | struct nes_init_values { |
| 752 | u32 index; |
| 753 | u32 data; |
| 754 | u8 wrt; |
| 755 | }; |
| 756 | |
| 757 | /* |
| 758 | * NES registers in BAR0. |
| 759 | */ |
| 760 | struct nes_pci_regs { |
| 761 | u32 int_status; |
| 762 | u32 int_mask; |
| 763 | u32 int_pending; |
| 764 | u32 intf_int_status; |
| 765 | u32 intf_int_mask; |
| 766 | u32 other_regs[59]; /* pad out to 256 bytes for now */ |
| 767 | }; |
| 768 | |
| 769 | #define NES_CQP_SQ_SIZE 128 |
| 770 | #define NES_CCQ_SIZE 128 |
| 771 | #define NES_NIC_WQ_SIZE 512 |
| 772 | #define NES_NIC_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512)) |
| 773 | #define NES_NIC_BACK_STORE 0x00038000 |
| 774 | |
| 775 | struct nes_device; |
| 776 | |
| 777 | struct nes_hw_nic_qp_context { |
| 778 | __le32 context_words[6]; |
| 779 | }; |
| 780 | |
| 781 | struct nes_hw_nic_sq_wqe { |
| 782 | __le32 wqe_words[16]; |
| 783 | }; |
| 784 | |
| 785 | struct nes_hw_nic_rq_wqe { |
| 786 | __le32 wqe_words[16]; |
| 787 | }; |
| 788 | |
| 789 | struct nes_hw_nic_cqe { |
| 790 | __le32 cqe_words[4]; |
| 791 | }; |
| 792 | |
| 793 | struct nes_hw_cqp_qp_context { |
| 794 | __le32 context_words[4]; |
| 795 | }; |
| 796 | |
| 797 | struct nes_hw_cqp_wqe { |
| 798 | __le32 wqe_words[16]; |
| 799 | }; |
| 800 | |
| 801 | struct nes_hw_qp_wqe { |
| 802 | __le32 wqe_words[32]; |
| 803 | }; |
| 804 | |
| 805 | struct nes_hw_cqe { |
| 806 | __le32 cqe_words[8]; |
| 807 | }; |
| 808 | |
| 809 | struct nes_hw_ceqe { |
| 810 | __le32 ceqe_words[2]; |
| 811 | }; |
| 812 | |
| 813 | struct nes_hw_aeqe { |
| 814 | __le32 aeqe_words[4]; |
| 815 | }; |
| 816 | |
| 817 | struct nes_cqp_request { |
| 818 | union { |
| 819 | u64 cqp_callback_context; |
| 820 | void *cqp_callback_pointer; |
| 821 | }; |
| 822 | wait_queue_head_t waitq; |
| 823 | struct nes_hw_cqp_wqe cqp_wqe; |
| 824 | struct list_head list; |
| 825 | atomic_t refcount; |
| 826 | void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request); |
| 827 | u16 major_code; |
| 828 | u16 minor_code; |
| 829 | u8 waiting; |
| 830 | u8 request_done; |
| 831 | u8 dynamic; |
| 832 | u8 callback; |
| 833 | }; |
| 834 | |
| 835 | struct nes_hw_cqp { |
| 836 | struct nes_hw_cqp_wqe *sq_vbase; |
| 837 | dma_addr_t sq_pbase; |
| 838 | spinlock_t lock; |
| 839 | wait_queue_head_t waitq; |
| 840 | u16 qp_id; |
| 841 | u16 sq_head; |
| 842 | u16 sq_tail; |
| 843 | u16 sq_size; |
| 844 | }; |
| 845 | |
| 846 | #define NES_FIRST_FRAG_SIZE 128 |
| 847 | struct nes_first_frag { |
| 848 | u8 buffer[NES_FIRST_FRAG_SIZE]; |
| 849 | }; |
| 850 | |
| 851 | struct nes_hw_nic { |
| 852 | struct nes_first_frag *first_frag_vbase; /* virtual address of first frags */ |
| 853 | struct nes_hw_nic_sq_wqe *sq_vbase; /* virtual address of sq */ |
| 854 | struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */ |
| 855 | struct sk_buff *tx_skb[NES_NIC_WQ_SIZE]; |
| 856 | struct sk_buff *rx_skb[NES_NIC_WQ_SIZE]; |
| 857 | dma_addr_t frag_paddr[NES_NIC_WQ_SIZE]; |
| 858 | unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)]; |
| 859 | dma_addr_t sq_pbase; /* PCI memory for host rings */ |
| 860 | dma_addr_t rq_pbase; /* PCI memory for host rings */ |
| 861 | |
| 862 | u16 qp_id; |
| 863 | u16 sq_head; |
| 864 | u16 sq_tail; |
| 865 | u16 sq_size; |
| 866 | u16 rq_head; |
| 867 | u16 rq_tail; |
| 868 | u16 rq_size; |
| 869 | u8 replenishing_rq; |
| 870 | u8 reserved; |
| 871 | |
| 872 | spinlock_t sq_lock; |
| 873 | spinlock_t rq_lock; |
| 874 | }; |
| 875 | |
| 876 | struct nes_hw_nic_cq { |
| 877 | struct nes_hw_nic_cqe volatile *cq_vbase; /* PCI memory for host rings */ |
| 878 | void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq); |
| 879 | dma_addr_t cq_pbase; /* PCI memory for host rings */ |
| 880 | int rx_cqes_completed; |
| 881 | int cqe_allocs_pending; |
| 882 | int rx_pkts_indicated; |
| 883 | u16 cq_head; |
| 884 | u16 cq_size; |
| 885 | u16 cq_number; |
| 886 | u8 cqes_pending; |
| 887 | }; |
| 888 | |
| 889 | struct nes_hw_qp { |
| 890 | struct nes_hw_qp_wqe *sq_vbase; /* PCI memory for host rings */ |
| 891 | struct nes_hw_qp_wqe *rq_vbase; /* PCI memory for host rings */ |
| 892 | void *q2_vbase; /* PCI memory for host rings */ |
| 893 | dma_addr_t sq_pbase; /* PCI memory for host rings */ |
| 894 | dma_addr_t rq_pbase; /* PCI memory for host rings */ |
| 895 | dma_addr_t q2_pbase; /* PCI memory for host rings */ |
| 896 | u32 qp_id; |
| 897 | u16 sq_head; |
| 898 | u16 sq_tail; |
| 899 | u16 sq_size; |
| 900 | u16 rq_head; |
| 901 | u16 rq_tail; |
| 902 | u16 rq_size; |
| 903 | u8 rq_encoded_size; |
| 904 | u8 sq_encoded_size; |
| 905 | }; |
| 906 | |
| 907 | struct nes_hw_cq { |
| 908 | struct nes_hw_cqe volatile *cq_vbase; /* PCI memory for host rings */ |
| 909 | void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq); |
| 910 | dma_addr_t cq_pbase; /* PCI memory for host rings */ |
| 911 | u16 cq_head; |
| 912 | u16 cq_size; |
| 913 | u16 cq_number; |
| 914 | }; |
| 915 | |
| 916 | struct nes_hw_ceq { |
| 917 | struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */ |
| 918 | dma_addr_t ceq_pbase; /* PCI memory for host rings */ |
| 919 | u16 ceq_head; |
| 920 | u16 ceq_size; |
| 921 | }; |
| 922 | |
| 923 | struct nes_hw_aeq { |
| 924 | struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */ |
| 925 | dma_addr_t aeq_pbase; /* PCI memory for host rings */ |
| 926 | u16 aeq_head; |
| 927 | u16 aeq_size; |
| 928 | }; |
| 929 | |
| 930 | struct nic_qp_map { |
| 931 | u8 qpid; |
| 932 | u8 nic_index; |
| 933 | u8 logical_port; |
| 934 | u8 is_hnic; |
| 935 | }; |
| 936 | |
| 937 | #define NES_CQP_ARP_AEQ_INDEX_MASK 0x000f0000 |
| 938 | #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16 |
| 939 | |
| 940 | #define NES_CQP_APBVT_ADD 0x00008000 |
| 941 | #define NES_CQP_APBVT_NIC_SHIFT 16 |
| 942 | |
| 943 | #define NES_ARP_ADD 1 |
| 944 | #define NES_ARP_DELETE 2 |
| 945 | #define NES_ARP_RESOLVE 3 |
| 946 | |
| 947 | #define NES_MAC_SW_IDLE 0 |
| 948 | #define NES_MAC_SW_INTERRUPT 1 |
| 949 | #define NES_MAC_SW_MH 2 |
| 950 | |
| 951 | struct nes_arp_entry { |
| 952 | u32 ip_addr; |
| 953 | u8 mac_addr[ETH_ALEN]; |
| 954 | }; |
| 955 | |
| 956 | #define NES_NIC_FAST_TIMER 96 |
| 957 | #define NES_NIC_FAST_TIMER_LOW 40 |
| 958 | #define NES_NIC_FAST_TIMER_HIGH 1000 |
| 959 | #define DEFAULT_NES_QL_HIGH 256 |
| 960 | #define DEFAULT_NES_QL_LOW 16 |
| 961 | #define DEFAULT_NES_QL_TARGET 64 |
| 962 | #define DEFAULT_JUMBO_NES_QL_LOW 12 |
| 963 | #define DEFAULT_JUMBO_NES_QL_TARGET 40 |
| 964 | #define DEFAULT_JUMBO_NES_QL_HIGH 128 |
| 965 | #define NES_NIC_CQ_DOWNWARD_TREND 8 |
| 966 | |
| 967 | struct nes_hw_tune_timer { |
| 968 | //u16 cq_count; |
| 969 | u16 threshold_low; |
| 970 | u16 threshold_target; |
| 971 | u16 threshold_high; |
| 972 | u16 timer_in_use; |
| 973 | u16 timer_in_use_old; |
| 974 | u16 timer_in_use_min; |
| 975 | u16 timer_in_use_max; |
| 976 | u8 timer_direction_upward; |
| 977 | u8 timer_direction_downward; |
| 978 | u16 cq_count_old; |
| 979 | u8 cq_direction_downward; |
| 980 | }; |
| 981 | |
| 982 | #define NES_TIMER_INT_LIMIT 2 |
| 983 | #define NES_TIMER_INT_LIMIT_DYNAMIC 10 |
| 984 | #define NES_TIMER_ENABLE_LIMIT 4 |
| 985 | #define NES_MAX_LINK_INTERRUPTS 128 |
| 986 | #define NES_MAX_LINK_CHECK 200 |
| 987 | |
| 988 | struct nes_adapter { |
| 989 | u64 fw_ver; |
| 990 | unsigned long *allocated_qps; |
| 991 | unsigned long *allocated_cqs; |
| 992 | unsigned long *allocated_mrs; |
| 993 | unsigned long *allocated_pds; |
| 994 | unsigned long *allocated_arps; |
| 995 | struct nes_qp **qp_table; |
| 996 | struct workqueue_struct *work_q; |
| 997 | |
| 998 | struct list_head list; |
| 999 | struct list_head active_listeners; |
| 1000 | /* list of the netdev's associated with each logical port */ |
| 1001 | struct list_head nesvnic_list[4]; |
| 1002 | |
| 1003 | struct timer_list mh_timer; |
| 1004 | struct timer_list lc_timer; |
| 1005 | struct work_struct work; |
| 1006 | spinlock_t resource_lock; |
| 1007 | spinlock_t phy_lock; |
| 1008 | spinlock_t pbl_lock; |
| 1009 | spinlock_t periodic_timer_lock; |
| 1010 | |
| 1011 | struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE]; |
| 1012 | |
| 1013 | /* Adapter CEQ and AEQs */ |
| 1014 | struct nes_hw_ceq ceq[16]; |
| 1015 | struct nes_hw_aeq aeq[8]; |
| 1016 | |
| 1017 | struct nes_hw_tune_timer tune_timer; |
| 1018 | |
| 1019 | unsigned long doorbell_start; |
| 1020 | |
| 1021 | u32 hw_rev; |
| 1022 | u32 vendor_id; |
| 1023 | u32 vendor_part_id; |
| 1024 | u32 device_cap_flags; |
| 1025 | u32 tick_delta; |
| 1026 | u32 timer_int_req; |
| 1027 | u32 arp_table_size; |
| 1028 | u32 next_arp_index; |
| 1029 | |
| 1030 | u32 max_mr; |
| 1031 | u32 max_256pbl; |
| 1032 | u32 max_4kpbl; |
| 1033 | u32 free_256pbl; |
| 1034 | u32 free_4kpbl; |
| 1035 | u32 max_mr_size; |
| 1036 | u32 max_qp; |
| 1037 | u32 next_qp; |
| 1038 | u32 max_irrq; |
| 1039 | u32 max_qp_wr; |
| 1040 | u32 max_sge; |
| 1041 | u32 max_cq; |
| 1042 | u32 next_cq; |
| 1043 | u32 max_cqe; |
| 1044 | u32 max_pd; |
| 1045 | u32 base_pd; |
| 1046 | u32 next_pd; |
| 1047 | u32 hte_index_mask; |
| 1048 | |
| 1049 | /* EEPROM information */ |
| 1050 | u32 rx_pool_size; |
| 1051 | u32 tx_pool_size; |
| 1052 | u32 rx_threshold; |
| 1053 | u32 tcp_timer_core_clk_divisor; |
| 1054 | u32 iwarp_config; |
| 1055 | u32 cm_config; |
| 1056 | u32 sws_timer_config; |
| 1057 | u32 tcp_config1; |
| 1058 | u32 wqm_wat; |
| 1059 | u32 core_clock; |
| 1060 | u32 firmware_version; |
| 1061 | |
| 1062 | u32 nic_rx_eth_route_err; |
| 1063 | |
| 1064 | u32 et_rx_coalesce_usecs; |
| 1065 | u32 et_rx_max_coalesced_frames; |
| 1066 | u32 et_rx_coalesce_usecs_irq; |
| 1067 | u32 et_rx_max_coalesced_frames_irq; |
| 1068 | u32 et_pkt_rate_low; |
| 1069 | u32 et_rx_coalesce_usecs_low; |
| 1070 | u32 et_rx_max_coalesced_frames_low; |
| 1071 | u32 et_pkt_rate_high; |
| 1072 | u32 et_rx_coalesce_usecs_high; |
| 1073 | u32 et_rx_max_coalesced_frames_high; |
| 1074 | u32 et_rate_sample_interval; |
| 1075 | u32 timer_int_limit; |
| 1076 | |
| 1077 | /* Adapter base MAC address */ |
| 1078 | u32 mac_addr_low; |
| 1079 | u16 mac_addr_high; |
| 1080 | |
| 1081 | u16 firmware_eeprom_offset; |
| 1082 | u16 software_eeprom_offset; |
| 1083 | |
| 1084 | u16 max_irrq_wr; |
| 1085 | |
| 1086 | /* pd config for each port */ |
| 1087 | u16 pd_config_size[4]; |
| 1088 | u16 pd_config_base[4]; |
| 1089 | |
| 1090 | u16 link_interrupt_count[4]; |
| 1091 | |
| 1092 | /* the phy index for each port */ |
| 1093 | u8 phy_index[4]; |
| 1094 | u8 mac_sw_state[4]; |
| 1095 | u8 mac_link_down[4]; |
| 1096 | u8 phy_type[4]; |
| 1097 | |
| 1098 | /* PCI information */ |
| 1099 | unsigned int devfn; |
| 1100 | unsigned char bus_number; |
| 1101 | unsigned char OneG_Mode; |
| 1102 | |
| 1103 | unsigned char ref_count; |
| 1104 | u8 netdev_count; |
| 1105 | u8 netdev_max; /* from host nic address count in EEPROM */ |
| 1106 | u8 port_count; |
| 1107 | u8 virtwq; |
| 1108 | u8 et_use_adaptive_rx_coalesce; |
| 1109 | u8 adapter_fcn_count; |
| 1110 | }; |
| 1111 | |
| 1112 | struct nes_pbl { |
| 1113 | u64 *pbl_vbase; |
| 1114 | dma_addr_t pbl_pbase; |
| 1115 | struct page *page; |
| 1116 | unsigned long user_base; |
| 1117 | u32 pbl_size; |
| 1118 | struct list_head list; |
| 1119 | /* TODO: need to add list for two level tables */ |
| 1120 | }; |
| 1121 | |
| 1122 | struct nes_listener { |
| 1123 | struct work_struct work; |
| 1124 | struct workqueue_struct *wq; |
| 1125 | struct nes_vnic *nesvnic; |
| 1126 | struct iw_cm_id *cm_id; |
| 1127 | struct list_head list; |
| 1128 | unsigned long socket; |
| 1129 | u8 accept_failed; |
| 1130 | }; |
| 1131 | |
| 1132 | struct nes_ib_device; |
| 1133 | |
| 1134 | struct nes_vnic { |
| 1135 | struct nes_ib_device *nesibdev; |
| 1136 | u64 sq_full; |
| 1137 | u64 sq_locked; |
| 1138 | u64 tso_requests; |
| 1139 | u64 segmented_tso_requests; |
| 1140 | u64 linearized_skbs; |
| 1141 | u64 tx_sw_dropped; |
| 1142 | u64 endnode_nstat_rx_discard; |
| 1143 | u64 endnode_nstat_rx_octets; |
| 1144 | u64 endnode_nstat_rx_frames; |
| 1145 | u64 endnode_nstat_tx_octets; |
| 1146 | u64 endnode_nstat_tx_frames; |
| 1147 | u64 endnode_ipv4_tcp_retransmits; |
| 1148 | /* void *mem; */ |
| 1149 | struct nes_device *nesdev; |
| 1150 | struct net_device *netdev; |
| 1151 | struct vlan_group *vlan_grp; |
| 1152 | atomic_t rx_skbs_needed; |
| 1153 | atomic_t rx_skb_timer_running; |
| 1154 | int budget; |
| 1155 | u32 msg_enable; |
| 1156 | /* u32 tx_avail; */ |
| 1157 | __be32 local_ipaddr; |
| 1158 | struct napi_struct napi; |
| 1159 | spinlock_t tx_lock; /* could use netdev tx lock? */ |
| 1160 | struct timer_list rq_wqes_timer; |
| 1161 | u32 nic_mem_size; |
| 1162 | void *nic_vbase; |
| 1163 | dma_addr_t nic_pbase; |
| 1164 | struct nes_hw_nic nic; |
| 1165 | struct nes_hw_nic_cq nic_cq; |
| 1166 | u32 mcrq_qp_id; |
| 1167 | struct nes_ucontext *mcrq_ucontext; |
| 1168 | struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev); |
| 1169 | void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *, int); |
| 1170 | int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr ); |
| 1171 | struct net_device_stats netstats; |
| 1172 | /* used to put the netdev on the adapters logical port list */ |
| 1173 | struct list_head list; |
| 1174 | u16 max_frame_size; |
| 1175 | u8 netdev_open; |
| 1176 | u8 linkup; |
| 1177 | u8 logical_port; |
| 1178 | u8 netdev_index; /* might not be needed, indexes nesdev->netdev */ |
| 1179 | u8 perfect_filter_index; |
| 1180 | u8 nic_index; |
| 1181 | u8 qp_nic_index[4]; |
| 1182 | u8 next_qp_nic_index; |
| 1183 | u8 of_device_registered; |
| 1184 | u8 rdma_enabled; |
| 1185 | u8 rx_checksum_disabled; |
| 1186 | }; |
| 1187 | |
| 1188 | struct nes_ib_device { |
| 1189 | struct ib_device ibdev; |
| 1190 | struct nes_vnic *nesvnic; |
| 1191 | |
| 1192 | /* Virtual RNIC Limits */ |
| 1193 | u32 max_mr; |
| 1194 | u32 max_qp; |
| 1195 | u32 max_cq; |
| 1196 | u32 max_pd; |
| 1197 | u32 num_mr; |
| 1198 | u32 num_qp; |
| 1199 | u32 num_cq; |
| 1200 | u32 num_pd; |
| 1201 | }; |
| 1202 | |
| 1203 | #define nes_vlan_rx vlan_hwaccel_receive_skb |
| 1204 | #define nes_netif_rx netif_receive_skb |
| 1205 | |
| 1206 | #endif /* __NES_HW_H */ |