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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 3f2bc4d6eb5a4fada842462ba22bb6bbb41d00c7 / . / arch / arm / mach-msm / devices-8064.c
blob: 3c4fe1b2385ac7649855b9ed6686431694f5a71c [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame^]1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/platform_device.h>
17#include <linux/msm_rotator.h>
18#include <linux/clkdev.h>
19#include <mach/irqs-8064.h>
20#include <mach/board.h>
21#include <mach/msm_iomap.h>
22#include "clock.h"
23#include "devices.h"
24
25/* Address of GSBI blocks */
26#define MSM_GSBI3_PHYS 0x16200000
27#define MSM_UART3DM_PHYS (MSM_GSBI3_PHYS + 0x40000)
28
29static struct resource resources_uart_gsbi3[] = {
30 {
31 .start = GSBI3_UARTDM_IRQ,
32 .end = GSBI3_UARTDM_IRQ,
33 .flags = IORESOURCE_IRQ,
34 },
35 {
36 .start = MSM_UART3DM_PHYS,
37 .end = MSM_UART3DM_PHYS + PAGE_SIZE - 1,
38 .name = "uartdm_resource",
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .start = MSM_GSBI3_PHYS,
43 .end = MSM_GSBI3_PHYS + PAGE_SIZE - 1,
44 .name = "gsbi_resource",
45 .flags = IORESOURCE_MEM,
46 },
47};
48
49struct platform_device apq8064_device_uart_gsbi3 = {
50 .name = "msm_serial_hsl",
51 .id = 0,
52 .num_resources = ARRAY_SIZE(resources_uart_gsbi3),
53 .resource = resources_uart_gsbi3,
54};
55
56static struct resource resources_qup_spi_gsbi5[] = {
57 {
58 .name = "spi_base",
59 .start = MSM_GSBI5_QUP_PHYS,
60 .end = MSM_GSBI5_QUP_PHYS + SZ_4K - 1,
61 .flags = IORESOURCE_MEM,
62 },
63 {
64 .name = "gsbi_base",
65 .start = MSM_GSBI5_PHYS,
66 .end = MSM_GSBI5_PHYS + 4 - 1,
67 .flags = IORESOURCE_MEM,
68 },
69 {
70 .name = "spi_irq_in",
71 .start = GSBI5_QUP_IRQ,
72 .end = GSBI5_QUP_IRQ,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77struct platform_device apq8064_device_qup_spi_gsbi5 = {
78 .name = "spi_qsd",
79 .id = 0,
80 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi5),
81 .resource = resources_qup_spi_gsbi5,
82};
83
84static struct resource resources_ssbi_pmic1[] = {
85 {
86 .start = MSM_PMIC1_SSBI_CMD_PHYS,
87 .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
88 .flags = IORESOURCE_MEM,
89 },
90};
91
92struct platform_device apq8064_device_ssbi_pmic1 = {
93 .name = "msm_ssbi",
94 .id = 0,
95 .resource = resources_ssbi_pmic1,
96 .num_resources = ARRAY_SIZE(resources_ssbi_pmic1),
97};
98
99static struct resource resources_ssbi_pmic2[] = {
100 {
101 .start = MSM_PMIC2_SSBI_CMD_PHYS,
102 .end = MSM_PMIC2_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
103 .flags = IORESOURCE_MEM,
104 },
105};
106
107struct platform_device apq8064_device_ssbi_pmic2 = {
108 .name = "msm_ssbi",
109 .id = 1,
110 .resource = resources_ssbi_pmic2,
111 .num_resources = ARRAY_SIZE(resources_ssbi_pmic2),
112};
113
114static struct resource resources_otg[] = {
115 {
116 .start = MSM_HSUSB_PHYS,
117 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 {
121 .start = USB1_HS_IRQ,
122 .end = USB1_HS_IRQ,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127struct platform_device msm_device_otg = {
128 .name = "msm_otg",
129 .id = -1,
130 .num_resources = ARRAY_SIZE(resources_otg),
131 .resource = resources_otg,
132 .dev = {
133 .coherent_dma_mask = 0xffffffff,
134 },
135};
136
137static struct resource resources_hsusb[] = {
138 {
139 .start = MSM_HSUSB_PHYS,
140 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE - 1,
141 .flags = IORESOURCE_MEM,
142 },
143 {
144 .start = USB1_HS_IRQ,
145 .end = USB1_HS_IRQ,
146 .flags = IORESOURCE_IRQ,
147 },
148};
149
150struct platform_device msm_device_gadget_peripheral = {
151 .name = "msm_hsusb",
152 .id = -1,
153 .num_resources = ARRAY_SIZE(resources_hsusb),
154 .resource = resources_hsusb,
155 .dev = {
156 .coherent_dma_mask = 0xffffffff,
157 },
158};
159
160#define MSM_SDC1_BASE 0x12400000
161#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
162#define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000)
163#define MSM_SDC2_BASE 0x12140000
164#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
165#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
166#define MSM_SDC3_BASE 0x12180000
167#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
168#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
169#define MSM_SDC4_BASE 0x121C0000
170#define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800)
171#define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000)
172
173static struct resource resources_sdc1[] = {
174 {
175 .name = "core_mem",
176 .flags = IORESOURCE_MEM,
177 .start = MSM_SDC1_BASE,
178 .end = MSM_SDC1_DML_BASE - 1,
179 },
180 {
181 .name = "core_irq",
182 .flags = IORESOURCE_IRQ,
183 .start = SDC1_IRQ_0,
184 .end = SDC1_IRQ_0
185 },
186#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
187 {
188 .name = "sdcc_dml_addr",
189 .start = MSM_SDC1_DML_BASE,
190 .end = MSM_SDC1_BAM_BASE - 1,
191 .flags = IORESOURCE_MEM,
192 },
193 {
194 .name = "sdcc_bam_addr",
195 .start = MSM_SDC1_BAM_BASE,
196 .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 {
200 .name = "sdcc_bam_irq",
201 .start = SDC1_BAM_IRQ,
202 .end = SDC1_BAM_IRQ,
203 .flags = IORESOURCE_IRQ,
204 },
205#endif
206};
207
208static struct resource resources_sdc2[] = {
209 {
210 .name = "core_mem",
211 .flags = IORESOURCE_MEM,
212 .start = MSM_SDC2_BASE,
213 .end = MSM_SDC2_DML_BASE - 1,
214 },
215 {
216 .name = "core_irq",
217 .flags = IORESOURCE_IRQ,
218 .start = SDC2_IRQ_0,
219 .end = SDC2_IRQ_0
220 },
221#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
222 {
223 .name = "sdcc_dml_addr",
224 .start = MSM_SDC2_DML_BASE,
225 .end = MSM_SDC2_BAM_BASE - 1,
226 .flags = IORESOURCE_MEM,
227 },
228 {
229 .name = "sdcc_bam_addr",
230 .start = MSM_SDC2_BAM_BASE,
231 .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .name = "sdcc_bam_irq",
236 .start = SDC2_BAM_IRQ,
237 .end = SDC2_BAM_IRQ,
238 .flags = IORESOURCE_IRQ,
239 },
240#endif
241};
242
243static struct resource resources_sdc3[] = {
244 {
245 .name = "core_mem",
246 .flags = IORESOURCE_MEM,
247 .start = MSM_SDC3_BASE,
248 .end = MSM_SDC3_DML_BASE - 1,
249 },
250 {
251 .name = "core_irq",
252 .flags = IORESOURCE_IRQ,
253 .start = SDC3_IRQ_0,
254 .end = SDC3_IRQ_0
255 },
256#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
257 {
258 .name = "sdcc_dml_addr",
259 .start = MSM_SDC3_DML_BASE,
260 .end = MSM_SDC3_BAM_BASE - 1,
261 .flags = IORESOURCE_MEM,
262 },
263 {
264 .name = "sdcc_bam_addr",
265 .start = MSM_SDC3_BAM_BASE,
266 .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1,
267 .flags = IORESOURCE_MEM,
268 },
269 {
270 .name = "sdcc_bam_irq",
271 .start = SDC3_BAM_IRQ,
272 .end = SDC3_BAM_IRQ,
273 .flags = IORESOURCE_IRQ,
274 },
275#endif
276};
277
278static struct resource resources_sdc4[] = {
279 {
280 .name = "core_mem",
281 .flags = IORESOURCE_MEM,
282 .start = MSM_SDC4_BASE,
283 .end = MSM_SDC4_DML_BASE - 1,
284 },
285 {
286 .name = "core_irq",
287 .flags = IORESOURCE_IRQ,
288 .start = SDC4_IRQ_0,
289 .end = SDC4_IRQ_0
290 },
291#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
292 {
293 .name = "sdcc_dml_addr",
294 .start = MSM_SDC4_DML_BASE,
295 .end = MSM_SDC4_BAM_BASE - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .name = "sdcc_bam_addr",
300 .start = MSM_SDC4_BAM_BASE,
301 .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .name = "sdcc_bam_irq",
306 .start = SDC4_BAM_IRQ,
307 .end = SDC4_BAM_IRQ,
308 .flags = IORESOURCE_IRQ,
309 },
310#endif
311};
312
313struct platform_device apq8064_device_sdc1 = {
314 .name = "msm_sdcc",
315 .id = 1,
316 .num_resources = ARRAY_SIZE(resources_sdc1),
317 .resource = resources_sdc1,
318 .dev = {
319 .coherent_dma_mask = 0xffffffff,
320 },
321};
322
323struct platform_device apq8064_device_sdc2 = {
324 .name = "msm_sdcc",
325 .id = 2,
326 .num_resources = ARRAY_SIZE(resources_sdc2),
327 .resource = resources_sdc2,
328 .dev = {
329 .coherent_dma_mask = 0xffffffff,
330 },
331};
332
333struct platform_device apq8064_device_sdc3 = {
334 .name = "msm_sdcc",
335 .id = 3,
336 .num_resources = ARRAY_SIZE(resources_sdc3),
337 .resource = resources_sdc3,
338 .dev = {
339 .coherent_dma_mask = 0xffffffff,
340 },
341};
342
343struct platform_device apq8064_device_sdc4 = {
344 .name = "msm_sdcc",
345 .id = 4,
346 .num_resources = ARRAY_SIZE(resources_sdc4),
347 .resource = resources_sdc4,
348 .dev = {
349 .coherent_dma_mask = 0xffffffff,
350 },
351};
352
353static struct platform_device *apq8064_sdcc_devices[] __initdata = {
354 &apq8064_device_sdc1,
355 &apq8064_device_sdc2,
356 &apq8064_device_sdc3,
357 &apq8064_device_sdc4,
358};
359
360int __init apq8064_add_sdcc(unsigned int controller,
361 struct mmc_platform_data *plat)
362{
363 struct platform_device *pdev;
364
365 if (!plat)
366 return 0;
367 if (controller < 1 || controller > 4)
368 return -EINVAL;
369
370 pdev = apq8064_sdcc_devices[controller-1];
371 pdev->dev.platform_data = plat;
372 return platform_device_register(pdev);
373}
374
375static struct clk_lookup msm_clocks_8064_dummy[] = {
376 CLK_DUMMY("pll2", PLL2, NULL, 0),
377 CLK_DUMMY("pll8", PLL8, NULL, 0),
378 CLK_DUMMY("pll4", PLL4, NULL, 0),
379
380 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
381 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
382 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
383 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
384 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
385 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
386 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
387 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
388 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
389 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
390 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
391 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
392 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
393 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
394 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
395 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
396
397 CLK_DUMMY("gsbi_uart_clk", GSBI1_UART_CLK, NULL, OFF),
398 CLK_DUMMY("gsbi_uart_clk", GSBI2_UART_CLK, NULL, OFF),
399 CLK_DUMMY("gsbi_uart_clk", GSBI3_UART_CLK,
400 "msm_serial_hsl.0", OFF),
401 CLK_DUMMY("gsbi_uart_clk", GSBI4_UART_CLK, NULL, OFF),
402 CLK_DUMMY("gsbi_uart_clk", GSBI5_UART_CLK, NULL, OFF),
403 CLK_DUMMY("uartdm_clk", GSBI6_UART_CLK, NULL, OFF),
404 CLK_DUMMY("gsbi_uart_clk", GSBI7_UART_CLK, NULL, OFF),
405 CLK_DUMMY("gsbi_uart_clk", GSBI8_UART_CLK, NULL, OFF),
406 CLK_DUMMY("gsbi_uart_clk", GSBI9_UART_CLK, NULL, OFF),
407 CLK_DUMMY("gsbi_uart_clk", GSBI10_UART_CLK, NULL, OFF),
408 CLK_DUMMY("gsbi_uart_clk", GSBI11_UART_CLK, NULL, OFF),
409 CLK_DUMMY("gsbi_uart_clk", GSBI12_UART_CLK, NULL, OFF),
410 CLK_DUMMY("spi_clk", GSBI1_QUP_CLK, NULL, OFF),
411 CLK_DUMMY("gsbi_qup_clk", GSBI2_QUP_CLK, NULL, OFF),
412 CLK_DUMMY("gsbi_qup_clk", GSBI3_QUP_CLK, NULL, OFF),
413 CLK_DUMMY("gsbi_qup_clk", GSBI4_QUP_CLK, NULL, OFF),
414 CLK_DUMMY("gsbi_qup_clk", GSBI5_QUP_CLK, NULL, OFF),
415 CLK_DUMMY("gsbi_qup_clk", GSBI6_QUP_CLK, NULL, OFF),
416 CLK_DUMMY("gsbi_qup_clk", GSBI7_QUP_CLK, NULL, OFF),
417 CLK_DUMMY("gsbi_qup_clk", GSBI8_QUP_CLK, NULL, OFF),
418 CLK_DUMMY("gsbi_qup_clk", GSBI9_QUP_CLK, NULL, OFF),
419 CLK_DUMMY("gsbi_qup_clk", GSBI10_QUP_CLK, NULL, OFF),
420 CLK_DUMMY("gsbi_qup_clk", GSBI11_QUP_CLK, NULL, OFF),
421 CLK_DUMMY("gsbi_qup_clk", GSBI12_QUP_CLK, NULL, OFF),
422 CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
423 CLK_DUMMY("pmem_clk", PMEM_CLK, NULL, OFF),
424 CLK_DUMMY("prng_clk", PRNG_CLK, NULL, OFF),
425 CLK_DUMMY("sdc_clk", SDC1_CLK, NULL, OFF),
426 CLK_DUMMY("sdc_clk", SDC2_CLK, NULL, OFF),
427 CLK_DUMMY("sdc_clk", SDC3_CLK, NULL, OFF),
428 CLK_DUMMY("sdc_clk", SDC4_CLK, NULL, OFF),
429 CLK_DUMMY("sdc_clk", SDC5_CLK, NULL, OFF),
430 CLK_DUMMY("tsif_ref_clk", TSIF_REF_CLK, NULL, OFF),
431 CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
432 CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
433 CLK_DUMMY("usb_phy_clk", USB_PHY0_CLK, NULL, OFF),
434 CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
435 CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL, OFF),
436 CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
437 CLK_DUMMY("usb_fs_src_clk", USB_FS2_SRC_CLK, NULL, OFF),
438 CLK_DUMMY("usb_fs_clk", USB_FS2_XCVR_CLK, NULL, OFF),
439 CLK_DUMMY("usb_fs_sys_clk", USB_FS2_SYS_CLK, NULL, OFF),
440 CLK_DUMMY("ce_pclk", CE2_CLK, NULL, OFF),
441 CLK_DUMMY("ce_clk", CE1_CORE_CLK, NULL, OFF),
442 CLK_DUMMY("spi_pclk", GSBI1_P_CLK, NULL, OFF),
443 CLK_DUMMY("gsbi_pclk", GSBI2_P_CLK, NULL, OFF),
444 CLK_DUMMY("gsbi_pclk", GSBI3_P_CLK,
445 "msm_serial_hsl.0", OFF),
446 CLK_DUMMY("gsbi_pclk", GSBI4_P_CLK, NULL, OFF),
447 CLK_DUMMY("gsbi_pclk", GSBI5_P_CLK, NULL, OFF),
448 CLK_DUMMY("uartdm_pclk", GSBI6_P_CLK, NULL, OFF),
449 CLK_DUMMY("gsbi_pclk", GSBI7_P_CLK, NULL, OFF),
450 CLK_DUMMY("gsbi_pclk", GSBI8_P_CLK, NULL, OFF),
451 CLK_DUMMY("gsbi_pclk", GSBI9_P_CLK, NULL, OFF),
452 CLK_DUMMY("gsbi_pclk", GSBI10_P_CLK, NULL, OFF),
453 CLK_DUMMY("gsbi_pclk", GSBI11_P_CLK, NULL, OFF),
454 CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL, OFF),
455 CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL, OFF),
456 CLK_DUMMY("tsif_pclk", TSIF_P_CLK, NULL, OFF),
457 CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL, OFF),
458 CLK_DUMMY("usb_fs_pclk", USB_FS2_P_CLK, NULL, OFF),
459 CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL, OFF),
460 CLK_DUMMY("sdc_pclk", SDC1_P_CLK, NULL, OFF),
461 CLK_DUMMY("sdc_pclk", SDC2_P_CLK, NULL, OFF),
462 CLK_DUMMY("sdc_pclk", SDC3_P_CLK, NULL, OFF),
463 CLK_DUMMY("sdc_pclk", SDC4_P_CLK, NULL, OFF),
464 CLK_DUMMY("sdc_pclk", SDC5_P_CLK, NULL, OFF),
465 CLK_DUMMY("adm_clk", ADM0_CLK, NULL, OFF),
466 CLK_DUMMY("adm_pclk", ADM0_P_CLK, NULL, OFF),
467 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
468 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
469 CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
470 CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
471 CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
472 CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
473 CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
474 CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
475 CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF),
476 CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
477 CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF),
478 CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
479 CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
480 CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF),
481 CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF),
482 CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF),
483 CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, NULL, OFF),
484 CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, NULL, OFF),
485 CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, NULL, OFF),
486 CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, NULL, OFF),
487 CLK_DUMMY("gfx2d0_clk", GFX2D0_CLK, NULL, OFF),
488 CLK_DUMMY("gfx2d1_clk", GFX2D1_CLK, NULL, OFF),
489 CLK_DUMMY("gfx3d_clk", GFX3D_CLK, NULL, OFF),
490 CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
491 CLK_DUMMY("imem_clk", IMEM_CLK, NULL, OFF),
492 CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
493 CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
494 CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
495 CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
496 CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
497 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
498 CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
499 CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
500 CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
501 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
502 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
503 CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL, OFF),
504 CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF),
505 CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF),
506 CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF),
507 CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
508 CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
509 CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
510 CLK_DUMMY("rot_axi_clk", ROT_AXI_CLK, NULL, OFF),
511 CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
512 CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
513 CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
514 CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF),
515 CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF),
516 CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF),
517 CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, NULL, OFF),
518 CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, NULL, OFF),
519 CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, NULL, OFF),
520 CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, NULL, OFF),
521 CLK_DUMMY("gfx2d0_pclk", GFX2D0_P_CLK, NULL, OFF),
522 CLK_DUMMY("gfx2d1_pclk", GFX2D1_P_CLK, NULL, OFF),
523 CLK_DUMMY("gfx3d_pclk", GFX3D_P_CLK, NULL, OFF),
524 CLK_DUMMY("hdmi_m_pclk", HDMI_M_P_CLK, NULL, OFF),
525 CLK_DUMMY("hdmi_s_pclk", HDMI_S_P_CLK, NULL, OFF),
526 CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF),
527 CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
528 CLK_DUMMY("imem_pclk", IMEM_P_CLK, NULL, OFF),
529 CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
530 CLK_DUMMY("smmu_pclk", SMMU_P_CLK, NULL, OFF),
531 CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
532 CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL, OFF),
533 CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
534 CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
535 CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
536 CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
537 CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
538 CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
539 CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
540 CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
541 CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
542 CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
543 CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
544 CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
545 CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
546 CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
547 CLK_DUMMY("iommu_clk", JPEGD_AXI_CLK, NULL, 0),
548 CLK_DUMMY("iommu_clk", VFE_AXI_CLK, NULL, 0),
549 CLK_DUMMY("iommu_clk", VCODEC_AXI_CLK, NULL, 0),
550 CLK_DUMMY("iommu_clk", GFX3D_CLK, NULL, 0),
551 CLK_DUMMY("iommu_clk", GFX2D0_CLK, NULL, 0),
552 CLK_DUMMY("iommu_clk", GFX2D1_CLK, NULL, 0),
553
554 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
555 CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
556 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC1_CLK, NULL, 0),
557 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC2_CLK, NULL, 0),
558 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC3_CLK, NULL, 0),
559 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC4_CLK, NULL, 0),
560 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC5_CLK, NULL, 0),
561 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
562 CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0),
563};
564
565unsigned msm_num_clocks_8064_dummy = ARRAY_SIZE(msm_clocks_8064_dummy);