Richard Röjfors | e1d5b65 | 2010-02-11 10:42:00 +0100 | [diff] [blame] | 1 | /* |
| 2 | * i2c-xiic.c |
| 3 | * Copyright (c) 2002-2007 Xilinx Inc. |
| 4 | * Copyright (c) 2009-2010 Intel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | * |
| 19 | * |
| 20 | * This code was implemented by Mocean Laboratories AB when porting linux |
| 21 | * to the automotive development board Russellville. The copyright holder |
| 22 | * as seen in the header is Intel corporation. |
| 23 | * Mocean Laboratories forked off the GNU/Linux platform work into a |
| 24 | * separate company called Pelagicore AB, which commited the code to the |
| 25 | * kernel. |
| 26 | */ |
| 27 | |
| 28 | /* Supports: |
| 29 | * Xilinx IIC |
| 30 | */ |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <linux/init.h> |
| 34 | #include <linux/errno.h> |
Randy Dunlap | 02ca6c4 | 2010-02-04 12:11:09 -0800 | [diff] [blame] | 35 | #include <linux/delay.h> |
Richard Röjfors | e1d5b65 | 2010-02-11 10:42:00 +0100 | [diff] [blame] | 36 | #include <linux/platform_device.h> |
| 37 | #include <linux/i2c.h> |
| 38 | #include <linux/interrupt.h> |
| 39 | #include <linux/wait.h> |
| 40 | #include <linux/i2c-xiic.h> |
| 41 | #include <linux/io.h> |
| 42 | |
| 43 | #define DRIVER_NAME "xiic-i2c" |
| 44 | |
| 45 | enum xilinx_i2c_state { |
| 46 | STATE_DONE, |
| 47 | STATE_ERROR, |
| 48 | STATE_START |
| 49 | }; |
| 50 | |
| 51 | /** |
| 52 | * struct xiic_i2c - Internal representation of the XIIC I2C bus |
| 53 | * @base: Memory base of the HW registers |
| 54 | * @wait: Wait queue for callers |
| 55 | * @adap: Kernel adapter representation |
| 56 | * @tx_msg: Messages from above to be sent |
| 57 | * @lock: Mutual exclusion |
| 58 | * @tx_pos: Current pos in TX message |
| 59 | * @nmsgs: Number of messages in tx_msg |
| 60 | * @state: See STATE_ |
| 61 | * @rx_msg: Current RX message |
| 62 | * @rx_pos: Position within current RX message |
| 63 | */ |
| 64 | struct xiic_i2c { |
| 65 | void __iomem *base; |
| 66 | wait_queue_head_t wait; |
| 67 | struct i2c_adapter adap; |
| 68 | struct i2c_msg *tx_msg; |
| 69 | spinlock_t lock; |
| 70 | unsigned int tx_pos; |
| 71 | unsigned int nmsgs; |
| 72 | enum xilinx_i2c_state state; |
| 73 | struct i2c_msg *rx_msg; |
| 74 | int rx_pos; |
| 75 | }; |
| 76 | |
| 77 | |
| 78 | #define XIIC_MSB_OFFSET 0 |
| 79 | #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) |
| 80 | |
| 81 | /* |
| 82 | * Register offsets in bytes from RegisterBase. Three is added to the |
| 83 | * base offset to access LSB (IBM style) of the word |
| 84 | */ |
| 85 | #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ |
| 86 | #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ |
| 87 | #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ |
| 88 | #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ |
| 89 | #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ |
| 90 | #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ |
| 91 | #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ |
| 92 | #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ |
| 93 | #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ |
| 94 | #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ |
| 95 | |
| 96 | /* Control Register masks */ |
| 97 | #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ |
| 98 | #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ |
| 99 | #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ |
| 100 | #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ |
| 101 | #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ |
| 102 | #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ |
| 103 | #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ |
| 104 | |
| 105 | /* Status Register masks */ |
| 106 | #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ |
| 107 | #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ |
| 108 | #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ |
| 109 | #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ |
| 110 | #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ |
| 111 | #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ |
| 112 | #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ |
| 113 | #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ |
| 114 | |
| 115 | /* Interrupt Status Register masks Interrupt occurs when... */ |
| 116 | #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ |
| 117 | #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ |
| 118 | #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ |
| 119 | #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ |
| 120 | #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ |
| 121 | #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ |
| 122 | #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ |
| 123 | #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ |
| 124 | |
| 125 | /* The following constants specify the depth of the FIFOs */ |
| 126 | #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ |
| 127 | #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ |
| 128 | |
| 129 | /* The following constants specify groups of interrupts that are typically |
| 130 | * enabled or disables at the same time |
| 131 | */ |
| 132 | #define XIIC_TX_INTERRUPTS \ |
| 133 | (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) |
| 134 | |
| 135 | #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) |
| 136 | |
| 137 | /* The following constants are used with the following macros to specify the |
| 138 | * operation, a read or write operation. |
| 139 | */ |
| 140 | #define XIIC_READ_OPERATION 1 |
| 141 | #define XIIC_WRITE_OPERATION 0 |
| 142 | |
| 143 | /* |
| 144 | * Tx Fifo upper bit masks. |
| 145 | */ |
| 146 | #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ |
| 147 | #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ |
| 148 | |
| 149 | /* |
| 150 | * The following constants define the register offsets for the Interrupt |
| 151 | * registers. There are some holes in the memory map for reserved addresses |
| 152 | * to allow other registers to be added and still match the memory map of the |
| 153 | * interrupt controller registers |
| 154 | */ |
| 155 | #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ |
| 156 | #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ |
| 157 | #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ |
| 158 | #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ |
| 159 | |
| 160 | #define XIIC_RESET_MASK 0xAUL |
| 161 | |
| 162 | /* |
| 163 | * The following constant is used for the device global interrupt enable |
| 164 | * register, to enable all interrupts for the device, this is the only bit |
| 165 | * in the register |
| 166 | */ |
| 167 | #define XIIC_GINTR_ENABLE_MASK 0x80000000UL |
| 168 | |
| 169 | #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) |
| 170 | #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) |
| 171 | |
| 172 | static void xiic_start_xfer(struct xiic_i2c *i2c); |
| 173 | static void __xiic_start_xfer(struct xiic_i2c *i2c); |
| 174 | |
| 175 | static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) |
| 176 | { |
| 177 | iowrite8(value, i2c->base + reg); |
| 178 | } |
| 179 | |
| 180 | static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) |
| 181 | { |
| 182 | return ioread8(i2c->base + reg); |
| 183 | } |
| 184 | |
| 185 | static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) |
| 186 | { |
| 187 | iowrite16(value, i2c->base + reg); |
| 188 | } |
| 189 | |
| 190 | static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) |
| 191 | { |
| 192 | iowrite32(value, i2c->base + reg); |
| 193 | } |
| 194 | |
| 195 | static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) |
| 196 | { |
| 197 | return ioread32(i2c->base + reg); |
| 198 | } |
| 199 | |
| 200 | static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) |
| 201 | { |
| 202 | u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); |
| 203 | xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); |
| 204 | } |
| 205 | |
| 206 | static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) |
| 207 | { |
| 208 | u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); |
| 209 | xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); |
| 210 | } |
| 211 | |
| 212 | static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) |
| 213 | { |
| 214 | u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); |
| 215 | xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); |
| 216 | } |
| 217 | |
| 218 | static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) |
| 219 | { |
| 220 | xiic_irq_clr(i2c, mask); |
| 221 | xiic_irq_en(i2c, mask); |
| 222 | } |
| 223 | |
| 224 | static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) |
| 225 | { |
| 226 | u8 sr; |
| 227 | for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); |
| 228 | !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); |
| 229 | sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) |
| 230 | xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); |
| 231 | } |
| 232 | |
| 233 | static void xiic_reinit(struct xiic_i2c *i2c) |
| 234 | { |
| 235 | xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); |
| 236 | |
| 237 | /* Set receive Fifo depth to maximum (zero based). */ |
| 238 | xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); |
| 239 | |
| 240 | /* Reset Tx Fifo. */ |
| 241 | xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); |
| 242 | |
| 243 | /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ |
| 244 | xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); |
| 245 | |
| 246 | /* make sure RX fifo is empty */ |
| 247 | xiic_clear_rx_fifo(i2c); |
| 248 | |
| 249 | /* Enable interrupts */ |
| 250 | xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); |
| 251 | |
| 252 | xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK); |
| 253 | } |
| 254 | |
| 255 | static void xiic_deinit(struct xiic_i2c *i2c) |
| 256 | { |
| 257 | u8 cr; |
| 258 | |
| 259 | xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); |
| 260 | |
| 261 | /* Disable IIC Device. */ |
| 262 | cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); |
| 263 | xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); |
| 264 | } |
| 265 | |
| 266 | static void xiic_read_rx(struct xiic_i2c *i2c) |
| 267 | { |
| 268 | u8 bytes_in_fifo; |
| 269 | int i; |
| 270 | |
| 271 | bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; |
| 272 | |
| 273 | dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d" |
| 274 | ", SR: 0x%x, CR: 0x%x\n", |
| 275 | __func__, bytes_in_fifo, xiic_rx_space(i2c), |
| 276 | xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), |
| 277 | xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); |
| 278 | |
| 279 | if (bytes_in_fifo > xiic_rx_space(i2c)) |
| 280 | bytes_in_fifo = xiic_rx_space(i2c); |
| 281 | |
| 282 | for (i = 0; i < bytes_in_fifo; i++) |
| 283 | i2c->rx_msg->buf[i2c->rx_pos++] = |
| 284 | xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); |
| 285 | |
| 286 | xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, |
| 287 | (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? |
| 288 | IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); |
| 289 | } |
| 290 | |
| 291 | static int xiic_tx_fifo_space(struct xiic_i2c *i2c) |
| 292 | { |
| 293 | /* return the actual space left in the FIFO */ |
| 294 | return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; |
| 295 | } |
| 296 | |
| 297 | static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) |
| 298 | { |
| 299 | u8 fifo_space = xiic_tx_fifo_space(i2c); |
| 300 | int len = xiic_tx_space(i2c); |
| 301 | |
| 302 | len = (len > fifo_space) ? fifo_space : len; |
| 303 | |
| 304 | dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", |
| 305 | __func__, len, fifo_space); |
| 306 | |
| 307 | while (len--) { |
| 308 | u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; |
| 309 | if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { |
| 310 | /* last message in transfer -> STOP */ |
| 311 | data |= XIIC_TX_DYN_STOP_MASK; |
| 312 | dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); |
| 313 | |
| 314 | xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); |
| 315 | } else |
| 316 | xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data); |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | static void xiic_wakeup(struct xiic_i2c *i2c, int code) |
| 321 | { |
| 322 | i2c->tx_msg = NULL; |
| 323 | i2c->rx_msg = NULL; |
| 324 | i2c->nmsgs = 0; |
| 325 | i2c->state = code; |
| 326 | wake_up(&i2c->wait); |
| 327 | } |
| 328 | |
| 329 | static void xiic_process(struct xiic_i2c *i2c) |
| 330 | { |
| 331 | u32 pend, isr, ier; |
| 332 | u32 clr = 0; |
| 333 | |
| 334 | /* Get the interrupt Status from the IPIF. There is no clearing of |
| 335 | * interrupts in the IPIF. Interrupts must be cleared at the source. |
| 336 | * To find which interrupts are pending; AND interrupts pending with |
| 337 | * interrupts masked. |
| 338 | */ |
| 339 | isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); |
| 340 | ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); |
| 341 | pend = isr & ier; |
| 342 | |
| 343 | dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, " |
| 344 | "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n", |
| 345 | __func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), |
| 346 | i2c->tx_msg, i2c->nmsgs); |
| 347 | |
| 348 | /* Do not processes a devices interrupts if the device has no |
| 349 | * interrupts pending |
| 350 | */ |
| 351 | if (!pend) |
| 352 | return; |
| 353 | |
| 354 | /* Service requesting interrupt */ |
| 355 | if ((pend & XIIC_INTR_ARB_LOST_MASK) || |
| 356 | ((pend & XIIC_INTR_TX_ERROR_MASK) && |
| 357 | !(pend & XIIC_INTR_RX_FULL_MASK))) { |
| 358 | /* bus arbritration lost, or... |
| 359 | * Transmit error _OR_ RX completed |
| 360 | * if this happens when RX_FULL is not set |
| 361 | * this is probably a TX error |
| 362 | */ |
| 363 | |
| 364 | dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); |
| 365 | |
| 366 | /* dynamic mode seem to suffer from problems if we just flushes |
| 367 | * fifos and the next message is a TX with len 0 (only addr) |
| 368 | * reset the IP instead of just flush fifos |
| 369 | */ |
| 370 | xiic_reinit(i2c); |
| 371 | |
| 372 | if (i2c->tx_msg) |
| 373 | xiic_wakeup(i2c, STATE_ERROR); |
| 374 | |
| 375 | } else if (pend & XIIC_INTR_RX_FULL_MASK) { |
| 376 | /* Receive register/FIFO is full */ |
| 377 | |
| 378 | clr = XIIC_INTR_RX_FULL_MASK; |
| 379 | if (!i2c->rx_msg) { |
| 380 | dev_dbg(i2c->adap.dev.parent, |
| 381 | "%s unexpexted RX IRQ\n", __func__); |
| 382 | xiic_clear_rx_fifo(i2c); |
| 383 | goto out; |
| 384 | } |
| 385 | |
| 386 | xiic_read_rx(i2c); |
| 387 | if (xiic_rx_space(i2c) == 0) { |
| 388 | /* this is the last part of the message */ |
| 389 | i2c->rx_msg = NULL; |
| 390 | |
| 391 | /* also clear TX error if there (RX complete) */ |
| 392 | clr |= (isr & XIIC_INTR_TX_ERROR_MASK); |
| 393 | |
| 394 | dev_dbg(i2c->adap.dev.parent, |
| 395 | "%s end of message, nmsgs: %d\n", |
| 396 | __func__, i2c->nmsgs); |
| 397 | |
| 398 | /* send next message if this wasn't the last, |
| 399 | * otherwise the transfer will be finialise when |
| 400 | * receiving the bus not busy interrupt |
| 401 | */ |
| 402 | if (i2c->nmsgs > 1) { |
| 403 | i2c->nmsgs--; |
| 404 | i2c->tx_msg++; |
| 405 | dev_dbg(i2c->adap.dev.parent, |
| 406 | "%s will start next...\n", __func__); |
| 407 | |
| 408 | __xiic_start_xfer(i2c); |
| 409 | } |
| 410 | } |
| 411 | } else if (pend & XIIC_INTR_BNB_MASK) { |
| 412 | /* IIC bus has transitioned to not busy */ |
| 413 | clr = XIIC_INTR_BNB_MASK; |
| 414 | |
| 415 | /* The bus is not busy, disable BusNotBusy interrupt */ |
| 416 | xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); |
| 417 | |
| 418 | if (!i2c->tx_msg) |
| 419 | goto out; |
| 420 | |
| 421 | if ((i2c->nmsgs == 1) && !i2c->rx_msg && |
| 422 | xiic_tx_space(i2c) == 0) |
| 423 | xiic_wakeup(i2c, STATE_DONE); |
| 424 | else |
| 425 | xiic_wakeup(i2c, STATE_ERROR); |
| 426 | |
| 427 | } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { |
| 428 | /* Transmit register/FIFO is empty or ½ empty */ |
| 429 | |
| 430 | clr = pend & |
| 431 | (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK); |
| 432 | |
| 433 | if (!i2c->tx_msg) { |
| 434 | dev_dbg(i2c->adap.dev.parent, |
| 435 | "%s unexpexted TX IRQ\n", __func__); |
| 436 | goto out; |
| 437 | } |
| 438 | |
| 439 | xiic_fill_tx_fifo(i2c); |
| 440 | |
| 441 | /* current message sent and there is space in the fifo */ |
| 442 | if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { |
| 443 | dev_dbg(i2c->adap.dev.parent, |
| 444 | "%s end of message sent, nmsgs: %d\n", |
| 445 | __func__, i2c->nmsgs); |
| 446 | if (i2c->nmsgs > 1) { |
| 447 | i2c->nmsgs--; |
| 448 | i2c->tx_msg++; |
| 449 | __xiic_start_xfer(i2c); |
| 450 | } else { |
| 451 | xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); |
| 452 | |
| 453 | dev_dbg(i2c->adap.dev.parent, |
| 454 | "%s Got TX IRQ but no more to do...\n", |
| 455 | __func__); |
| 456 | } |
| 457 | } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) |
| 458 | /* current frame is sent and is last, |
| 459 | * make sure to disable tx half |
| 460 | */ |
| 461 | xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); |
| 462 | } else { |
| 463 | /* got IRQ which is not acked */ |
| 464 | dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n", |
| 465 | __func__); |
| 466 | clr = pend; |
| 467 | } |
| 468 | out: |
| 469 | dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); |
| 470 | |
| 471 | xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); |
| 472 | } |
| 473 | |
| 474 | static int xiic_bus_busy(struct xiic_i2c *i2c) |
| 475 | { |
| 476 | u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); |
| 477 | |
| 478 | return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; |
| 479 | } |
| 480 | |
| 481 | static int xiic_busy(struct xiic_i2c *i2c) |
| 482 | { |
| 483 | int tries = 3; |
| 484 | int err; |
| 485 | |
| 486 | if (i2c->tx_msg) |
| 487 | return -EBUSY; |
| 488 | |
| 489 | /* for instance if previous transfer was terminated due to TX error |
| 490 | * it might be that the bus is on it's way to become available |
| 491 | * give it at most 3 ms to wake |
| 492 | */ |
| 493 | err = xiic_bus_busy(i2c); |
| 494 | while (err && tries--) { |
| 495 | mdelay(1); |
| 496 | err = xiic_bus_busy(i2c); |
| 497 | } |
| 498 | |
| 499 | return err; |
| 500 | } |
| 501 | |
| 502 | static void xiic_start_recv(struct xiic_i2c *i2c) |
| 503 | { |
| 504 | u8 rx_watermark; |
| 505 | struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; |
| 506 | |
| 507 | /* Clear and enable Rx full interrupt. */ |
| 508 | xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); |
| 509 | |
| 510 | /* we want to get all but last byte, because the TX_ERROR IRQ is used |
| 511 | * to inidicate error ACK on the address, and negative ack on the last |
| 512 | * received byte, so to not mix them receive all but last. |
| 513 | * In the case where there is only one byte to receive |
| 514 | * we can check if ERROR and RX full is set at the same time |
| 515 | */ |
| 516 | rx_watermark = msg->len; |
| 517 | if (rx_watermark > IIC_RX_FIFO_DEPTH) |
| 518 | rx_watermark = IIC_RX_FIFO_DEPTH; |
| 519 | xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); |
| 520 | |
| 521 | if (!(msg->flags & I2C_M_NOSTART)) |
| 522 | /* write the address */ |
| 523 | xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, |
| 524 | (msg->addr << 1) | XIIC_READ_OPERATION | |
| 525 | XIIC_TX_DYN_START_MASK); |
| 526 | |
| 527 | xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); |
| 528 | |
| 529 | xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, |
| 530 | msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); |
| 531 | if (i2c->nmsgs == 1) |
| 532 | /* very last, enable bus not busy as well */ |
| 533 | xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); |
| 534 | |
| 535 | /* the message is tx:ed */ |
| 536 | i2c->tx_pos = msg->len; |
| 537 | } |
| 538 | |
| 539 | static void xiic_start_send(struct xiic_i2c *i2c) |
| 540 | { |
| 541 | struct i2c_msg *msg = i2c->tx_msg; |
| 542 | |
| 543 | xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); |
| 544 | |
| 545 | dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d, " |
| 546 | "ISR: 0x%x, CR: 0x%x\n", |
| 547 | __func__, msg, msg->len, xiic_getreg32(i2c, XIIC_IISR_OFFSET), |
| 548 | xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); |
| 549 | |
| 550 | if (!(msg->flags & I2C_M_NOSTART)) { |
| 551 | /* write the address */ |
| 552 | u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION | |
| 553 | XIIC_TX_DYN_START_MASK; |
| 554 | if ((i2c->nmsgs == 1) && msg->len == 0) |
| 555 | /* no data and last message -> add STOP */ |
| 556 | data |= XIIC_TX_DYN_STOP_MASK; |
| 557 | |
| 558 | xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); |
| 559 | } |
| 560 | |
| 561 | xiic_fill_tx_fifo(i2c); |
| 562 | |
| 563 | /* Clear any pending Tx empty, Tx Error and then enable them. */ |
| 564 | xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | |
| 565 | XIIC_INTR_BNB_MASK); |
| 566 | } |
| 567 | |
| 568 | static irqreturn_t xiic_isr(int irq, void *dev_id) |
| 569 | { |
| 570 | struct xiic_i2c *i2c = dev_id; |
| 571 | |
| 572 | spin_lock(&i2c->lock); |
| 573 | /* disable interrupts globally */ |
| 574 | xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); |
| 575 | |
| 576 | dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); |
| 577 | |
| 578 | xiic_process(i2c); |
| 579 | |
| 580 | xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); |
| 581 | spin_unlock(&i2c->lock); |
| 582 | |
| 583 | return IRQ_HANDLED; |
| 584 | } |
| 585 | |
| 586 | static void __xiic_start_xfer(struct xiic_i2c *i2c) |
| 587 | { |
| 588 | int first = 1; |
| 589 | int fifo_space = xiic_tx_fifo_space(i2c); |
| 590 | dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", |
| 591 | __func__, i2c->tx_msg, fifo_space); |
| 592 | |
| 593 | if (!i2c->tx_msg) |
| 594 | return; |
| 595 | |
| 596 | i2c->rx_pos = 0; |
| 597 | i2c->tx_pos = 0; |
| 598 | i2c->state = STATE_START; |
| 599 | while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { |
| 600 | if (!first) { |
| 601 | i2c->nmsgs--; |
| 602 | i2c->tx_msg++; |
| 603 | i2c->tx_pos = 0; |
| 604 | } else |
| 605 | first = 0; |
| 606 | |
| 607 | if (i2c->tx_msg->flags & I2C_M_RD) { |
| 608 | /* we dont date putting several reads in the FIFO */ |
| 609 | xiic_start_recv(i2c); |
| 610 | return; |
| 611 | } else { |
| 612 | xiic_start_send(i2c); |
| 613 | if (xiic_tx_space(i2c) != 0) { |
| 614 | /* the message could not be completely sent */ |
| 615 | break; |
| 616 | } |
| 617 | } |
| 618 | |
| 619 | fifo_space = xiic_tx_fifo_space(i2c); |
| 620 | } |
| 621 | |
| 622 | /* there are more messages or the current one could not be completely |
| 623 | * put into the FIFO, also enable the half empty interrupt |
| 624 | */ |
| 625 | if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) |
| 626 | xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); |
| 627 | |
| 628 | } |
| 629 | |
| 630 | static void xiic_start_xfer(struct xiic_i2c *i2c) |
| 631 | { |
| 632 | unsigned long flags; |
| 633 | |
| 634 | spin_lock_irqsave(&i2c->lock, flags); |
| 635 | xiic_reinit(i2c); |
| 636 | /* disable interrupts globally */ |
| 637 | xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); |
| 638 | spin_unlock_irqrestore(&i2c->lock, flags); |
| 639 | |
| 640 | __xiic_start_xfer(i2c); |
| 641 | xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); |
| 642 | } |
| 643 | |
| 644 | static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) |
| 645 | { |
| 646 | struct xiic_i2c *i2c = i2c_get_adapdata(adap); |
| 647 | int err; |
| 648 | |
| 649 | dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, |
| 650 | xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); |
| 651 | |
| 652 | err = xiic_busy(i2c); |
| 653 | if (err) |
| 654 | return err; |
| 655 | |
| 656 | i2c->tx_msg = msgs; |
| 657 | i2c->nmsgs = num; |
| 658 | |
| 659 | xiic_start_xfer(i2c); |
| 660 | |
| 661 | if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || |
| 662 | (i2c->state == STATE_DONE), HZ)) |
| 663 | return (i2c->state == STATE_DONE) ? num : -EIO; |
| 664 | else { |
| 665 | i2c->tx_msg = NULL; |
| 666 | i2c->rx_msg = NULL; |
| 667 | i2c->nmsgs = 0; |
| 668 | return -ETIMEDOUT; |
| 669 | } |
| 670 | } |
| 671 | |
| 672 | static u32 xiic_func(struct i2c_adapter *adap) |
| 673 | { |
| 674 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
| 675 | } |
| 676 | |
| 677 | static const struct i2c_algorithm xiic_algorithm = { |
| 678 | .master_xfer = xiic_xfer, |
| 679 | .functionality = xiic_func, |
| 680 | }; |
| 681 | |
| 682 | static struct i2c_adapter xiic_adapter = { |
| 683 | .owner = THIS_MODULE, |
| 684 | .name = DRIVER_NAME, |
| 685 | .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, |
| 686 | .algo = &xiic_algorithm, |
| 687 | }; |
| 688 | |
| 689 | |
| 690 | static int __devinit xiic_i2c_probe(struct platform_device *pdev) |
| 691 | { |
| 692 | struct xiic_i2c *i2c; |
| 693 | struct xiic_i2c_platform_data *pdata; |
| 694 | struct resource *res; |
| 695 | int ret, irq; |
| 696 | u8 i; |
| 697 | |
| 698 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 699 | if (!res) |
| 700 | goto resource_missing; |
| 701 | |
| 702 | irq = platform_get_irq(pdev, 0); |
| 703 | if (irq < 0) |
| 704 | goto resource_missing; |
| 705 | |
| 706 | pdata = (struct xiic_i2c_platform_data *) pdev->dev.platform_data; |
| 707 | if (!pdata) |
| 708 | return -EINVAL; |
| 709 | |
| 710 | i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); |
| 711 | if (!i2c) |
| 712 | return -ENOMEM; |
| 713 | |
| 714 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { |
| 715 | dev_err(&pdev->dev, "Memory region busy\n"); |
| 716 | ret = -EBUSY; |
| 717 | goto request_mem_failed; |
| 718 | } |
| 719 | |
| 720 | i2c->base = ioremap(res->start, resource_size(res)); |
| 721 | if (!i2c->base) { |
| 722 | dev_err(&pdev->dev, "Unable to map registers\n"); |
| 723 | ret = -EIO; |
| 724 | goto map_failed; |
| 725 | } |
| 726 | |
| 727 | /* hook up driver to tree */ |
| 728 | platform_set_drvdata(pdev, i2c); |
| 729 | i2c->adap = xiic_adapter; |
| 730 | i2c_set_adapdata(&i2c->adap, i2c); |
| 731 | i2c->adap.dev.parent = &pdev->dev; |
| 732 | |
| 733 | xiic_reinit(i2c); |
| 734 | |
| 735 | spin_lock_init(&i2c->lock); |
| 736 | init_waitqueue_head(&i2c->wait); |
| 737 | ret = request_irq(irq, xiic_isr, 0, pdev->name, i2c); |
| 738 | if (ret) { |
| 739 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); |
| 740 | goto request_irq_failed; |
| 741 | } |
| 742 | |
| 743 | /* add i2c adapter to i2c tree */ |
| 744 | ret = i2c_add_adapter(&i2c->adap); |
| 745 | if (ret) { |
| 746 | dev_err(&pdev->dev, "Failed to add adapter\n"); |
| 747 | goto add_adapter_failed; |
| 748 | } |
| 749 | |
| 750 | /* add in known devices to the bus */ |
| 751 | for (i = 0; i < pdata->num_devices; i++) |
| 752 | i2c_new_device(&i2c->adap, pdata->devices + i); |
| 753 | |
| 754 | return 0; |
| 755 | |
| 756 | add_adapter_failed: |
| 757 | free_irq(irq, i2c); |
| 758 | request_irq_failed: |
| 759 | xiic_deinit(i2c); |
| 760 | iounmap(i2c->base); |
| 761 | map_failed: |
| 762 | release_mem_region(res->start, resource_size(res)); |
| 763 | request_mem_failed: |
| 764 | kfree(i2c); |
| 765 | |
| 766 | return ret; |
| 767 | resource_missing: |
| 768 | dev_err(&pdev->dev, "IRQ or Memory resource is missing\n"); |
| 769 | return -ENOENT; |
| 770 | } |
| 771 | |
| 772 | static int __devexit xiic_i2c_remove(struct platform_device* pdev) |
| 773 | { |
| 774 | struct xiic_i2c *i2c = platform_get_drvdata(pdev); |
| 775 | struct resource *res; |
| 776 | |
| 777 | /* remove adapter & data */ |
| 778 | i2c_del_adapter(&i2c->adap); |
| 779 | |
| 780 | xiic_deinit(i2c); |
| 781 | |
| 782 | platform_set_drvdata(pdev, NULL); |
| 783 | |
| 784 | free_irq(platform_get_irq(pdev, 0), i2c); |
| 785 | |
| 786 | iounmap(i2c->base); |
| 787 | |
| 788 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 789 | if (res) |
| 790 | release_mem_region(res->start, resource_size(res)); |
| 791 | |
| 792 | kfree(i2c); |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | |
| 798 | /* work with hotplug and coldplug */ |
| 799 | MODULE_ALIAS("platform:"DRIVER_NAME); |
| 800 | |
| 801 | static struct platform_driver xiic_i2c_driver = { |
| 802 | .probe = xiic_i2c_probe, |
| 803 | .remove = __devexit_p(xiic_i2c_remove), |
| 804 | .driver = { |
| 805 | .owner = THIS_MODULE, |
| 806 | .name = DRIVER_NAME, |
| 807 | }, |
| 808 | }; |
| 809 | |
| 810 | static int __init xiic_i2c_init(void) |
| 811 | { |
| 812 | return platform_driver_register(&xiic_i2c_driver); |
| 813 | } |
| 814 | |
| 815 | static void __exit xiic_i2c_exit(void) |
| 816 | { |
| 817 | platform_driver_unregister(&xiic_i2c_driver); |
| 818 | } |
| 819 | |
| 820 | module_init(xiic_i2c_init); |
| 821 | module_exit(xiic_i2c_exit); |
| 822 | |
| 823 | MODULE_AUTHOR("info@mocean-labs.com"); |
| 824 | MODULE_DESCRIPTION("Xilinx I2C bus driver"); |
| 825 | MODULE_LICENSE("GPL v2"); |