Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface |
| 3 | * |
| 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or (at |
| 9 | * your option) any later version. |
| 10 | */ |
Robert P. J. Day | 100e918 | 2011-05-27 16:04:03 -0400 | [diff] [blame] | 11 | #ifndef LINUX_MMC_SDHCI_H |
| 12 | #define LINUX_MMC_SDHCI_H |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 13 | |
| 14 | #include <linux/scatterlist.h> |
| 15 | #include <linux/compiler.h> |
| 16 | #include <linux/types.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/mmc/host.h> |
Sahitya Tummala | b4e8404 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 19 | #include <linux/pm_qos.h> |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 20 | |
Shawn Guo | 6f9ad6f | 2011-04-17 00:48:36 +0800 | [diff] [blame] | 21 | struct sdhci_next { |
| 22 | unsigned int sg_count; |
| 23 | s32 cookie; |
| 24 | }; |
| 25 | |
Sujit Reddy Thumma | deb1ada | 2013-06-19 20:15:37 +0530 | [diff] [blame] | 26 | enum sdhci_power_policy { |
| 27 | SDHCI_PERFORMANCE_MODE, |
| 28 | SDHCI_POWER_SAVE_MODE, |
| 29 | }; |
| 30 | |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 31 | struct sdhci_host { |
| 32 | /* Data set by hardware interface driver */ |
| 33 | const char *hw_name; /* Hardware bus name */ |
| 34 | |
| 35 | unsigned int quirks; /* Deviations from spec. */ |
| 36 | |
| 37 | /* Controller doesn't honor resets unless we touch the clock register */ |
| 38 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) |
| 39 | /* Controller has bad caps bits, but really supports DMA */ |
| 40 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) |
| 41 | /* Controller doesn't like to be reset when there is no card inserted. */ |
| 42 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) |
| 43 | /* Controller doesn't like clearing the power reg before a change */ |
| 44 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) |
| 45 | /* Controller has flaky internal state so reset it on each ios change */ |
| 46 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) |
| 47 | /* Controller has an unusable DMA engine */ |
| 48 | #define SDHCI_QUIRK_BROKEN_DMA (1<<5) |
| 49 | /* Controller has an unusable ADMA engine */ |
| 50 | #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) |
| 51 | /* Controller can only DMA from 32-bit aligned addresses */ |
| 52 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) |
| 53 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ |
| 54 | #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) |
| 55 | /* Controller can only ADMA chunks that are a multiple of 32 bits */ |
| 56 | #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) |
| 57 | /* Controller needs to be reset after each request to stay stable */ |
| 58 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) |
| 59 | /* Controller needs voltage and power writes to happen separately */ |
| 60 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) |
| 61 | /* Controller provides an incorrect timeout value for transfers */ |
| 62 | #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) |
| 63 | /* Controller has an issue with buffer bits for small transfers */ |
| 64 | #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) |
| 65 | /* Controller does not provide transfer-complete interrupt when not busy */ |
| 66 | #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) |
| 67 | /* Controller has unreliable card detection */ |
| 68 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) |
| 69 | /* Controller reports inverted write-protect state */ |
| 70 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) |
| 71 | /* Controller has nonstandard clock management */ |
| 72 | #define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17) |
| 73 | /* Controller does not like fast PIO transfers */ |
| 74 | #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) |
| 75 | /* Controller losing signal/interrupt enable states after reset */ |
| 76 | #define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19) |
| 77 | /* Controller has to be forced to use block size of 2048 bytes */ |
| 78 | #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) |
| 79 | /* Controller cannot do multi-block transfers */ |
| 80 | #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) |
| 81 | /* Controller can only handle 1-bit data transfers */ |
| 82 | #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) |
| 83 | /* Controller needs 10ms delay between applying power and clock */ |
| 84 | #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) |
| 85 | /* Controller uses SDCLK instead of TMCLK for data timeouts */ |
| 86 | #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) |
| 87 | /* Controller reports wrong base clock capability */ |
| 88 | #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) |
| 89 | /* Controller cannot support End Attribute in NOP ADMA descriptor */ |
| 90 | #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) |
| 91 | /* Controller is missing device caps. Use caps provided by host */ |
| 92 | #define SDHCI_QUIRK_MISSING_CAPS (1<<27) |
| 93 | /* Controller uses Auto CMD12 command to stop the transfer */ |
| 94 | #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) |
| 95 | /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ |
| 96 | #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 97 | /* Controller treats ADMA descriptors with length 0000h incorrectly */ |
| 98 | #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 99 | /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ |
| 100 | #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 101 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 102 | unsigned int quirks2; /* More deviations from spec. */ |
| 103 | |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 104 | #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) |
Venkat Gopalakrishnan | e9beaa2 | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 105 | /* |
| 106 | * Read Transfer Active/ Write Transfer Active may be not |
| 107 | * de-asserted after end of transaction. Issue reset for DAT line. |
| 108 | */ |
| 109 | #define SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT (1<<1) |
| 110 | /* |
| 111 | * Slow interrupt clearance at 400KHz may cause |
| 112 | * host controller driver interrupt handler to |
| 113 | * be called twice. |
| 114 | */ |
| 115 | #define SDHCI_QUIRK2_SLOW_INT_CLR (1<<2) |
Sahitya Tummala | d6a74b0 | 2013-02-25 15:50:08 +0530 | [diff] [blame] | 116 | /* Ignore CMD CRC errors for tuning commands */ |
| 117 | #define SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING (1<<3) |
Sahitya Tummala | 0024012 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 118 | /* |
| 119 | * If the base clock can be scalable, then there should be no further |
| 120 | * clock dividing as the input clock itself will be scaled down to |
| 121 | * required frequency. |
| 122 | */ |
| 123 | #define SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK (1<<4) |
Krishna Konda | a20d336 | 2013-04-01 21:01:59 -0700 | [diff] [blame] | 124 | /* |
| 125 | * Dont use the max_discard_to in sdhci driver so that the maximum discard |
| 126 | * unit gets picked by the mmc queue. Otherwise, it takes a long time for |
| 127 | * secure discard kind of operations to complete. |
| 128 | */ |
| 129 | #define SDHCI_QUIRK2_USE_MAX_DISCARD_SIZE (1<<5) |
Sahitya Tummala | d2ae883 | 2013-04-12 11:49:11 +0530 | [diff] [blame] | 130 | /* |
| 131 | * Ignore data timeout error for R1B commands as there will be no |
| 132 | * data associated and the busy timeout value for these commands |
| 133 | * could be lager than the maximum timeout value that controller |
| 134 | * can handle. |
| 135 | */ |
| 136 | #define SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD (1<<6) |
Sahitya Tummala | e6886bd | 2013-04-12 12:11:20 +0530 | [diff] [blame] | 137 | /* |
| 138 | * The preset value registers are not properly initialized by |
| 139 | * some hardware and hence preset value must not be enabled for |
| 140 | * such controllers. |
| 141 | */ |
| 142 | #define SDHCI_QUIRK2_BROKEN_PRESET_VALUE (1<<7) |
Sahitya Tummala | 4d12d0b | 2013-04-12 11:59:25 +0530 | [diff] [blame] | 143 | /* |
| 144 | * Some controllers define the usage of 0xF in data timeout counter |
| 145 | * register (0x2E) which is actually a reserved bit as per |
| 146 | * specification. |
| 147 | */ |
| 148 | #define SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT (1<<8) |
Sahitya Tummala | f667cc1 | 2013-06-10 16:32:51 +0530 | [diff] [blame] | 149 | /* |
| 150 | * This is applicable for controllers that advertize timeout clock |
| 151 | * value in capabilities register (bit 5-0) as just 50MHz whereas the |
| 152 | * base clock frequency is 200MHz. So, the controller internally |
| 153 | * multiplies the value in timeout control register by 4 with the |
| 154 | * assumption that driver always uses fixed timeout clock value from |
| 155 | * capabilities register to calculate the timeout. But when the driver |
| 156 | * uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK base clock frequency is directly |
| 157 | * controller by driver and it's rate varies upto max. 200MHz. This new quirk |
| 158 | * will be used in such cases to avoid controller mulplication when timeout is |
| 159 | * calculated based on the base clock. |
| 160 | */ |
| 161 | #define SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 (1 << 9) |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 162 | |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 163 | int irq; /* Device IRQ */ |
| 164 | void __iomem *ioaddr; /* Mapped address */ |
| 165 | |
| 166 | const struct sdhci_ops *ops; /* Low level hw interface */ |
| 167 | |
| 168 | struct regulator *vmmc; /* Power regulator */ |
| 169 | |
| 170 | /* Internal data */ |
| 171 | struct mmc_host *mmc; /* MMC structure */ |
| 172 | u64 dma_mask; /* custom DMA mask */ |
| 173 | |
| 174 | #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) |
| 175 | struct led_classdev led; /* LED control */ |
| 176 | char led_name[32]; |
| 177 | #endif |
| 178 | |
| 179 | spinlock_t lock; /* Mutex */ |
| 180 | |
| 181 | int flags; /* Host attributes */ |
| 182 | #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ |
| 183 | #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ |
| 184 | #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ |
| 185 | #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 186 | #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 187 | #define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */ |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 188 | #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 189 | #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 190 | #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ |
| 191 | #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ |
Girish K S | 2cd06dc | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 192 | #define SDHCI_HS200_NEEDS_TUNING (1<<10) /* HS200 needs tuning */ |
Venkat Gopalakrishnan | ceca475 | 2013-06-11 21:29:40 -0700 | [diff] [blame] | 193 | #define SDHCI_HS400_NEEDS_TUNING (1<<11) /* HS400 needs tuning */ |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 194 | |
| 195 | unsigned int version; /* SDHCI spec. version */ |
| 196 | |
| 197 | unsigned int max_clk; /* Max possible freq (MHz) */ |
| 198 | unsigned int timeout_clk; /* Timeout freq (KHz) */ |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 199 | unsigned int clk_mul; /* Clock Muliplier value */ |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 200 | |
| 201 | unsigned int clock; /* Current clock (MHz) */ |
| 202 | u8 pwr; /* Current voltage */ |
| 203 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 204 | bool runtime_suspended; /* Host is runtime suspended */ |
| 205 | |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 206 | struct mmc_request *mrq; /* Current request */ |
| 207 | struct mmc_command *cmd; /* Current command */ |
| 208 | struct mmc_data *data; /* Current data request */ |
| 209 | unsigned int data_early:1; /* Data finished before cmd */ |
| 210 | |
| 211 | struct sg_mapping_iter sg_miter; /* SG state for PIO */ |
| 212 | unsigned int blocks; /* remaining PIO blocks */ |
| 213 | |
| 214 | int sg_count; /* Mapped sg entries */ |
| 215 | |
| 216 | u8 *adma_desc; /* ADMA descriptor table */ |
| 217 | u8 *align_buffer; /* Bounce buffer */ |
| 218 | |
Asutosh Das | c8e8e56 | 2013-01-10 21:05:49 +0530 | [diff] [blame] | 219 | unsigned int adma_desc_sz; /* ADMA descriptor table size */ |
| 220 | unsigned int align_buf_sz; /* Bounce buffer size */ |
| 221 | unsigned int adma_max_desc; /* Max ADMA descriptos (max sg segments) */ |
| 222 | |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 223 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ |
| 224 | dma_addr_t align_addr; /* Mapped bounce buffer */ |
| 225 | |
| 226 | struct tasklet_struct card_tasklet; /* Tasklet structures */ |
| 227 | struct tasklet_struct finish_tasklet; |
| 228 | |
| 229 | struct timer_list timer; /* Timer for timeouts */ |
| 230 | |
| 231 | unsigned int caps; /* Alternative capabilities */ |
| 232 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 233 | unsigned int ocr_avail_sdio; /* OCR bit masks */ |
| 234 | unsigned int ocr_avail_sd; |
| 235 | unsigned int ocr_avail_mmc; |
| 236 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 237 | wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ |
| 238 | unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ |
| 239 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 240 | unsigned int tuning_count; /* Timer count for re-tuning */ |
| 241 | unsigned int tuning_mode; /* Re-tuning mode supported by host */ |
| 242 | #define SDHCI_TUNING_MODE_1 0 |
| 243 | struct timer_list tuning_timer; /* Timer for tuning */ |
| 244 | |
Sahitya Tummala | b4e8404 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 245 | unsigned int cpu_dma_latency_us; |
| 246 | struct pm_qos_request pm_qos_req_dma; |
Sujit Reddy Thumma | deb1ada | 2013-06-19 20:15:37 +0530 | [diff] [blame] | 247 | unsigned int pm_qos_timeout_us; /* timeout for PM QoS request */ |
Sujit Reddy Thumma | 693af8d | 2013-06-19 20:25:38 +0530 | [diff] [blame] | 248 | struct device_attribute pm_qos_tout; |
Sahitya Tummala | b4e8404 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 249 | |
Shawn Guo | 6f9ad6f | 2011-04-17 00:48:36 +0800 | [diff] [blame] | 250 | struct sdhci_next next_data; |
Sahitya Tummala | 48b458e | 2013-04-08 12:53:44 +0530 | [diff] [blame] | 251 | ktime_t data_start_time; |
Sahitya Tummala | 40474e4 | 2013-07-10 14:40:37 +0530 | [diff] [blame] | 252 | struct mutex ios_mutex; |
Sujit Reddy Thumma | deb1ada | 2013-06-19 20:15:37 +0530 | [diff] [blame] | 253 | enum sdhci_power_policy power_policy; |
Shawn Guo | 6f9ad6f | 2011-04-17 00:48:36 +0800 | [diff] [blame] | 254 | |
Sahitya Tummala | 8f6c000 | 2013-08-07 18:40:29 +0530 | [diff] [blame] | 255 | u32 auto_cmd_err_sts; |
Giuseppe Cavallaro | 1978fda | 2010-09-28 10:41:29 +0200 | [diff] [blame] | 256 | unsigned long private[0] ____cacheline_aligned; |
| 257 | }; |
Robert P. J. Day | 100e918 | 2011-05-27 16:04:03 -0400 | [diff] [blame] | 258 | #endif /* LINUX_MMC_SDHCI_H */ |