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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 4b30b87042aa71ed8682e4df622a10456796fccd / . / drivers / gpu / drm / radeon / radeon_clocks.c
blob: 2c541e08f16067eb28d4067c013a089f0373285d [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon_drm.h"
30#include "radeon_reg.h"
31#include "radeon.h"
32#include "atom.h"
33
34/* 10 khz */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]35uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]36{
37 struct radeon_pll *spll = &rdev->clock.spll;
38 uint32_t fb_div, ref_div, post_div, sclk;
39
40 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
41 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
42 fb_div <<= 1;
43 fb_div *= spll->reference_freq;
44
45 ref_div =
46 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
Dave Airlie4b30b872009-12-01 09:13:40 +1000[diff] [blame^]47
48 if (ref_div == 0)
49 return 0;
50
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]51 sclk = fb_div / ref_div;
52
53 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
54 if (post_div == 2)
55 sclk >>= 1;
56 else if (post_div == 3)
57 sclk >>= 2;
58 else if (post_div == 4)
59 sclk >>= 4;
60
61 return sclk;
62}
63
64/* 10 khz */
65static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
66{
67 struct radeon_pll *mpll = &rdev->clock.mpll;
68 uint32_t fb_div, ref_div, post_div, mclk;
69
70 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
71 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
72 fb_div <<= 1;
73 fb_div *= mpll->reference_freq;
74
75 ref_div =
76 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
Dave Airlie4b30b872009-12-01 09:13:40 +1000[diff] [blame^]77
78 if (ref_div == 0)
79 return 0;
80
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]81 mclk = fb_div / ref_div;
82
83 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
84 if (post_div == 2)
85 mclk >>= 1;
86 else if (post_div == 3)
87 mclk >>= 2;
88 else if (post_div == 4)
89 mclk >>= 4;
90
91 return mclk;
92}
93
94void radeon_get_clock_info(struct drm_device *dev)
95{
96 struct radeon_device *rdev = dev->dev_private;
97 struct radeon_pll *p1pll = &rdev->clock.p1pll;
98 struct radeon_pll *p2pll = &rdev->clock.p2pll;
99 struct radeon_pll *spll = &rdev->clock.spll;
100 struct radeon_pll *mpll = &rdev->clock.mpll;
101 int ret;
102
103 if (rdev->is_atom_bios)
104 ret = radeon_atom_get_clock_info(dev);
105 else
106 ret = radeon_combios_get_clock_info(dev);
107
108 if (ret) {
109 if (p1pll->reference_div < 2)
110 p1pll->reference_div = 12;
111 if (p2pll->reference_div < 2)
112 p2pll->reference_div = 12;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]113 if (rdev->family < CHIP_RS600) {
114 if (spll->reference_div < 2)
115 spll->reference_div =
116 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
117 RADEON_M_SPLL_REF_DIV_MASK;
118 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]119 if (mpll->reference_div < 2)
120 mpll->reference_div = spll->reference_div;
121 } else {
122 if (ASIC_IS_AVIVO(rdev)) {
123 /* TODO FALLBACK */
124 } else {
125 DRM_INFO("Using generic clock info\n");
126
127 if (rdev->flags & RADEON_IS_IGP) {
128 p1pll->reference_freq = 1432;
129 p2pll->reference_freq = 1432;
130 spll->reference_freq = 1432;
131 mpll->reference_freq = 1432;
132 } else {
133 p1pll->reference_freq = 2700;
134 p2pll->reference_freq = 2700;
135 spll->reference_freq = 2700;
136 mpll->reference_freq = 2700;
137 }
138 p1pll->reference_div =
139 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
140 if (p1pll->reference_div < 2)
141 p1pll->reference_div = 12;
142 p2pll->reference_div = p1pll->reference_div;
143
144 if (rdev->family >= CHIP_R420) {
145 p1pll->pll_in_min = 100;
146 p1pll->pll_in_max = 1350;
147 p1pll->pll_out_min = 20000;
148 p1pll->pll_out_max = 50000;
149 p2pll->pll_in_min = 100;
150 p2pll->pll_in_max = 1350;
151 p2pll->pll_out_min = 20000;
152 p2pll->pll_out_max = 50000;
153 } else {
154 p1pll->pll_in_min = 40;
155 p1pll->pll_in_max = 500;
156 p1pll->pll_out_min = 12500;
157 p1pll->pll_out_max = 35000;
158 p2pll->pll_in_min = 40;
159 p2pll->pll_in_max = 500;
160 p2pll->pll_out_min = 12500;
161 p2pll->pll_out_max = 35000;
162 }
163
164 spll->reference_div =
165 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
166 RADEON_M_SPLL_REF_DIV_MASK;
167 mpll->reference_div = spll->reference_div;
168 rdev->clock.default_sclk =
169 radeon_legacy_get_engine_clock(rdev);
170 rdev->clock.default_mclk =
171 radeon_legacy_get_memory_clock(rdev);
172 }
173 }
174
175 /* pixel clocks */
176 if (ASIC_IS_AVIVO(rdev)) {
177 p1pll->min_post_div = 2;
178 p1pll->max_post_div = 0x7f;
179 p1pll->min_frac_feedback_div = 0;
180 p1pll->max_frac_feedback_div = 9;
181 p2pll->min_post_div = 2;
182 p2pll->max_post_div = 0x7f;
183 p2pll->min_frac_feedback_div = 0;
184 p2pll->max_frac_feedback_div = 9;
185 } else {
186 p1pll->min_post_div = 1;
187 p1pll->max_post_div = 16;
188 p1pll->min_frac_feedback_div = 0;
189 p1pll->max_frac_feedback_div = 0;
190 p2pll->min_post_div = 1;
191 p2pll->max_post_div = 12;
192 p2pll->min_frac_feedback_div = 0;
193 p2pll->max_frac_feedback_div = 0;
194 }
195
196 p1pll->min_ref_div = 2;
197 p1pll->max_ref_div = 0x3ff;
198 p1pll->min_feedback_div = 4;
199 p1pll->max_feedback_div = 0x7ff;
200 p1pll->best_vco = 0;
201
202 p2pll->min_ref_div = 2;
203 p2pll->max_ref_div = 0x3ff;
204 p2pll->min_feedback_div = 4;
205 p2pll->max_feedback_div = 0x7ff;
206 p2pll->best_vco = 0;
207
208 /* system clock */
209 spll->min_post_div = 1;
210 spll->max_post_div = 1;
211 spll->min_ref_div = 2;
212 spll->max_ref_div = 0xff;
213 spll->min_feedback_div = 4;
214 spll->max_feedback_div = 0xff;
215 spll->best_vco = 0;
216
217 /* memory clock */
218 mpll->min_post_div = 1;
219 mpll->max_post_div = 1;
220 mpll->min_ref_div = 2;
221 mpll->max_ref_div = 0xff;
222 mpll->min_feedback_div = 4;
223 mpll->max_feedback_div = 0xff;
224 mpll->best_vco = 0;
225
226}
227
228/* 10 khz */
229static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
230 uint32_t req_clock,
231 int *fb_div, int *post_div)
232{
233 struct radeon_pll *spll = &rdev->clock.spll;
234 int ref_div = spll->reference_div;
235
236 if (!ref_div)
237 ref_div =
238 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
239 RADEON_M_SPLL_REF_DIV_MASK;
240
241 if (req_clock < 15000) {
242 *post_div = 8;
243 req_clock *= 8;
244 } else if (req_clock < 30000) {
245 *post_div = 4;
246 req_clock *= 4;
247 } else if (req_clock < 60000) {
248 *post_div = 2;
249 req_clock *= 2;
250 } else
251 *post_div = 1;
252
253 req_clock *= ref_div;
254 req_clock += spll->reference_freq;
255 req_clock /= (2 * spll->reference_freq);
256
257 *fb_div = req_clock & 0xff;
258
259 req_clock = (req_clock & 0xffff) << 1;
260 req_clock *= spll->reference_freq;
261 req_clock /= ref_div;
262 req_clock /= *post_div;
263
264 return req_clock;
265}
266
267/* 10 khz */
268void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
269 uint32_t eng_clock)
270{
271 uint32_t tmp;
272 int fb_div, post_div;
273
274 /* XXX: wait for idle */
275
276 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
277
278 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
279 tmp &= ~RADEON_DONT_USE_XTALIN;
280 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
281
282 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
283 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
284 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
285
286 udelay(10);
287
288 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
289 tmp |= RADEON_SPLL_SLEEP;
290 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
291
292 udelay(2);
293
294 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
295 tmp |= RADEON_SPLL_RESET;
296 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
297
298 udelay(200);
299
300 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
301 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
302 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
303 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
304
305 /* XXX: verify on different asics */
306 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
307 tmp &= ~RADEON_SPLL_PVG_MASK;
308 if ((eng_clock * post_div) >= 90000)
309 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
310 else
311 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
312 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
313
314 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
315 tmp &= ~RADEON_SPLL_SLEEP;
316 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
317
318 udelay(2);
319
320 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
321 tmp &= ~RADEON_SPLL_RESET;
322 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
323
324 udelay(200);
325
326 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
327 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
328 switch (post_div) {
329 case 1:
330 default:
331 tmp |= 1;
332 break;
333 case 2:
334 tmp |= 2;
335 break;
336 case 4:
337 tmp |= 3;
338 break;
339 case 8:
340 tmp |= 4;
341 break;
342 }
343 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
344
345 udelay(20);
346
347 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
348 tmp |= RADEON_DONT_USE_XTALIN;
349 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
350
351 udelay(10);
352}
353
354void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
355{
356 uint32_t tmp;
357
358 if (enable) {
359 if (rdev->flags & RADEON_SINGLE_CRTC) {
360 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
361 if ((RREG32(RADEON_CONFIG_CNTL) &
362 RADEON_CFG_ATI_REV_ID_MASK) >
363 RADEON_CFG_ATI_REV_A13) {
364 tmp &=
365 ~(RADEON_SCLK_FORCE_CP |
366 RADEON_SCLK_FORCE_RB);
367 }
368 tmp &=
369 ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
370 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
371 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
372 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
373 RADEON_SCLK_FORCE_TDM);
374 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
375 } else if (ASIC_IS_R300(rdev)) {
376 if ((rdev->family == CHIP_RS400) ||
377 (rdev->family == CHIP_RS480)) {
378 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
379 tmp &=
380 ~(RADEON_SCLK_FORCE_DISP2 |
381 RADEON_SCLK_FORCE_CP |
382 RADEON_SCLK_FORCE_HDP |
383 RADEON_SCLK_FORCE_DISP1 |
384 RADEON_SCLK_FORCE_TOP |
385 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
386 | RADEON_SCLK_FORCE_IDCT |
387 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
388 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
389 | R300_SCLK_FORCE_US |
390 RADEON_SCLK_FORCE_TV_SCLK |
391 R300_SCLK_FORCE_SU |
392 RADEON_SCLK_FORCE_OV0);
393 tmp |= RADEON_DYN_STOP_LAT_MASK;
394 tmp |=
395 RADEON_SCLK_FORCE_TOP |
396 RADEON_SCLK_FORCE_VIP;
397 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
398
399 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
400 tmp &= ~RADEON_SCLK_MORE_FORCEON;
401 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
402 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
403
404 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
405 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
406 RADEON_PIXCLK_DAC_ALWAYS_ONb);
407 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
408
409 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
410 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
411 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
412 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
413 R300_DVOCLK_ALWAYS_ONb |
414 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
415 RADEON_PIXCLK_GV_ALWAYS_ONb |
416 R300_PIXCLK_DVO_ALWAYS_ONb |
417 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
418 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
419 R300_PIXCLK_TRANS_ALWAYS_ONb |
420 R300_PIXCLK_TVO_ALWAYS_ONb |
421 R300_P2G2CLK_ALWAYS_ONb |
Roel Kluinaa96e342009-10-06 21:48:40 +0200[diff] [blame]422 R300_P2G2CLK_DAC_ALWAYS_ONb);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]423 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
424 } else if (rdev->family >= CHIP_RV350) {
425 tmp = RREG32_PLL(R300_SCLK_CNTL2);
426 tmp &= ~(R300_SCLK_FORCE_TCL |
427 R300_SCLK_FORCE_GA |
428 R300_SCLK_FORCE_CBA);
429 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
430 R300_SCLK_GA_MAX_DYN_STOP_LAT |
431 R300_SCLK_CBA_MAX_DYN_STOP_LAT);
432 WREG32_PLL(R300_SCLK_CNTL2, tmp);
433
434 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
435 tmp &=
436 ~(RADEON_SCLK_FORCE_DISP2 |
437 RADEON_SCLK_FORCE_CP |
438 RADEON_SCLK_FORCE_HDP |
439 RADEON_SCLK_FORCE_DISP1 |
440 RADEON_SCLK_FORCE_TOP |
441 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
442 | RADEON_SCLK_FORCE_IDCT |
443 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
444 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
445 | R300_SCLK_FORCE_US |
446 RADEON_SCLK_FORCE_TV_SCLK |
447 R300_SCLK_FORCE_SU |
448 RADEON_SCLK_FORCE_OV0);
449 tmp |= RADEON_DYN_STOP_LAT_MASK;
450 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
451
452 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
453 tmp &= ~RADEON_SCLK_MORE_FORCEON;
454 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
455 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
456
457 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
458 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
459 RADEON_PIXCLK_DAC_ALWAYS_ONb);
460 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
461
462 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
463 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
464 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
465 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
466 R300_DVOCLK_ALWAYS_ONb |
467 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
468 RADEON_PIXCLK_GV_ALWAYS_ONb |
469 R300_PIXCLK_DVO_ALWAYS_ONb |
470 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
471 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
472 R300_PIXCLK_TRANS_ALWAYS_ONb |
473 R300_PIXCLK_TVO_ALWAYS_ONb |
474 R300_P2G2CLK_ALWAYS_ONb |
Roel Kluinaa96e342009-10-06 21:48:40 +0200[diff] [blame]475 R300_P2G2CLK_DAC_ALWAYS_ONb);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]476 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
477
478 tmp = RREG32_PLL(RADEON_MCLK_MISC);
479 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
480 RADEON_IO_MCLK_DYN_ENABLE);
481 WREG32_PLL(RADEON_MCLK_MISC, tmp);
482
483 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
484 tmp |= (RADEON_FORCEON_MCLKA |
485 RADEON_FORCEON_MCLKB);
486
487 tmp &= ~(RADEON_FORCEON_YCLKA |
488 RADEON_FORCEON_YCLKB |
489 RADEON_FORCEON_MC);
490
491 /* Some releases of vbios have set DISABLE_MC_MCLKA
492 and DISABLE_MC_MCLKB bits in the vbios table. Setting these
493 bits will cause H/W hang when reading video memory with dynamic clocking
494 enabled. */
495 if ((tmp & R300_DISABLE_MC_MCLKA) &&
496 (tmp & R300_DISABLE_MC_MCLKB)) {
497 /* If both bits are set, then check the active channels */
498 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
499 if (rdev->mc.vram_width == 64) {
500 if (RREG32(RADEON_MEM_CNTL) &
501 R300_MEM_USE_CD_CH_ONLY)
502 tmp &=
503 ~R300_DISABLE_MC_MCLKB;
504 else
505 tmp &=
506 ~R300_DISABLE_MC_MCLKA;
507 } else {
508 tmp &= ~(R300_DISABLE_MC_MCLKA |
509 R300_DISABLE_MC_MCLKB);
510 }
511 }
512
513 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
514 } else {
515 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
516 tmp &= ~(R300_SCLK_FORCE_VAP);
517 tmp |= RADEON_SCLK_FORCE_CP;
518 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
519 udelay(15000);
520
521 tmp = RREG32_PLL(R300_SCLK_CNTL2);
522 tmp &= ~(R300_SCLK_FORCE_TCL |
523 R300_SCLK_FORCE_GA |
524 R300_SCLK_FORCE_CBA);
525 WREG32_PLL(R300_SCLK_CNTL2, tmp);
526 }
527 } else {
528 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
529
530 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
531 RADEON_DISP_DYN_STOP_LAT_MASK |
532 RADEON_DYN_STOP_MODE_MASK);
533
534 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
535 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
536 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
537 udelay(15000);
538
539 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
540 tmp |= RADEON_SCLK_DYN_START_CNTL;
541 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
542 udelay(15000);
543
544 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
545 to lockup randomly, leave them as set by BIOS.
546 */
547 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
548 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
549 tmp &= ~RADEON_SCLK_FORCEON_MASK;
550
551 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
552 if (((rdev->family == CHIP_RV250) &&
553 ((RREG32(RADEON_CONFIG_CNTL) &
554 RADEON_CFG_ATI_REV_ID_MASK) <
555 RADEON_CFG_ATI_REV_A13))
556 || ((rdev->family == CHIP_RV100)
557 &&
558 ((RREG32(RADEON_CONFIG_CNTL) &
559 RADEON_CFG_ATI_REV_ID_MASK) <=
560 RADEON_CFG_ATI_REV_A13))) {
561 tmp |= RADEON_SCLK_FORCE_CP;
562 tmp |= RADEON_SCLK_FORCE_VIP;
563 }
564
565 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
566
567 if ((rdev->family == CHIP_RV200) ||
568 (rdev->family == CHIP_RV250) ||
569 (rdev->family == CHIP_RV280)) {
570 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
571 tmp &= ~RADEON_SCLK_MORE_FORCEON;
572
573 /* RV200::A11 A12 RV250::A11 A12 */
574 if (((rdev->family == CHIP_RV200) ||
575 (rdev->family == CHIP_RV250)) &&
576 ((RREG32(RADEON_CONFIG_CNTL) &
577 RADEON_CFG_ATI_REV_ID_MASK) <
578 RADEON_CFG_ATI_REV_A13)) {
579 tmp |= RADEON_SCLK_MORE_FORCEON;
580 }
581 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
582 udelay(15000);
583 }
584
585 /* RV200::A11 A12, RV250::A11 A12 */
586 if (((rdev->family == CHIP_RV200) ||
587 (rdev->family == CHIP_RV250)) &&
588 ((RREG32(RADEON_CONFIG_CNTL) &
589 RADEON_CFG_ATI_REV_ID_MASK) <
590 RADEON_CFG_ATI_REV_A13)) {
591 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
592 tmp |= RADEON_TCL_BYPASS_DISABLE;
593 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
594 }
595 udelay(15000);
596
597 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
598 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
599 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
600 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
601 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
602 RADEON_PIXCLK_GV_ALWAYS_ONb |
603 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
604 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
605 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
606
607 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
608 udelay(15000);
609
610 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
611 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
612 RADEON_PIXCLK_DAC_ALWAYS_ONb);
613
614 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
615 udelay(15000);
616 }
617 } else {
618 /* Turn everything OFF (ForceON to everything) */
619 if (rdev->flags & RADEON_SINGLE_CRTC) {
620 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
621 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
622 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
623 | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
624 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
625 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
626 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
627 RADEON_SCLK_FORCE_RB);
628 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
629 } else if ((rdev->family == CHIP_RS400) ||
630 (rdev->family == CHIP_RS480)) {
631 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
632 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
633 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
634 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
635 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
636 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
637 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
638 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
639 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
640 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
641
642 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
643 tmp |= RADEON_SCLK_MORE_FORCEON;
644 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
645
646 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
647 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
648 RADEON_PIXCLK_DAC_ALWAYS_ONb |
649 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
650 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
651
652 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
653 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
654 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
655 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
656 R300_DVOCLK_ALWAYS_ONb |
657 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
658 RADEON_PIXCLK_GV_ALWAYS_ONb |
659 R300_PIXCLK_DVO_ALWAYS_ONb |
660 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
661 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
662 R300_PIXCLK_TRANS_ALWAYS_ONb |
663 R300_PIXCLK_TVO_ALWAYS_ONb |
664 R300_P2G2CLK_ALWAYS_ONb |
Roel Kluinaa96e342009-10-06 21:48:40 +0200[diff] [blame]665 R300_P2G2CLK_DAC_ALWAYS_ONb |
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]666 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
667 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
668 } else if (rdev->family >= CHIP_RV350) {
669 /* for RV350/M10, no delays are required. */
670 tmp = RREG32_PLL(R300_SCLK_CNTL2);
671 tmp |= (R300_SCLK_FORCE_TCL |
672 R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
673 WREG32_PLL(R300_SCLK_CNTL2, tmp);
674
675 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
676 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
677 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
678 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
679 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
680 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
681 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
682 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
683 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
684 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
685
686 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
687 tmp |= RADEON_SCLK_MORE_FORCEON;
688 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
689
690 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
691 tmp |= (RADEON_FORCEON_MCLKA |
692 RADEON_FORCEON_MCLKB |
693 RADEON_FORCEON_YCLKA |
694 RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
695 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
696
697 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
698 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
699 RADEON_PIXCLK_DAC_ALWAYS_ONb |
700 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
701 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
702
703 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
704 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
705 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
706 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
707 R300_DVOCLK_ALWAYS_ONb |
708 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
709 RADEON_PIXCLK_GV_ALWAYS_ONb |
710 R300_PIXCLK_DVO_ALWAYS_ONb |
711 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
712 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
713 R300_PIXCLK_TRANS_ALWAYS_ONb |
714 R300_PIXCLK_TVO_ALWAYS_ONb |
715 R300_P2G2CLK_ALWAYS_ONb |
Roel Kluinaa96e342009-10-06 21:48:40 +0200[diff] [blame]716 R300_P2G2CLK_DAC_ALWAYS_ONb |
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]717 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
718 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
719 } else {
720 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
721 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
722 tmp |= RADEON_SCLK_FORCE_SE;
723
724 if (rdev->flags & RADEON_SINGLE_CRTC) {
725 tmp |= (RADEON_SCLK_FORCE_RB |
726 RADEON_SCLK_FORCE_TDM |
727 RADEON_SCLK_FORCE_TAM |
728 RADEON_SCLK_FORCE_PB |
729 RADEON_SCLK_FORCE_RE |
730 RADEON_SCLK_FORCE_VIP |
731 RADEON_SCLK_FORCE_IDCT |
732 RADEON_SCLK_FORCE_TOP |
733 RADEON_SCLK_FORCE_DISP1 |
734 RADEON_SCLK_FORCE_DISP2 |
735 RADEON_SCLK_FORCE_HDP);
736 } else if ((rdev->family == CHIP_R300) ||
737 (rdev->family == CHIP_R350)) {
738 tmp |= (RADEON_SCLK_FORCE_HDP |
739 RADEON_SCLK_FORCE_DISP1 |
740 RADEON_SCLK_FORCE_DISP2 |
741 RADEON_SCLK_FORCE_TOP |
742 RADEON_SCLK_FORCE_IDCT |
743 RADEON_SCLK_FORCE_VIP);
744 }
745 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
746
747 udelay(16000);
748
749 if ((rdev->family == CHIP_R300) ||
750 (rdev->family == CHIP_R350)) {
751 tmp = RREG32_PLL(R300_SCLK_CNTL2);
752 tmp |= (R300_SCLK_FORCE_TCL |
753 R300_SCLK_FORCE_GA |
754 R300_SCLK_FORCE_CBA);
755 WREG32_PLL(R300_SCLK_CNTL2, tmp);
756 udelay(16000);
757 }
758
759 if (rdev->flags & RADEON_IS_IGP) {
760 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
761 tmp &= ~(RADEON_FORCEON_MCLKA |
762 RADEON_FORCEON_YCLKA);
763 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
764 udelay(16000);
765 }
766
767 if ((rdev->family == CHIP_RV200) ||
768 (rdev->family == CHIP_RV250) ||
769 (rdev->family == CHIP_RV280)) {
770 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
771 tmp |= RADEON_SCLK_MORE_FORCEON;
772 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
773 udelay(16000);
774 }
775
776 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
777 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
778 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
779 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
780 RADEON_PIXCLK_GV_ALWAYS_ONb |
781 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
782 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
783 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
784
785 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
786 udelay(16000);
787
788 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
789 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
790 RADEON_PIXCLK_DAC_ALWAYS_ONb);
791 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
792 }
793 }
794}
795
796static void radeon_apply_clock_quirks(struct radeon_device *rdev)
797{
798 uint32_t tmp;
799
800 /* XXX make sure engine is idle */
801
802 if (rdev->family < CHIP_RS600) {
803 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
804 if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev))
805 tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
806 if ((rdev->family == CHIP_RV250)
807 || (rdev->family == CHIP_RV280))
808 tmp |=
809 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
810 if ((rdev->family == CHIP_RV350)
811 || (rdev->family == CHIP_RV380))
812 tmp |= R300_SCLK_FORCE_VAP;
813 if (rdev->family == CHIP_R420)
814 tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
815 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
816 } else if (rdev->family < CHIP_R600) {
817 tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL);
818 tmp |= AVIVO_CP_FORCEON;
819 WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp);
820
821 tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL);
822 tmp |= AVIVO_E2_FORCEON;
823 WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp);
824
825 tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL);
826 tmp |= AVIVO_IDCT_FORCEON;
827 WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp);
828 }
829}
830
831int radeon_static_clocks_init(struct drm_device *dev)
832{
833 struct radeon_device *rdev = dev->dev_private;
834
835 /* XXX make sure engine is idle */
836
837 if (radeon_dynclks != -1) {
838 if (radeon_dynclks)
839 radeon_set_clock_gating(rdev, 1);
840 }
841 radeon_apply_clock_quirks(rdev);
842 return 0;
843}