blob: 8f93e2b4b0c821153ca9969255e22e1f95c95513 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
Dave Airlie746c1aa2009-12-08 07:07:28 +100036#include <drm_dp_helper.h>
Ben Skeggs68adac52010-04-28 11:46:42 +100037#include <drm_fixed.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020038#include <linux/i2c.h>
39#include <linux/i2c-id.h>
40#include <linux/i2c-algo-bit.h>
Jerome Glissec93bb852009-07-13 21:04:08 +020041
Dave Airlie38651672010-03-30 05:34:13 +000042struct radeon_bo;
Jerome Glissec93bb852009-07-13 21:04:08 +020043struct radeon_device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020044
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
Jerome Glisse771fe6b2009-06-05 14:42:42 +020050enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
Alex Deucherd79766f2009-12-17 19:00:29 -050066 TV_STD_PAL_N,
Jerome Glisse771fe6b2009-06-05 14:42:42 +020067};
68
Alex Deucher5b1714d2010-08-03 19:59:20 -040069enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
Alex Deucher8e36ed02010-05-18 19:26:47 -040075enum radeon_hpd_id {
76 RADEON_HPD_1 = 0,
77 RADEON_HPD_2,
78 RADEON_HPD_3,
79 RADEON_HPD_4,
80 RADEON_HPD_5,
81 RADEON_HPD_6,
82 RADEON_HPD_NONE = 0xff,
83};
84
Alex Deucherf376b942010-08-05 21:21:16 -040085#define RADEON_MAX_I2C_BUS 16
86
Alex Deucher9b9fe722009-11-10 15:59:44 -050087/* radeon gpio-based i2c
88 * 1. "mask" reg and bits
89 * grabs the gpio pins for software use
90 * 0=not held 1=held
91 * 2. "a" reg and bits
92 * output pin value
93 * 0=low 1=high
94 * 3. "en" reg and bits
95 * sets the pin direction
96 * 0=input 1=output
97 * 4. "y" reg and bits
98 * input pin value
99 * 0=low 1=high
100 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200101struct radeon_i2c_bus_rec {
102 bool valid;
Alex Deucher6a93cb22009-11-23 17:39:28 -0500103 /* id used by atom */
104 uint8_t i2c_id;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500105 /* id used by atom */
Alex Deucher8e36ed02010-05-18 19:26:47 -0400106 enum radeon_hpd_id hpd;
Alex Deucher6a93cb22009-11-23 17:39:28 -0500107 /* can be used with hw i2c engine */
108 bool hw_capable;
109 /* uses multi-media i2c engine */
110 bool mm_i2c;
111 /* regs and bits */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200112 uint32_t mask_clk_reg;
113 uint32_t mask_data_reg;
114 uint32_t a_clk_reg;
115 uint32_t a_data_reg;
Alex Deucher9b9fe722009-11-10 15:59:44 -0500116 uint32_t en_clk_reg;
117 uint32_t en_data_reg;
118 uint32_t y_clk_reg;
119 uint32_t y_data_reg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200120 uint32_t mask_clk_mask;
121 uint32_t mask_data_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122 uint32_t a_clk_mask;
123 uint32_t a_data_mask;
Alex Deucher9b9fe722009-11-10 15:59:44 -0500124 uint32_t en_clk_mask;
125 uint32_t en_data_mask;
126 uint32_t y_clk_mask;
127 uint32_t y_data_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200128};
129
130struct radeon_tmds_pll {
131 uint32_t freq;
132 uint32_t value;
133};
134
135#define RADEON_MAX_BIOS_CONNECTOR 16
136
Alex Deucher7c27f872010-02-02 12:05:01 -0500137/* pll flags */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200138#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
139#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
140#define RADEON_PLL_USE_REF_DIV (1 << 2)
141#define RADEON_PLL_LEGACY (1 << 3)
142#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
143#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
144#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
145#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
146#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
147#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
148#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
Alex Deucherd0e275a2009-07-13 11:08:18 -0400149#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
Alex Deucherfc103322010-01-19 17:16:10 -0500150#define RADEON_PLL_USE_POST_DIV (1 << 12)
Alex Deucher86cb2bb2010-03-08 12:55:16 -0500151#define RADEON_PLL_IS_LCD (1 << 13)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200152
Alex Deucher7c27f872010-02-02 12:05:01 -0500153/* pll algo */
154enum radeon_pll_algo {
155 PLL_ALGO_LEGACY,
Alex Deucher383be5d2010-02-23 03:24:38 -0500156 PLL_ALGO_NEW
Alex Deucher7c27f872010-02-02 12:05:01 -0500157};
158
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159struct radeon_pll {
Alex Deucherfc103322010-01-19 17:16:10 -0500160 /* reference frequency */
161 uint32_t reference_freq;
162
163 /* fixed dividers */
164 uint32_t reference_div;
165 uint32_t post_div;
166
167 /* pll in/out limits */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200168 uint32_t pll_in_min;
169 uint32_t pll_in_max;
170 uint32_t pll_out_min;
171 uint32_t pll_out_max;
Alex Deucher86cb2bb2010-03-08 12:55:16 -0500172 uint32_t lcd_pll_out_min;
173 uint32_t lcd_pll_out_max;
Alex Deucherfc103322010-01-19 17:16:10 -0500174 uint32_t best_vco;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200175
Alex Deucherfc103322010-01-19 17:16:10 -0500176 /* divider limits */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200177 uint32_t min_ref_div;
178 uint32_t max_ref_div;
179 uint32_t min_post_div;
180 uint32_t max_post_div;
181 uint32_t min_feedback_div;
182 uint32_t max_feedback_div;
183 uint32_t min_frac_feedback_div;
184 uint32_t max_frac_feedback_div;
Alex Deucherfc103322010-01-19 17:16:10 -0500185
186 /* flags for the current clock */
187 uint32_t flags;
188
189 /* pll id */
190 uint32_t id;
Alex Deucher7c27f872010-02-02 12:05:01 -0500191 /* pll algo */
192 enum radeon_pll_algo algo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200193};
194
195struct radeon_i2c_chan {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200196 struct i2c_adapter adapter;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000197 struct drm_device *dev;
198 union {
Alex Deucherac1aade2010-03-14 12:22:44 -0400199 struct i2c_algo_bit_data bit;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000200 struct i2c_algo_dp_aux_data dp;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000201 } algo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200202 struct radeon_i2c_bus_rec rec;
203};
204
205/* mostly for macs, but really any system without connector tables */
206enum radeon_connector_table {
207 CT_NONE,
208 CT_GENERIC,
209 CT_IBOOK,
210 CT_POWERBOOK_EXTERNAL,
211 CT_POWERBOOK_INTERNAL,
212 CT_POWERBOOK_VGA,
213 CT_MINI_EXTERNAL,
214 CT_MINI_INTERNAL,
215 CT_IMAC_G5_ISIGHT,
216 CT_EMAC,
Dave Airlie76a71422010-06-11 01:09:05 -0400217 CT_RN50_POWER,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200218};
219
Alex Deucherfcec5702009-11-10 21:25:07 -0500220enum radeon_dvo_chip {
221 DVO_SIL164,
222 DVO_SIL1178,
223};
224
Dave Airlie8be48d92010-03-30 05:34:14 +0000225struct radeon_fbdev;
Dave Airlie38651672010-03-30 05:34:13 +0000226
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200227struct radeon_mode_info {
228 struct atom_context *atom_context;
Mathias Fröhlich61c4b242009-10-27 15:08:01 -0400229 struct card_info *atom_card_info;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200230 enum radeon_connector_table connector_table;
231 bool mode_config_initialized;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500232 struct radeon_crtc *crtcs[6];
Dave Airlie445282d2009-09-09 17:40:54 +1000233 /* DVI-I properties */
234 struct drm_property *coherent_mode_property;
235 /* DAC enable load detect */
236 struct drm_property *load_detect_property;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400237 /* TV standard */
Dave Airlie445282d2009-09-09 17:40:54 +1000238 struct drm_property *tv_std_property;
239 /* legacy TMDS PLL detect */
240 struct drm_property *tmds_pll_property;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400241 /* underscan */
242 struct drm_property *underscan_property;
Alex Deucher3c537882010-02-05 04:21:19 -0500243 /* hardcoded DFP edid from BIOS */
244 struct edid *bios_hardcoded_edid;
Dave Airlie38651672010-03-30 05:34:13 +0000245
246 /* pointer to fbdev info structure */
Dave Airlie8be48d92010-03-30 05:34:14 +0000247 struct radeon_fbdev *rfbdev;
Jerome Glissec93bb852009-07-13 21:04:08 +0200248};
249
Dave Airlie4ce001a2009-08-13 16:32:14 +1000250#define MAX_H_CODE_TIMING_LEN 32
251#define MAX_V_CODE_TIMING_LEN 32
252
253/* need to store these as reading
254 back code tables is excessive */
255struct radeon_tv_regs {
256 uint32_t tv_uv_adr;
257 uint32_t timing_cntl;
258 uint32_t hrestart;
259 uint32_t vrestart;
260 uint32_t frestart;
261 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
262 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
263};
264
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200265struct radeon_crtc {
266 struct drm_crtc base;
267 int crtc_id;
268 u16 lut_r[256], lut_g[256], lut_b[256];
269 bool enabled;
270 bool can_tile;
271 uint32_t crtc_offset;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200272 struct drm_gem_object *cursor_bo;
273 uint64_t cursor_addr;
274 int cursor_width;
275 int cursor_height;
Dave Airlie41623382009-07-09 15:04:19 +1000276 uint32_t legacy_display_base_addr;
Alex Deucherc836e862009-07-13 13:51:03 -0400277 uint32_t legacy_cursor_offset;
Jerome Glissec93bb852009-07-13 21:04:08 +0200278 enum radeon_rmx_type rmx_type;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400279 u8 h_border;
280 u8 v_border;
Jerome Glissec93bb852009-07-13 21:04:08 +0200281 fixed20_12 vsc;
282 fixed20_12 hsc;
Alex Deucherde2103e2009-10-09 15:14:30 -0400283 struct drm_display_mode native_mode;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500284 int pll_id;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200285};
286
287struct radeon_encoder_primary_dac {
288 /* legacy primary dac */
289 uint32_t ps2_pdac_adj;
290};
291
292struct radeon_encoder_lvds {
293 /* legacy lvds */
294 uint16_t panel_vcc_delay;
295 uint8_t panel_pwr_delay;
296 uint8_t panel_digon_delay;
297 uint8_t panel_blon_delay;
298 uint16_t panel_ref_divider;
299 uint8_t panel_post_divider;
300 uint16_t panel_fb_divider;
301 bool use_bios_dividers;
302 uint32_t lvds_gen_cntl;
303 /* panel mode */
Alex Deucherde2103e2009-10-09 15:14:30 -0400304 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200305};
306
307struct radeon_encoder_tv_dac {
308 /* legacy tv dac */
309 uint32_t ps2_tvdac_adj;
310 uint32_t ntsc_tvdac_adj;
311 uint32_t pal_tvdac_adj;
312
Dave Airlie4ce001a2009-08-13 16:32:14 +1000313 int h_pos;
314 int v_pos;
315 int h_size;
316 int supported_tv_stds;
317 bool tv_on;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200318 enum radeon_tv_std tv_std;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000319 struct radeon_tv_regs tv;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200320};
321
322struct radeon_encoder_int_tmds {
323 /* legacy int tmds */
324 struct radeon_tmds_pll tmds_pll[4];
325};
326
Alex Deucherfcec5702009-11-10 21:25:07 -0500327struct radeon_encoder_ext_tmds {
328 /* tmds over dvo */
329 struct radeon_i2c_chan *i2c_bus;
330 uint8_t slave_addr;
331 enum radeon_dvo_chip dvo_chip;
332};
333
Alex Deucherebbe1cb2009-10-16 11:15:25 -0400334/* spread spectrum */
335struct radeon_atom_ss {
336 uint16_t percentage;
337 uint8_t type;
338 uint8_t step;
339 uint8_t delay;
340 uint8_t range;
341 uint8_t refdiv;
342};
343
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200344struct radeon_encoder_atom_dig {
Alex Deucher5137ee92010-08-12 18:58:47 -0400345 bool linkb;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200346 /* atom dig */
347 bool coherent_mode;
Dave Airlief28cf332010-01-28 17:15:25 +1000348 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200349 /* atom lvds */
350 uint32_t lvds_misc;
351 uint16_t panel_pwr_delay;
Alex Deucher7c27f872010-02-02 12:05:01 -0500352 enum radeon_pll_algo pll_algo;
Alex Deucherebbe1cb2009-10-16 11:15:25 -0400353 struct radeon_atom_ss *ss;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200354 /* panel mode */
Alex Deucherde2103e2009-10-09 15:14:30 -0400355 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200356};
357
Dave Airlie4ce001a2009-08-13 16:32:14 +1000358struct radeon_encoder_atom_dac {
359 enum radeon_tv_std tv_std;
360};
361
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200362struct radeon_encoder {
363 struct drm_encoder base;
Alex Deucher5137ee92010-08-12 18:58:47 -0400364 uint32_t encoder_enum;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200365 uint32_t encoder_id;
366 uint32_t devices;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000367 uint32_t active_device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200368 uint32_t flags;
369 uint32_t pixel_clock;
370 enum radeon_rmx_type rmx_type;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400371 enum radeon_underscan_type underscan_type;
Alex Deucherde2103e2009-10-09 15:14:30 -0400372 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200373 void *enc_priv;
Christian König58bd0862010-04-05 22:14:55 +0200374 int audio_polling_active;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200375 int hdmi_offset;
Rafał Miłecki808032e2010-03-06 13:03:33 +0000376 int hdmi_config_offset;
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200377 int hdmi_audio_workaround;
378 int hdmi_buffer_status;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200379};
380
381struct radeon_connector_atom_dig {
382 uint32_t igp_lane_info;
Alex Deucher4143e912009-11-23 18:02:35 -0500383 /* displayport */
Dave Airlie746c1aa2009-12-08 07:07:28 +1000384 struct radeon_i2c_chan *dp_i2c_bus;
Alex Deucher1a66c952009-11-20 19:40:13 -0500385 u8 dpcd[8];
Alex Deucher4143e912009-11-23 18:02:35 -0500386 u8 dp_sink_type;
Alex Deucher5801ead2009-11-24 13:32:59 -0500387 int dp_clock;
388 int dp_lane_count;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200389};
390
Alex Deuchereed45b32009-12-04 14:45:27 -0500391struct radeon_gpio_rec {
392 bool valid;
393 u8 id;
394 u32 reg;
395 u32 mask;
396};
397
Alex Deuchereed45b32009-12-04 14:45:27 -0500398struct radeon_hpd {
399 enum radeon_hpd_id hpd;
400 u8 plugged_state;
401 struct radeon_gpio_rec gpio;
402};
403
Alex Deucher26b5bc92010-08-05 21:21:18 -0400404struct radeon_router {
405 bool valid;
406 u32 router_id;
407 struct radeon_i2c_bus_rec i2c_info;
408 u8 i2c_addr;
409 u8 mux_type;
410 u8 mux_control_pin;
411 u8 mux_state;
412};
413
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200414struct radeon_connector {
415 struct drm_connector base;
416 uint32_t connector_id;
417 uint32_t devices;
418 struct radeon_i2c_chan *ddc_bus;
Alex Deucher5b1714d2010-08-03 19:59:20 -0400419 /* some systems have an hdmi and vga port with a shared ddc line */
Alex Deucher0294cf4f2009-10-15 16:16:35 -0400420 bool shared_ddc;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000421 bool use_digital;
422 /* we need to mind the EDID between detect
423 and get modes due to analog/digital/tvencoder */
424 struct edid *edid;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200425 void *con_priv;
Dave Airlie445282d2009-09-09 17:40:54 +1000426 bool dac_load_detect;
Alex Deucherb75fad02009-11-05 13:16:01 -0500427 uint16_t connector_object_id;
Alex Deuchereed45b32009-12-04 14:45:27 -0500428 struct radeon_hpd hpd;
Alex Deucher26b5bc92010-08-05 21:21:18 -0400429 struct radeon_router router;
430 struct radeon_i2c_chan *router_bus;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200431};
432
433struct radeon_framebuffer {
434 struct drm_framebuffer base;
435 struct drm_gem_object *obj;
436};
437
Alex Deucherd79766f2009-12-17 19:00:29 -0500438extern enum radeon_tv_std
439radeon_combios_get_tv_info(struct radeon_device *rdev);
440extern enum radeon_tv_std
441radeon_atombios_get_tv_info(struct radeon_device *rdev);
442
Alex Deucher5b1714d2010-08-03 19:59:20 -0400443extern struct drm_connector *
444radeon_get_connector_for_encoder(struct drm_encoder *encoder);
445
Alex Deucherd4877cf2009-12-04 16:56:37 -0500446extern void radeon_connector_hotplug(struct drm_connector *connector);
447extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
Alex Deucher5801ead2009-11-24 13:32:59 -0500448extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
449 struct drm_display_mode *mode);
450extern void radeon_dp_set_link_config(struct drm_connector *connector,
451 struct drm_display_mode *mode);
452extern void dp_link_train(struct drm_encoder *encoder,
453 struct drm_connector *connector);
Alex Deucher4143e912009-11-23 18:02:35 -0500454extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
Alex Deucher9fa05c92009-11-27 13:01:46 -0500455extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500456extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
Alex Deucher5801ead2009-11-24 13:32:59 -0500457extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
458 int action, uint8_t lane_num,
459 uint8_t lane_set);
Dave Airlie746c1aa2009-12-08 07:07:28 +1000460extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
461 uint8_t write_byte, uint8_t *read_byte);
462
Alex Deucherf376b942010-08-05 21:21:16 -0400463extern void radeon_i2c_init(struct radeon_device *rdev);
464extern void radeon_i2c_fini(struct radeon_device *rdev);
465extern void radeon_combios_i2c_init(struct radeon_device *rdev);
466extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
467extern void radeon_i2c_add(struct radeon_device *rdev,
468 struct radeon_i2c_bus_rec *rec,
469 const char *name);
470extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
471 struct radeon_i2c_bus_rec *i2c_bus);
Dave Airlie746c1aa2009-12-08 07:07:28 +1000472extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
Alex Deucher6a93cb22009-11-23 17:39:28 -0500473 struct radeon_i2c_bus_rec *rec,
474 const char *name);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200475extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
476 struct radeon_i2c_bus_rec *rec,
477 const char *name);
478extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
Alex Deucher5a6f98f2009-12-22 15:04:48 -0500479extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
480 u8 slave_addr,
481 u8 addr,
482 u8 *val);
483extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
484 u8 slave_addr,
485 u8 addr,
486 u8 val);
Alex Deucher26b5bc92010-08-05 21:21:18 -0400487extern void radeon_router_select_port(struct radeon_connector *radeon_connector);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200488extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
489extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
490
491extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
492
493extern void radeon_compute_pll(struct radeon_pll *pll,
494 uint64_t freq,
495 uint32_t *dot_clock_p,
496 uint32_t *fb_div_p,
497 uint32_t *frac_fb_div_p,
498 uint32_t *ref_div_p,
Alex Deucherfc103322010-01-19 17:16:10 -0500499 uint32_t *post_div_p);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200500
Dave Airlie1f3b6a42009-10-13 14:10:37 +1000501extern void radeon_setup_encoder_clones(struct drm_device *dev);
502
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200503struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
504struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
505struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
506struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
507struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
508extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
Alex Deucher32f48ff2009-11-30 01:54:16 -0500509extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200510extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000511extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200512
513extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
514extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
515 struct drm_framebuffer *old_fb);
516extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
517 struct drm_display_mode *mode,
518 struct drm_display_mode *adjusted_mode,
519 int x, int y,
520 struct drm_framebuffer *old_fb);
521extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
522
523extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
524 struct drm_framebuffer *old_fb);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200525
526extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
527 struct drm_file *file_priv,
528 uint32_t handle,
529 uint32_t width,
530 uint32_t height);
531extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
532 int x, int y);
533
Alex Deucher3c537882010-02-05 04:21:19 -0500534extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
535extern struct edid *
536radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200537extern bool radeon_atom_get_clock_info(struct drm_device *dev);
538extern bool radeon_combios_get_clock_info(struct drm_device *dev);
539extern struct radeon_encoder_atom_dig *
540radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
Alex Deucherfcec5702009-11-10 21:25:07 -0500541extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
542 struct radeon_encoder_int_tmds *tmds);
543extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
544 struct radeon_encoder_int_tmds *tmds);
545extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
546 struct radeon_encoder_int_tmds *tmds);
547extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
548 struct radeon_encoder_ext_tmds *tmds);
549extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
550 struct radeon_encoder_ext_tmds *tmds);
Alex Deucher6fe7ac32009-06-12 17:26:08 +0000551extern struct radeon_encoder_primary_dac *
552radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
553extern struct radeon_encoder_tv_dac *
554radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200555extern struct radeon_encoder_lvds *
556radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200557extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
558extern struct radeon_encoder_tv_dac *
559radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
560extern struct radeon_encoder_primary_dac *
561radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
Alex Deucherfcec5702009-11-10 21:25:07 -0500562extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
563extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200564extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
565extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
566extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
567extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
Yang Zhaof657c2a2009-09-15 12:21:01 +1000568extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
569extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200570extern void
571radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
572extern void
573radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
574extern void
575radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
576extern void
577radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
578extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
579 u16 blue, int regno);
Dave Airlieb8c00ac2009-10-06 13:54:01 +1000580extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
581 u16 *blue, int regno);
Dave Airlie38651672010-03-30 05:34:13 +0000582void radeon_framebuffer_init(struct drm_device *dev,
583 struct radeon_framebuffer *rfb,
584 struct drm_mode_fb_cmd *mode_cmd,
585 struct drm_gem_object *obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200586
587int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
588bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
589bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
590void radeon_atombios_init_crtc(struct drm_device *dev,
591 struct radeon_crtc *radeon_crtc);
592void radeon_legacy_init_crtc(struct drm_device *dev,
593 struct radeon_crtc *radeon_crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200594
595void radeon_get_clock_info(struct drm_device *dev);
596
597extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
598extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
599
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200600void radeon_enc_destroy(struct drm_encoder *encoder);
601void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
602void radeon_combios_asic_init(struct drm_device *dev);
603extern int radeon_static_clocks_init(struct drm_device *dev);
Jerome Glissec93bb852009-07-13 21:04:08 +0200604bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
605 struct drm_display_mode *mode,
606 struct drm_display_mode *adjusted_mode);
Alex Deucher35153872010-04-30 12:00:44 -0400607void radeon_panel_mode_fixup(struct drm_encoder *encoder,
608 struct drm_display_mode *adjusted_mode);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000609void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200610
Dave Airlie4ce001a2009-08-13 16:32:14 +1000611/* legacy tv */
612void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
613 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
614 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
615void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
616 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
617 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
618void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
619 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
620 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
621void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
622 struct drm_display_mode *mode,
623 struct drm_display_mode *adjusted_mode);
Dave Airlie38651672010-03-30 05:34:13 +0000624
625/* fbdev layer */
626int radeon_fbdev_init(struct radeon_device *rdev);
627void radeon_fbdev_fini(struct radeon_device *rdev);
628void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
629int radeon_fbdev_total_size(struct radeon_device *rdev);
630bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
Dave Airlieeb1f8e42010-05-07 06:42:51 +0000631
632void radeon_fb_output_poll_changed(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200633#endif