blob: 5d584b0dbb517043c05ce3d7050ffd999932ce2f [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_FALCON_HWDEFS_H
12#define EFX_FALCON_HWDEFS_H
13
14/*
15 * Falcon hardware value definitions.
16 * Falcon is the internal codename for the SFC4000 controller that is
17 * present in SFE400X evaluation boards
18 */
19
20/**************************************************************************
21 *
22 * Falcon registers
23 *
24 **************************************************************************
25 */
26
27/* Address region register */
28#define ADR_REGION_REG_KER 0x00
29#define ADR_REGION0_LBN 0
30#define ADR_REGION0_WIDTH 18
31#define ADR_REGION1_LBN 32
32#define ADR_REGION1_WIDTH 18
33#define ADR_REGION2_LBN 64
34#define ADR_REGION2_WIDTH 18
35#define ADR_REGION3_LBN 96
36#define ADR_REGION3_WIDTH 18
37
38/* Interrupt enable register */
39#define INT_EN_REG_KER 0x0010
40#define KER_INT_KER_LBN 3
41#define KER_INT_KER_WIDTH 1
42#define DRV_INT_EN_KER_LBN 0
43#define DRV_INT_EN_KER_WIDTH 1
44
45/* Interrupt status address register */
46#define INT_ADR_REG_KER 0x0030
47#define NORM_INT_VEC_DIS_KER_LBN 64
48#define NORM_INT_VEC_DIS_KER_WIDTH 1
49#define INT_ADR_KER_LBN 0
50#define INT_ADR_KER_WIDTH EFX_DMA_TYPE_WIDTH(64) /* not 46 for this one */
51
52/* Interrupt status register (B0 only) */
53#define INT_ISR0_B0 0x90
54#define INT_ISR1_B0 0xA0
55
56/* Interrupt acknowledge register (A0/A1 only) */
57#define INT_ACK_REG_KER_A1 0x0050
58#define INT_ACK_DUMMY_DATA_LBN 0
59#define INT_ACK_DUMMY_DATA_WIDTH 32
60
61/* Interrupt acknowledge work-around register (A0/A1 only )*/
62#define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070
63
64/* SPI host command register */
65#define EE_SPI_HCMD_REG_KER 0x0100
66#define EE_SPI_HCMD_CMD_EN_LBN 31
67#define EE_SPI_HCMD_CMD_EN_WIDTH 1
68#define EE_WR_TIMER_ACTIVE_LBN 28
69#define EE_WR_TIMER_ACTIVE_WIDTH 1
70#define EE_SPI_HCMD_SF_SEL_LBN 24
71#define EE_SPI_HCMD_SF_SEL_WIDTH 1
72#define EE_SPI_EEPROM 0
73#define EE_SPI_FLASH 1
74#define EE_SPI_HCMD_DABCNT_LBN 16
75#define EE_SPI_HCMD_DABCNT_WIDTH 5
76#define EE_SPI_HCMD_READ_LBN 15
77#define EE_SPI_HCMD_READ_WIDTH 1
78#define EE_SPI_READ 1
79#define EE_SPI_WRITE 0
80#define EE_SPI_HCMD_DUBCNT_LBN 12
81#define EE_SPI_HCMD_DUBCNT_WIDTH 2
82#define EE_SPI_HCMD_ADBCNT_LBN 8
83#define EE_SPI_HCMD_ADBCNT_WIDTH 2
84#define EE_SPI_HCMD_ENC_LBN 0
85#define EE_SPI_HCMD_ENC_WIDTH 8
86
87/* SPI host address register */
88#define EE_SPI_HADR_REG_KER 0x0110
89#define EE_SPI_HADR_ADR_LBN 0
90#define EE_SPI_HADR_ADR_WIDTH 24
91
92/* SPI host data register */
93#define EE_SPI_HDATA_REG_KER 0x0120
94
Ben Hutchings4a5b5042008-09-01 12:47:16 +010095/* SPI/VPD config register */
96#define EE_VPD_CFG_REG_KER 0x0140
97#define EE_VPD_EN_LBN 0
98#define EE_VPD_EN_WIDTH 1
99#define EE_VPD_EN_AD9_MODE_LBN 1
100#define EE_VPD_EN_AD9_MODE_WIDTH 1
101#define EE_EE_CLOCK_DIV_LBN 112
102#define EE_EE_CLOCK_DIV_WIDTH 7
103#define EE_SF_CLOCK_DIV_LBN 120
104#define EE_SF_CLOCK_DIV_WIDTH 7
105
Ben Hutchings8ceee662008-04-27 12:55:59 +0100106/* PCIE CORE ACCESS REG */
107#define PCIE_CORE_ADDR_PCIE_DEVICE_CTRL_STAT 0x68
108#define PCIE_CORE_ADDR_PCIE_LINK_CTRL_STAT 0x70
109#define PCIE_CORE_ADDR_ACK_RPL_TIMER 0x700
110#define PCIE_CORE_ADDR_ACK_FREQ 0x70C
111
112/* NIC status register */
113#define NIC_STAT_REG 0x0200
114#define ONCHIP_SRAM_LBN 16
115#define ONCHIP_SRAM_WIDTH 1
116#define SF_PRST_LBN 9
117#define SF_PRST_WIDTH 1
118#define EE_PRST_LBN 8
119#define EE_PRST_WIDTH 1
Ben Hutchings8ceee662008-04-27 12:55:59 +0100120/* These bit definitions are extrapolated from the list of numerical
121 * values for STRAP_PINS.
122 */
123#define STRAP_10G_LBN 2
124#define STRAP_10G_WIDTH 1
125#define STRAP_PCIE_LBN 0
126#define STRAP_PCIE_WIDTH 1
127
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100128#define BOOTED_USING_NVDEVICE_LBN 3
129#define BOOTED_USING_NVDEVICE_WIDTH 1
130
Ben Hutchings8ceee662008-04-27 12:55:59 +0100131/* GPIO control register */
132#define GPIO_CTL_REG_KER 0x0210
133#define GPIO_OUTPUTS_LBN (16)
134#define GPIO_OUTPUTS_WIDTH (4)
135#define GPIO_INPUTS_LBN (8)
136#define GPIO_DIRECTION_LBN (24)
137#define GPIO_DIRECTION_WIDTH (4)
138#define GPIO_DIRECTION_OUT (1)
139#define GPIO_SRAM_SLEEP (1 << 1)
140
141#define GPIO3_OEN_LBN (GPIO_DIRECTION_LBN + 3)
142#define GPIO3_OEN_WIDTH 1
143#define GPIO2_OEN_LBN (GPIO_DIRECTION_LBN + 2)
144#define GPIO2_OEN_WIDTH 1
145#define GPIO1_OEN_LBN (GPIO_DIRECTION_LBN + 1)
146#define GPIO1_OEN_WIDTH 1
147#define GPIO0_OEN_LBN (GPIO_DIRECTION_LBN + 0)
148#define GPIO0_OEN_WIDTH 1
149
150#define GPIO3_OUT_LBN (GPIO_OUTPUTS_LBN + 3)
151#define GPIO3_OUT_WIDTH 1
152#define GPIO2_OUT_LBN (GPIO_OUTPUTS_LBN + 2)
153#define GPIO2_OUT_WIDTH 1
154#define GPIO1_OUT_LBN (GPIO_OUTPUTS_LBN + 1)
155#define GPIO1_OUT_WIDTH 1
156#define GPIO0_OUT_LBN (GPIO_OUTPUTS_LBN + 0)
157#define GPIO0_OUT_WIDTH 1
158
159#define GPIO3_IN_LBN (GPIO_INPUTS_LBN + 3)
160#define GPIO3_IN_WIDTH 1
161#define GPIO2_IN_WIDTH 1
162#define GPIO1_IN_WIDTH 1
163#define GPIO0_IN_LBN (GPIO_INPUTS_LBN + 0)
164#define GPIO0_IN_WIDTH 1
165
166/* Global control register */
167#define GLB_CTL_REG_KER 0x0220
168#define EXT_PHY_RST_CTL_LBN 63
169#define EXT_PHY_RST_CTL_WIDTH 1
170#define PCIE_SD_RST_CTL_LBN 61
171#define PCIE_SD_RST_CTL_WIDTH 1
172
173#define PCIE_NSTCK_RST_CTL_LBN 58
174#define PCIE_NSTCK_RST_CTL_WIDTH 1
175#define PCIE_CORE_RST_CTL_LBN 57
176#define PCIE_CORE_RST_CTL_WIDTH 1
177#define EE_RST_CTL_LBN 49
178#define EE_RST_CTL_WIDTH 1
179#define RST_XGRX_LBN 24
180#define RST_XGRX_WIDTH 1
181#define RST_XGTX_LBN 23
182#define RST_XGTX_WIDTH 1
183#define RST_EM_LBN 22
184#define RST_EM_WIDTH 1
185#define EXT_PHY_RST_DUR_LBN 1
186#define EXT_PHY_RST_DUR_WIDTH 3
187#define SWRST_LBN 0
188#define SWRST_WIDTH 1
189#define INCLUDE_IN_RESET 0
190#define EXCLUDE_FROM_RESET 1
191
192/* Fatal interrupt register */
193#define FATAL_INTR_REG_KER 0x0230
194#define RBUF_OWN_INT_KER_EN_LBN 39
195#define RBUF_OWN_INT_KER_EN_WIDTH 1
196#define TBUF_OWN_INT_KER_EN_LBN 38
197#define TBUF_OWN_INT_KER_EN_WIDTH 1
198#define ILL_ADR_INT_KER_EN_LBN 33
199#define ILL_ADR_INT_KER_EN_WIDTH 1
200#define MEM_PERR_INT_KER_LBN 8
201#define MEM_PERR_INT_KER_WIDTH 1
202#define INT_KER_ERROR_LBN 0
203#define INT_KER_ERROR_WIDTH 12
204
205#define DP_CTRL_REG 0x250
206#define FLS_EVQ_ID_LBN 0
207#define FLS_EVQ_ID_WIDTH 11
208
209#define MEM_STAT_REG_KER 0x260
210
211/* Debug probe register */
212#define DEBUG_BLK_SEL_MISC 7
213#define DEBUG_BLK_SEL_SERDES 6
214#define DEBUG_BLK_SEL_EM 5
215#define DEBUG_BLK_SEL_SR 4
216#define DEBUG_BLK_SEL_EV 3
217#define DEBUG_BLK_SEL_RX 2
218#define DEBUG_BLK_SEL_TX 1
219#define DEBUG_BLK_SEL_BIU 0
220
221/* FPGA build version */
222#define ALTERA_BUILD_REG_KER 0x0300
223#define VER_ALL_LBN 0
224#define VER_ALL_WIDTH 32
225
226/* Spare EEPROM bits register (flash 0x390) */
227#define SPARE_REG_KER 0x310
228#define MEM_PERR_EN_TX_DATA_LBN 72
229#define MEM_PERR_EN_TX_DATA_WIDTH 2
230
231/* Timer table for kernel access */
232#define TIMER_CMD_REG_KER 0x420
233#define TIMER_MODE_LBN 12
234#define TIMER_MODE_WIDTH 2
235#define TIMER_MODE_DIS 0
236#define TIMER_MODE_INT_HLDOFF 2
237#define TIMER_VAL_LBN 0
238#define TIMER_VAL_WIDTH 12
239
240/* Driver generated event register */
241#define DRV_EV_REG_KER 0x440
242#define DRV_EV_QID_LBN 64
243#define DRV_EV_QID_WIDTH 12
244#define DRV_EV_DATA_LBN 0
245#define DRV_EV_DATA_WIDTH 64
246
247/* Buffer table configuration register */
248#define BUF_TBL_CFG_REG_KER 0x600
249#define BUF_TBL_MODE_LBN 3
250#define BUF_TBL_MODE_WIDTH 1
251#define BUF_TBL_MODE_HALF 0
252#define BUF_TBL_MODE_FULL 1
253
254/* SRAM receive descriptor cache configuration register */
255#define SRM_RX_DC_CFG_REG_KER 0x610
256#define SRM_RX_DC_BASE_ADR_LBN 0
257#define SRM_RX_DC_BASE_ADR_WIDTH 21
258
259/* SRAM transmit descriptor cache configuration register */
260#define SRM_TX_DC_CFG_REG_KER 0x620
261#define SRM_TX_DC_BASE_ADR_LBN 0
262#define SRM_TX_DC_BASE_ADR_WIDTH 21
263
264/* SRAM configuration register */
265#define SRM_CFG_REG_KER 0x630
266#define SRAM_OOB_BT_INIT_EN_LBN 3
267#define SRAM_OOB_BT_INIT_EN_WIDTH 1
268#define SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0
269#define SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3
270#define SRM_NB_BSZ_1BANKS_2M 0
271#define SRM_NB_BSZ_1BANKS_4M 1
272#define SRM_NB_BSZ_1BANKS_8M 2
273#define SRM_NB_BSZ_DEFAULT 3 /* char driver will set the default */
274#define SRM_NB_BSZ_2BANKS_4M 4
275#define SRM_NB_BSZ_2BANKS_8M 5
276#define SRM_NB_BSZ_2BANKS_16M 6
277#define SRM_NB_BSZ_RESERVED 7
278
279/* Special buffer table update register */
280#define BUF_TBL_UPD_REG_KER 0x0650
281#define BUF_UPD_CMD_LBN 63
282#define BUF_UPD_CMD_WIDTH 1
283#define BUF_CLR_CMD_LBN 62
284#define BUF_CLR_CMD_WIDTH 1
285#define BUF_CLR_END_ID_LBN 32
286#define BUF_CLR_END_ID_WIDTH 20
287#define BUF_CLR_START_ID_LBN 0
288#define BUF_CLR_START_ID_WIDTH 20
289
290/* Receive configuration register */
291#define RX_CFG_REG_KER 0x800
292
293/* B0 */
294#define RX_INGR_EN_B0_LBN 47
295#define RX_INGR_EN_B0_WIDTH 1
296#define RX_DESC_PUSH_EN_B0_LBN 43
297#define RX_DESC_PUSH_EN_B0_WIDTH 1
298#define RX_XON_TX_TH_B0_LBN 33
299#define RX_XON_TX_TH_B0_WIDTH 5
300#define RX_XOFF_TX_TH_B0_LBN 28
301#define RX_XOFF_TX_TH_B0_WIDTH 5
302#define RX_USR_BUF_SIZE_B0_LBN 19
303#define RX_USR_BUF_SIZE_B0_WIDTH 9
304#define RX_XON_MAC_TH_B0_LBN 10
305#define RX_XON_MAC_TH_B0_WIDTH 9
306#define RX_XOFF_MAC_TH_B0_LBN 1
307#define RX_XOFF_MAC_TH_B0_WIDTH 9
308#define RX_XOFF_MAC_EN_B0_LBN 0
309#define RX_XOFF_MAC_EN_B0_WIDTH 1
310
311/* A1 */
312#define RX_DESC_PUSH_EN_A1_LBN 35
313#define RX_DESC_PUSH_EN_A1_WIDTH 1
314#define RX_XON_TX_TH_A1_LBN 25
315#define RX_XON_TX_TH_A1_WIDTH 5
316#define RX_XOFF_TX_TH_A1_LBN 20
317#define RX_XOFF_TX_TH_A1_WIDTH 5
318#define RX_USR_BUF_SIZE_A1_LBN 11
319#define RX_USR_BUF_SIZE_A1_WIDTH 9
320#define RX_XON_MAC_TH_A1_LBN 6
321#define RX_XON_MAC_TH_A1_WIDTH 5
322#define RX_XOFF_MAC_TH_A1_LBN 1
323#define RX_XOFF_MAC_TH_A1_WIDTH 5
324#define RX_XOFF_MAC_EN_A1_LBN 0
325#define RX_XOFF_MAC_EN_A1_WIDTH 1
326
327/* Receive filter control register */
328#define RX_FILTER_CTL_REG 0x810
329#define UDP_FULL_SRCH_LIMIT_LBN 32
330#define UDP_FULL_SRCH_LIMIT_WIDTH 8
331#define NUM_KER_LBN 24
332#define NUM_KER_WIDTH 2
333#define UDP_WILD_SRCH_LIMIT_LBN 16
334#define UDP_WILD_SRCH_LIMIT_WIDTH 8
335#define TCP_WILD_SRCH_LIMIT_LBN 8
336#define TCP_WILD_SRCH_LIMIT_WIDTH 8
337#define TCP_FULL_SRCH_LIMIT_LBN 0
338#define TCP_FULL_SRCH_LIMIT_WIDTH 8
339
340/* RX queue flush register */
341#define RX_FLUSH_DESCQ_REG_KER 0x0820
342#define RX_FLUSH_DESCQ_CMD_LBN 24
343#define RX_FLUSH_DESCQ_CMD_WIDTH 1
344#define RX_FLUSH_DESCQ_LBN 0
345#define RX_FLUSH_DESCQ_WIDTH 12
346
347/* Receive descriptor update register */
348#define RX_DESC_UPD_REG_KER_DWORD (0x830 + 12)
349#define RX_DESC_WPTR_DWORD_LBN 0
350#define RX_DESC_WPTR_DWORD_WIDTH 12
351
352/* Receive descriptor cache configuration register */
353#define RX_DC_CFG_REG_KER 0x840
354#define RX_DC_SIZE_LBN 0
355#define RX_DC_SIZE_WIDTH 2
356
357#define RX_DC_PF_WM_REG_KER 0x850
358#define RX_DC_PF_LWM_LBN 0
359#define RX_DC_PF_LWM_WIDTH 6
360
361/* RX no descriptor drop counter */
362#define RX_NODESC_DROP_REG_KER 0x880
363#define RX_NODESC_DROP_CNT_LBN 0
364#define RX_NODESC_DROP_CNT_WIDTH 16
365
366/* RX black magic register */
367#define RX_SELF_RST_REG_KER 0x890
368#define RX_ISCSI_DIS_LBN 17
369#define RX_ISCSI_DIS_WIDTH 1
370#define RX_NODESC_WAIT_DIS_LBN 9
371#define RX_NODESC_WAIT_DIS_WIDTH 1
372#define RX_RECOVERY_EN_LBN 8
373#define RX_RECOVERY_EN_WIDTH 1
374
375/* TX queue flush register */
376#define TX_FLUSH_DESCQ_REG_KER 0x0a00
377#define TX_FLUSH_DESCQ_CMD_LBN 12
378#define TX_FLUSH_DESCQ_CMD_WIDTH 1
379#define TX_FLUSH_DESCQ_LBN 0
380#define TX_FLUSH_DESCQ_WIDTH 12
381
382/* Transmit descriptor update register */
383#define TX_DESC_UPD_REG_KER_DWORD (0xa10 + 12)
384#define TX_DESC_WPTR_DWORD_LBN 0
385#define TX_DESC_WPTR_DWORD_WIDTH 12
386
387/* Transmit descriptor cache configuration register */
388#define TX_DC_CFG_REG_KER 0xa20
389#define TX_DC_SIZE_LBN 0
390#define TX_DC_SIZE_WIDTH 2
391
392/* Transmit checksum configuration register (A0/A1 only) */
393#define TX_CHKSM_CFG_REG_KER_A1 0xa30
394
395/* Transmit configuration register */
396#define TX_CFG_REG_KER 0xa50
397#define TX_NO_EOP_DISC_EN_LBN 5
398#define TX_NO_EOP_DISC_EN_WIDTH 1
399
400/* Transmit configuration register 2 */
401#define TX_CFG2_REG_KER 0xa80
402#define TX_CSR_PUSH_EN_LBN 89
403#define TX_CSR_PUSH_EN_WIDTH 1
404#define TX_RX_SPACER_LBN 64
405#define TX_RX_SPACER_WIDTH 8
406#define TX_SW_EV_EN_LBN 59
407#define TX_SW_EV_EN_WIDTH 1
408#define TX_RX_SPACER_EN_LBN 57
409#define TX_RX_SPACER_EN_WIDTH 1
410#define TX_PREF_THRESHOLD_LBN 19
411#define TX_PREF_THRESHOLD_WIDTH 2
412#define TX_ONE_PKT_PER_Q_LBN 18
413#define TX_ONE_PKT_PER_Q_WIDTH 1
414#define TX_DIS_NON_IP_EV_LBN 17
415#define TX_DIS_NON_IP_EV_WIDTH 1
416#define TX_FLUSH_MIN_LEN_EN_B0_LBN 7
417#define TX_FLUSH_MIN_LEN_EN_B0_WIDTH 1
418
419/* PHY management transmit data register */
420#define MD_TXD_REG_KER 0xc00
421#define MD_TXD_LBN 0
422#define MD_TXD_WIDTH 16
423
424/* PHY management receive data register */
425#define MD_RXD_REG_KER 0xc10
426#define MD_RXD_LBN 0
427#define MD_RXD_WIDTH 16
428
429/* PHY management configuration & status register */
430#define MD_CS_REG_KER 0xc20
431#define MD_GC_LBN 4
432#define MD_GC_WIDTH 1
433#define MD_RIC_LBN 2
434#define MD_RIC_WIDTH 1
435#define MD_RDC_LBN 1
436#define MD_RDC_WIDTH 1
437#define MD_WRC_LBN 0
438#define MD_WRC_WIDTH 1
439
440/* PHY management PHY address register */
441#define MD_PHY_ADR_REG_KER 0xc30
442#define MD_PHY_ADR_LBN 0
443#define MD_PHY_ADR_WIDTH 16
444
445/* PHY management ID register */
446#define MD_ID_REG_KER 0xc40
447#define MD_PRT_ADR_LBN 11
448#define MD_PRT_ADR_WIDTH 5
449#define MD_DEV_ADR_LBN 6
450#define MD_DEV_ADR_WIDTH 5
451/* Used for writing both at once */
452#define MD_PRT_DEV_ADR_LBN 6
453#define MD_PRT_DEV_ADR_WIDTH 10
454
455/* PHY management status & mask register (DWORD read only) */
456#define MD_STAT_REG_KER 0xc50
457#define MD_BSERR_LBN 2
458#define MD_BSERR_WIDTH 1
459#define MD_LNFL_LBN 1
460#define MD_LNFL_WIDTH 1
461#define MD_BSY_LBN 0
462#define MD_BSY_WIDTH 1
463
464/* Port 0 and 1 MAC stats registers */
465#define MAC0_STAT_DMA_REG_KER 0xc60
466#define MAC_STAT_DMA_CMD_LBN 48
467#define MAC_STAT_DMA_CMD_WIDTH 1
468#define MAC_STAT_DMA_ADR_LBN 0
469#define MAC_STAT_DMA_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
470
471/* Port 0 and 1 MAC control registers */
472#define MAC0_CTRL_REG_KER 0xc80
473#define MAC_XOFF_VAL_LBN 16
474#define MAC_XOFF_VAL_WIDTH 16
475#define TXFIFO_DRAIN_EN_B0_LBN 7
476#define TXFIFO_DRAIN_EN_B0_WIDTH 1
477#define MAC_BCAD_ACPT_LBN 4
478#define MAC_BCAD_ACPT_WIDTH 1
479#define MAC_UC_PROM_LBN 3
480#define MAC_UC_PROM_WIDTH 1
481#define MAC_LINK_STATUS_LBN 2
482#define MAC_LINK_STATUS_WIDTH 1
483#define MAC_SPEED_LBN 0
484#define MAC_SPEED_WIDTH 2
485
486/* 10G XAUI XGXS default values */
487#define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */
488#define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */
489#define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */
490
491/* Multicast address hash table */
492#define MAC_MCAST_HASH_REG0_KER 0xca0
493#define MAC_MCAST_HASH_REG1_KER 0xcb0
494
Ben Hutchings8ceee662008-04-27 12:55:59 +0100495/* XGMAC address register low */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100496#define XM_ADR_LO_REG 0x1200
Ben Hutchings8ceee662008-04-27 12:55:59 +0100497#define XM_ADR_3_LBN 24
498#define XM_ADR_3_WIDTH 8
499#define XM_ADR_2_LBN 16
500#define XM_ADR_2_WIDTH 8
501#define XM_ADR_1_LBN 8
502#define XM_ADR_1_WIDTH 8
503#define XM_ADR_0_LBN 0
504#define XM_ADR_0_WIDTH 8
505
506/* XGMAC address register high */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100507#define XM_ADR_HI_REG 0x1210
Ben Hutchings8ceee662008-04-27 12:55:59 +0100508#define XM_ADR_5_LBN 8
509#define XM_ADR_5_WIDTH 8
510#define XM_ADR_4_LBN 0
511#define XM_ADR_4_WIDTH 8
512
513/* XGMAC global configuration */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100514#define XM_GLB_CFG_REG 0x1220
Ben Hutchings8ceee662008-04-27 12:55:59 +0100515#define XM_RX_STAT_EN_LBN 11
516#define XM_RX_STAT_EN_WIDTH 1
517#define XM_TX_STAT_EN_LBN 10
518#define XM_TX_STAT_EN_WIDTH 1
519#define XM_RX_JUMBO_MODE_LBN 6
520#define XM_RX_JUMBO_MODE_WIDTH 1
521#define XM_INTCLR_MODE_LBN 3
522#define XM_INTCLR_MODE_WIDTH 1
523#define XM_CORE_RST_LBN 0
524#define XM_CORE_RST_WIDTH 1
525
526/* XGMAC transmit configuration */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100527#define XM_TX_CFG_REG 0x1230
Ben Hutchings8ceee662008-04-27 12:55:59 +0100528#define XM_IPG_LBN 16
529#define XM_IPG_WIDTH 4
530#define XM_FCNTL_LBN 10
531#define XM_FCNTL_WIDTH 1
532#define XM_TXCRC_LBN 8
533#define XM_TXCRC_WIDTH 1
534#define XM_AUTO_PAD_LBN 5
535#define XM_AUTO_PAD_WIDTH 1
536#define XM_TX_PRMBL_LBN 2
537#define XM_TX_PRMBL_WIDTH 1
538#define XM_TXEN_LBN 1
539#define XM_TXEN_WIDTH 1
540
541/* XGMAC receive configuration */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100542#define XM_RX_CFG_REG 0x1240
Ben Hutchings8ceee662008-04-27 12:55:59 +0100543#define XM_PASS_CRC_ERR_LBN 25
544#define XM_PASS_CRC_ERR_WIDTH 1
545#define XM_ACPT_ALL_MCAST_LBN 11
546#define XM_ACPT_ALL_MCAST_WIDTH 1
547#define XM_ACPT_ALL_UCAST_LBN 9
548#define XM_ACPT_ALL_UCAST_WIDTH 1
549#define XM_AUTO_DEPAD_LBN 8
550#define XM_AUTO_DEPAD_WIDTH 1
551#define XM_RXEN_LBN 1
552#define XM_RXEN_WIDTH 1
553
554/* XGMAC management interrupt mask register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100555#define XM_MGT_INT_MSK_REG_B0 0x1250
Ben Hutchings8ceee662008-04-27 12:55:59 +0100556#define XM_MSK_PRMBLE_ERR_LBN 2
557#define XM_MSK_PRMBLE_ERR_WIDTH 1
558#define XM_MSK_RMTFLT_LBN 1
559#define XM_MSK_RMTFLT_WIDTH 1
560#define XM_MSK_LCLFLT_LBN 0
561#define XM_MSK_LCLFLT_WIDTH 1
562
563/* XGMAC flow control register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100564#define XM_FC_REG 0x1270
Ben Hutchings8ceee662008-04-27 12:55:59 +0100565#define XM_PAUSE_TIME_LBN 16
566#define XM_PAUSE_TIME_WIDTH 16
567#define XM_DIS_FCNTL_LBN 0
568#define XM_DIS_FCNTL_WIDTH 1
569
570/* XGMAC pause time count register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100571#define XM_PAUSE_TIME_REG 0x1290
Ben Hutchings8ceee662008-04-27 12:55:59 +0100572
573/* XGMAC transmit parameter register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100574#define XM_TX_PARAM_REG 0x012d0
Ben Hutchings8ceee662008-04-27 12:55:59 +0100575#define XM_TX_JUMBO_MODE_LBN 31
576#define XM_TX_JUMBO_MODE_WIDTH 1
577#define XM_MAX_TX_FRM_SIZE_LBN 16
578#define XM_MAX_TX_FRM_SIZE_WIDTH 14
579
580/* XGMAC receive parameter register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100581#define XM_RX_PARAM_REG 0x12e0
Ben Hutchings8ceee662008-04-27 12:55:59 +0100582#define XM_MAX_RX_FRM_SIZE_LBN 0
583#define XM_MAX_RX_FRM_SIZE_WIDTH 14
584
585/* XGMAC management interrupt status register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100586#define XM_MGT_INT_REG_B0 0x12f0
Ben Hutchings8ceee662008-04-27 12:55:59 +0100587#define XM_PRMBLE_ERR 2
588#define XM_PRMBLE_WIDTH 1
589#define XM_RMTFLT_LBN 1
590#define XM_RMTFLT_WIDTH 1
591#define XM_LCLFLT_LBN 0
592#define XM_LCLFLT_WIDTH 1
593
594/* XGXS/XAUI powerdown/reset register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100595#define XX_PWR_RST_REG 0x1300
Ben Hutchings8ceee662008-04-27 12:55:59 +0100596
597#define XX_PWRDND_EN_LBN 15
598#define XX_PWRDND_EN_WIDTH 1
599#define XX_PWRDNC_EN_LBN 14
600#define XX_PWRDNC_EN_WIDTH 1
601#define XX_PWRDNB_EN_LBN 13
602#define XX_PWRDNB_EN_WIDTH 1
603#define XX_PWRDNA_EN_LBN 12
604#define XX_PWRDNA_EN_WIDTH 1
605#define XX_RSTPLLCD_EN_LBN 9
606#define XX_RSTPLLCD_EN_WIDTH 1
607#define XX_RSTPLLAB_EN_LBN 8
608#define XX_RSTPLLAB_EN_WIDTH 1
609#define XX_RESETD_EN_LBN 7
610#define XX_RESETD_EN_WIDTH 1
611#define XX_RESETC_EN_LBN 6
612#define XX_RESETC_EN_WIDTH 1
613#define XX_RESETB_EN_LBN 5
614#define XX_RESETB_EN_WIDTH 1
615#define XX_RESETA_EN_LBN 4
616#define XX_RESETA_EN_WIDTH 1
617#define XX_RSTXGXSRX_EN_LBN 2
618#define XX_RSTXGXSRX_EN_WIDTH 1
619#define XX_RSTXGXSTX_EN_LBN 1
620#define XX_RSTXGXSTX_EN_WIDTH 1
621#define XX_RST_XX_EN_LBN 0
622#define XX_RST_XX_EN_WIDTH 1
623
624/* XGXS/XAUI powerdown/reset control register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100625#define XX_SD_CTL_REG 0x1310
Ben Hutchings8ceee662008-04-27 12:55:59 +0100626#define XX_HIDRVD_LBN 15
627#define XX_HIDRVD_WIDTH 1
628#define XX_LODRVD_LBN 14
629#define XX_LODRVD_WIDTH 1
630#define XX_HIDRVC_LBN 13
631#define XX_HIDRVC_WIDTH 1
632#define XX_LODRVC_LBN 12
633#define XX_LODRVC_WIDTH 1
634#define XX_HIDRVB_LBN 11
635#define XX_HIDRVB_WIDTH 1
636#define XX_LODRVB_LBN 10
637#define XX_LODRVB_WIDTH 1
638#define XX_HIDRVA_LBN 9
639#define XX_HIDRVA_WIDTH 1
640#define XX_LODRVA_LBN 8
641#define XX_LODRVA_WIDTH 1
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100642#define XX_LPBKD_LBN 3
643#define XX_LPBKD_WIDTH 1
644#define XX_LPBKC_LBN 2
645#define XX_LPBKC_WIDTH 1
646#define XX_LPBKB_LBN 1
647#define XX_LPBKB_WIDTH 1
648#define XX_LPBKA_LBN 0
649#define XX_LPBKA_WIDTH 1
Ben Hutchings8ceee662008-04-27 12:55:59 +0100650
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100651#define XX_TXDRV_CTL_REG 0x1320
Ben Hutchings8ceee662008-04-27 12:55:59 +0100652#define XX_DEQD_LBN 28
653#define XX_DEQD_WIDTH 4
654#define XX_DEQC_LBN 24
655#define XX_DEQC_WIDTH 4
656#define XX_DEQB_LBN 20
657#define XX_DEQB_WIDTH 4
658#define XX_DEQA_LBN 16
659#define XX_DEQA_WIDTH 4
660#define XX_DTXD_LBN 12
661#define XX_DTXD_WIDTH 4
662#define XX_DTXC_LBN 8
663#define XX_DTXC_WIDTH 4
664#define XX_DTXB_LBN 4
665#define XX_DTXB_WIDTH 4
666#define XX_DTXA_LBN 0
667#define XX_DTXA_WIDTH 4
668
669/* XAUI XGXS core status register */
Ben Hutchingsc1e5fcc2008-09-01 12:48:41 +0100670#define XX_CORE_STAT_REG 0x1360
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100671#define XX_FORCE_SIG_LBN 24
672#define XX_FORCE_SIG_WIDTH 8
673#define XX_FORCE_SIG_DECODE_FORCED 0xff
674#define XX_XGXS_LB_EN_LBN 23
675#define XX_XGXS_LB_EN_WIDTH 1
676#define XX_XGMII_LB_EN_LBN 22
677#define XX_XGMII_LB_EN_WIDTH 1
Ben Hutchings8ceee662008-04-27 12:55:59 +0100678#define XX_ALIGN_DONE_LBN 20
679#define XX_ALIGN_DONE_WIDTH 1
680#define XX_SYNC_STAT_LBN 16
681#define XX_SYNC_STAT_WIDTH 4
682#define XX_SYNC_STAT_DECODE_SYNCED 0xf
683#define XX_COMMA_DET_LBN 12
684#define XX_COMMA_DET_WIDTH 4
685#define XX_COMMA_DET_DECODE_DETECTED 0xf
686#define XX_COMMA_DET_RESET 0xf
687#define XX_CHARERR_LBN 4
688#define XX_CHARERR_WIDTH 4
689#define XX_CHARERR_RESET 0xf
690#define XX_DISPERR_LBN 0
691#define XX_DISPERR_WIDTH 4
692#define XX_DISPERR_RESET 0xf
693
694/* Receive filter table */
695#define RX_FILTER_TBL0 0xF00000
696
697/* Receive descriptor pointer table */
698#define RX_DESC_PTR_TBL_KER_A1 0x11800
699#define RX_DESC_PTR_TBL_KER_B0 0xF40000
700#define RX_DESC_PTR_TBL_KER_P0 0x900
701#define RX_ISCSI_DDIG_EN_LBN 88
702#define RX_ISCSI_DDIG_EN_WIDTH 1
703#define RX_ISCSI_HDIG_EN_LBN 87
704#define RX_ISCSI_HDIG_EN_WIDTH 1
705#define RX_DESCQ_BUF_BASE_ID_LBN 36
706#define RX_DESCQ_BUF_BASE_ID_WIDTH 20
707#define RX_DESCQ_EVQ_ID_LBN 24
708#define RX_DESCQ_EVQ_ID_WIDTH 12
709#define RX_DESCQ_OWNER_ID_LBN 10
710#define RX_DESCQ_OWNER_ID_WIDTH 14
711#define RX_DESCQ_LABEL_LBN 5
712#define RX_DESCQ_LABEL_WIDTH 5
713#define RX_DESCQ_SIZE_LBN 3
714#define RX_DESCQ_SIZE_WIDTH 2
715#define RX_DESCQ_SIZE_4K 3
716#define RX_DESCQ_SIZE_2K 2
717#define RX_DESCQ_SIZE_1K 1
718#define RX_DESCQ_SIZE_512 0
719#define RX_DESCQ_TYPE_LBN 2
720#define RX_DESCQ_TYPE_WIDTH 1
721#define RX_DESCQ_JUMBO_LBN 1
722#define RX_DESCQ_JUMBO_WIDTH 1
723#define RX_DESCQ_EN_LBN 0
724#define RX_DESCQ_EN_WIDTH 1
725
726/* Transmit descriptor pointer table */
727#define TX_DESC_PTR_TBL_KER_A1 0x11900
728#define TX_DESC_PTR_TBL_KER_B0 0xF50000
729#define TX_DESC_PTR_TBL_KER_P0 0xa40
730#define TX_NON_IP_DROP_DIS_B0_LBN 91
731#define TX_NON_IP_DROP_DIS_B0_WIDTH 1
732#define TX_IP_CHKSM_DIS_B0_LBN 90
733#define TX_IP_CHKSM_DIS_B0_WIDTH 1
734#define TX_TCP_CHKSM_DIS_B0_LBN 89
735#define TX_TCP_CHKSM_DIS_B0_WIDTH 1
736#define TX_DESCQ_EN_LBN 88
737#define TX_DESCQ_EN_WIDTH 1
738#define TX_ISCSI_DDIG_EN_LBN 87
739#define TX_ISCSI_DDIG_EN_WIDTH 1
740#define TX_ISCSI_HDIG_EN_LBN 86
741#define TX_ISCSI_HDIG_EN_WIDTH 1
742#define TX_DESCQ_BUF_BASE_ID_LBN 36
743#define TX_DESCQ_BUF_BASE_ID_WIDTH 20
744#define TX_DESCQ_EVQ_ID_LBN 24
745#define TX_DESCQ_EVQ_ID_WIDTH 12
746#define TX_DESCQ_OWNER_ID_LBN 10
747#define TX_DESCQ_OWNER_ID_WIDTH 14
748#define TX_DESCQ_LABEL_LBN 5
749#define TX_DESCQ_LABEL_WIDTH 5
750#define TX_DESCQ_SIZE_LBN 3
751#define TX_DESCQ_SIZE_WIDTH 2
752#define TX_DESCQ_SIZE_4K 3
753#define TX_DESCQ_SIZE_2K 2
754#define TX_DESCQ_SIZE_1K 1
755#define TX_DESCQ_SIZE_512 0
756#define TX_DESCQ_TYPE_LBN 1
757#define TX_DESCQ_TYPE_WIDTH 2
758
759/* Event queue pointer */
760#define EVQ_PTR_TBL_KER_A1 0x11a00
761#define EVQ_PTR_TBL_KER_B0 0xf60000
762#define EVQ_PTR_TBL_KER_P0 0x500
763#define EVQ_EN_LBN 23
764#define EVQ_EN_WIDTH 1
765#define EVQ_SIZE_LBN 20
766#define EVQ_SIZE_WIDTH 3
767#define EVQ_SIZE_32K 6
768#define EVQ_SIZE_16K 5
769#define EVQ_SIZE_8K 4
770#define EVQ_SIZE_4K 3
771#define EVQ_SIZE_2K 2
772#define EVQ_SIZE_1K 1
773#define EVQ_SIZE_512 0
774#define EVQ_BUF_BASE_ID_LBN 0
775#define EVQ_BUF_BASE_ID_WIDTH 20
776
777/* Event queue read pointer */
778#define EVQ_RPTR_REG_KER_A1 0x11b00
779#define EVQ_RPTR_REG_KER_B0 0xfa0000
780#define EVQ_RPTR_REG_KER_DWORD (EVQ_RPTR_REG_KER + 0)
781#define EVQ_RPTR_DWORD_LBN 0
782#define EVQ_RPTR_DWORD_WIDTH 14
783
784/* RSS indirection table */
785#define RX_RSS_INDIR_TBL_B0 0xFB0000
786#define RX_RSS_INDIR_ENT_B0_LBN 0
787#define RX_RSS_INDIR_ENT_B0_WIDTH 6
788
789/* Special buffer descriptors (full-mode) */
790#define BUF_FULL_TBL_KER_A1 0x8000
791#define BUF_FULL_TBL_KER_B0 0x800000
792#define IP_DAT_BUF_SIZE_LBN 50
793#define IP_DAT_BUF_SIZE_WIDTH 1
794#define IP_DAT_BUF_SIZE_8K 1
795#define IP_DAT_BUF_SIZE_4K 0
796#define BUF_ADR_REGION_LBN 48
797#define BUF_ADR_REGION_WIDTH 2
798#define BUF_ADR_FBUF_LBN 14
799#define BUF_ADR_FBUF_WIDTH 34
800#define BUF_OWNER_ID_FBUF_LBN 0
801#define BUF_OWNER_ID_FBUF_WIDTH 14
802
803/* Transmit descriptor */
804#define TX_KER_PORT_LBN 63
805#define TX_KER_PORT_WIDTH 1
806#define TX_KER_CONT_LBN 62
807#define TX_KER_CONT_WIDTH 1
808#define TX_KER_BYTE_CNT_LBN 48
809#define TX_KER_BYTE_CNT_WIDTH 14
810#define TX_KER_BUF_REGION_LBN 46
811#define TX_KER_BUF_REGION_WIDTH 2
812#define TX_KER_BUF_REGION0_DECODE 0
813#define TX_KER_BUF_REGION1_DECODE 1
814#define TX_KER_BUF_REGION2_DECODE 2
815#define TX_KER_BUF_REGION3_DECODE 3
816#define TX_KER_BUF_ADR_LBN 0
817#define TX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
818
819/* Receive descriptor */
820#define RX_KER_BUF_SIZE_LBN 48
821#define RX_KER_BUF_SIZE_WIDTH 14
822#define RX_KER_BUF_REGION_LBN 46
823#define RX_KER_BUF_REGION_WIDTH 2
824#define RX_KER_BUF_REGION0_DECODE 0
825#define RX_KER_BUF_REGION1_DECODE 1
826#define RX_KER_BUF_REGION2_DECODE 2
827#define RX_KER_BUF_REGION3_DECODE 3
828#define RX_KER_BUF_ADR_LBN 0
829#define RX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46)
830
831/**************************************************************************
832 *
833 * Falcon events
834 *
835 **************************************************************************
836 */
837
838/* Event queue entries */
839#define EV_CODE_LBN 60
840#define EV_CODE_WIDTH 4
841#define RX_IP_EV_DECODE 0
842#define TX_IP_EV_DECODE 2
843#define DRIVER_EV_DECODE 5
844#define GLOBAL_EV_DECODE 6
845#define DRV_GEN_EV_DECODE 7
846#define WHOLE_EVENT_LBN 0
847#define WHOLE_EVENT_WIDTH 64
848
849/* Receive events */
850#define RX_EV_PKT_OK_LBN 56
851#define RX_EV_PKT_OK_WIDTH 1
852#define RX_EV_PAUSE_FRM_ERR_LBN 55
853#define RX_EV_PAUSE_FRM_ERR_WIDTH 1
854#define RX_EV_BUF_OWNER_ID_ERR_LBN 54
855#define RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
856#define RX_EV_IF_FRAG_ERR_LBN 53
857#define RX_EV_IF_FRAG_ERR_WIDTH 1
858#define RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
859#define RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
860#define RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
861#define RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
862#define RX_EV_ETH_CRC_ERR_LBN 50
863#define RX_EV_ETH_CRC_ERR_WIDTH 1
864#define RX_EV_FRM_TRUNC_LBN 49
865#define RX_EV_FRM_TRUNC_WIDTH 1
866#define RX_EV_DRIB_NIB_LBN 48
867#define RX_EV_DRIB_NIB_WIDTH 1
868#define RX_EV_TOBE_DISC_LBN 47
869#define RX_EV_TOBE_DISC_WIDTH 1
870#define RX_EV_PKT_TYPE_LBN 44
871#define RX_EV_PKT_TYPE_WIDTH 3
872#define RX_EV_PKT_TYPE_ETH_DECODE 0
873#define RX_EV_PKT_TYPE_LLC_DECODE 1
874#define RX_EV_PKT_TYPE_JUMBO_DECODE 2
875#define RX_EV_PKT_TYPE_VLAN_DECODE 3
876#define RX_EV_PKT_TYPE_VLAN_LLC_DECODE 4
877#define RX_EV_PKT_TYPE_VLAN_JUMBO_DECODE 5
878#define RX_EV_HDR_TYPE_LBN 42
879#define RX_EV_HDR_TYPE_WIDTH 2
880#define RX_EV_HDR_TYPE_TCP_IPV4_DECODE 0
881#define RX_EV_HDR_TYPE_UDP_IPV4_DECODE 1
882#define RX_EV_HDR_TYPE_OTHER_IP_DECODE 2
883#define RX_EV_HDR_TYPE_NON_IP_DECODE 3
884#define RX_EV_HDR_TYPE_HAS_CHECKSUMS(hdr_type) \
885 ((hdr_type) <= RX_EV_HDR_TYPE_UDP_IPV4_DECODE)
886#define RX_EV_MCAST_HASH_MATCH_LBN 40
887#define RX_EV_MCAST_HASH_MATCH_WIDTH 1
888#define RX_EV_MCAST_PKT_LBN 39
889#define RX_EV_MCAST_PKT_WIDTH 1
890#define RX_EV_Q_LABEL_LBN 32
891#define RX_EV_Q_LABEL_WIDTH 5
892#define RX_EV_JUMBO_CONT_LBN 31
893#define RX_EV_JUMBO_CONT_WIDTH 1
894#define RX_EV_BYTE_CNT_LBN 16
895#define RX_EV_BYTE_CNT_WIDTH 14
896#define RX_EV_SOP_LBN 15
897#define RX_EV_SOP_WIDTH 1
898#define RX_EV_DESC_PTR_LBN 0
899#define RX_EV_DESC_PTR_WIDTH 12
900
901/* Transmit events */
902#define TX_EV_PKT_ERR_LBN 38
903#define TX_EV_PKT_ERR_WIDTH 1
904#define TX_EV_Q_LABEL_LBN 32
905#define TX_EV_Q_LABEL_WIDTH 5
906#define TX_EV_WQ_FF_FULL_LBN 15
907#define TX_EV_WQ_FF_FULL_WIDTH 1
908#define TX_EV_COMP_LBN 12
909#define TX_EV_COMP_WIDTH 1
910#define TX_EV_DESC_PTR_LBN 0
911#define TX_EV_DESC_PTR_WIDTH 12
912
913/* Driver events */
914#define DRIVER_EV_SUB_CODE_LBN 56
915#define DRIVER_EV_SUB_CODE_WIDTH 4
916#define DRIVER_EV_SUB_DATA_LBN 0
917#define DRIVER_EV_SUB_DATA_WIDTH 14
918#define TX_DESCQ_FLS_DONE_EV_DECODE 0
919#define RX_DESCQ_FLS_DONE_EV_DECODE 1
920#define EVQ_INIT_DONE_EV_DECODE 2
921#define EVQ_NOT_EN_EV_DECODE 3
922#define RX_DESCQ_FLSFF_OVFL_EV_DECODE 4
923#define SRM_UPD_DONE_EV_DECODE 5
924#define WAKE_UP_EV_DECODE 6
925#define TX_PKT_NON_TCP_UDP_DECODE 9
926#define TIMER_EV_DECODE 10
927#define RX_RECOVERY_EV_DECODE 11
928#define RX_DSC_ERROR_EV_DECODE 14
929#define TX_DSC_ERROR_EV_DECODE 15
930#define DRIVER_EV_TX_DESCQ_ID_LBN 0
931#define DRIVER_EV_TX_DESCQ_ID_WIDTH 12
932#define DRIVER_EV_RX_FLUSH_FAIL_LBN 12
933#define DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
934#define DRIVER_EV_RX_DESCQ_ID_LBN 0
935#define DRIVER_EV_RX_DESCQ_ID_WIDTH 12
936#define SRM_CLR_EV_DECODE 0
937#define SRM_UPD_EV_DECODE 1
938#define SRM_ILLCLR_EV_DECODE 2
939
940/* Global events */
941#define RX_RECOVERY_B0_LBN 12
942#define RX_RECOVERY_B0_WIDTH 1
943#define XG_MNT_INTR_B0_LBN 11
944#define XG_MNT_INTR_B0_WIDTH 1
945#define RX_RECOVERY_A1_LBN 11
946#define RX_RECOVERY_A1_WIDTH 1
947#define XG_PHY_INTR_LBN 9
948#define XG_PHY_INTR_WIDTH 1
949#define G_PHY1_INTR_LBN 8
950#define G_PHY1_INTR_WIDTH 1
951#define G_PHY0_INTR_LBN 7
952#define G_PHY0_INTR_WIDTH 1
953
954/* Driver-generated test events */
955#define EVQ_MAGIC_LBN 0
956#define EVQ_MAGIC_WIDTH 32
957
958/**************************************************************************
959 *
960 * Falcon MAC stats
961 *
962 **************************************************************************
963 *
964 */
965#define GRxGoodOct_offset 0x0
966#define GRxBadOct_offset 0x8
967#define GRxMissPkt_offset 0x10
968#define GRxFalseCRS_offset 0x14
969#define GRxPausePkt_offset 0x18
970#define GRxBadPkt_offset 0x1C
971#define GRxUcastPkt_offset 0x20
972#define GRxMcastPkt_offset 0x24
973#define GRxBcastPkt_offset 0x28
974#define GRxGoodLt64Pkt_offset 0x2C
975#define GRxBadLt64Pkt_offset 0x30
976#define GRx64Pkt_offset 0x34
977#define GRx65to127Pkt_offset 0x38
978#define GRx128to255Pkt_offset 0x3C
979#define GRx256to511Pkt_offset 0x40
980#define GRx512to1023Pkt_offset 0x44
981#define GRx1024to15xxPkt_offset 0x48
982#define GRx15xxtoJumboPkt_offset 0x4C
983#define GRxGtJumboPkt_offset 0x50
984#define GRxFcsErr64to15xxPkt_offset 0x54
985#define GRxFcsErr15xxtoJumboPkt_offset 0x58
986#define GRxFcsErrGtJumboPkt_offset 0x5C
987#define GTxGoodBadOct_offset 0x80
988#define GTxGoodOct_offset 0x88
989#define GTxSglColPkt_offset 0x90
990#define GTxMultColPkt_offset 0x94
991#define GTxExColPkt_offset 0x98
992#define GTxDefPkt_offset 0x9C
993#define GTxLateCol_offset 0xA0
994#define GTxExDefPkt_offset 0xA4
995#define GTxPausePkt_offset 0xA8
996#define GTxBadPkt_offset 0xAC
997#define GTxUcastPkt_offset 0xB0
998#define GTxMcastPkt_offset 0xB4
999#define GTxBcastPkt_offset 0xB8
1000#define GTxLt64Pkt_offset 0xBC
1001#define GTx64Pkt_offset 0xC0
1002#define GTx65to127Pkt_offset 0xC4
1003#define GTx128to255Pkt_offset 0xC8
1004#define GTx256to511Pkt_offset 0xCC
1005#define GTx512to1023Pkt_offset 0xD0
1006#define GTx1024to15xxPkt_offset 0xD4
1007#define GTx15xxtoJumboPkt_offset 0xD8
1008#define GTxGtJumboPkt_offset 0xDC
1009#define GTxNonTcpUdpPkt_offset 0xE0
1010#define GTxMacSrcErrPkt_offset 0xE4
1011#define GTxIpSrcErrPkt_offset 0xE8
1012#define GDmaDone_offset 0xEC
1013
1014#define XgRxOctets_offset 0x0
1015#define XgRxOctets_WIDTH 48
1016#define XgRxOctetsOK_offset 0x8
1017#define XgRxOctetsOK_WIDTH 48
1018#define XgRxPkts_offset 0x10
1019#define XgRxPkts_WIDTH 32
1020#define XgRxPktsOK_offset 0x14
1021#define XgRxPktsOK_WIDTH 32
1022#define XgRxBroadcastPkts_offset 0x18
1023#define XgRxBroadcastPkts_WIDTH 32
1024#define XgRxMulticastPkts_offset 0x1C
1025#define XgRxMulticastPkts_WIDTH 32
1026#define XgRxUnicastPkts_offset 0x20
1027#define XgRxUnicastPkts_WIDTH 32
1028#define XgRxUndersizePkts_offset 0x24
1029#define XgRxUndersizePkts_WIDTH 32
1030#define XgRxOversizePkts_offset 0x28
1031#define XgRxOversizePkts_WIDTH 32
1032#define XgRxJabberPkts_offset 0x2C
1033#define XgRxJabberPkts_WIDTH 32
1034#define XgRxUndersizeFCSerrorPkts_offset 0x30
1035#define XgRxUndersizeFCSerrorPkts_WIDTH 32
1036#define XgRxDropEvents_offset 0x34
1037#define XgRxDropEvents_WIDTH 32
1038#define XgRxFCSerrorPkts_offset 0x38
1039#define XgRxFCSerrorPkts_WIDTH 32
1040#define XgRxAlignError_offset 0x3C
1041#define XgRxAlignError_WIDTH 32
1042#define XgRxSymbolError_offset 0x40
1043#define XgRxSymbolError_WIDTH 32
1044#define XgRxInternalMACError_offset 0x44
1045#define XgRxInternalMACError_WIDTH 32
1046#define XgRxControlPkts_offset 0x48
1047#define XgRxControlPkts_WIDTH 32
1048#define XgRxPausePkts_offset 0x4C
1049#define XgRxPausePkts_WIDTH 32
1050#define XgRxPkts64Octets_offset 0x50
1051#define XgRxPkts64Octets_WIDTH 32
1052#define XgRxPkts65to127Octets_offset 0x54
1053#define XgRxPkts65to127Octets_WIDTH 32
1054#define XgRxPkts128to255Octets_offset 0x58
1055#define XgRxPkts128to255Octets_WIDTH 32
1056#define XgRxPkts256to511Octets_offset 0x5C
1057#define XgRxPkts256to511Octets_WIDTH 32
1058#define XgRxPkts512to1023Octets_offset 0x60
1059#define XgRxPkts512to1023Octets_WIDTH 32
1060#define XgRxPkts1024to15xxOctets_offset 0x64
1061#define XgRxPkts1024to15xxOctets_WIDTH 32
1062#define XgRxPkts15xxtoMaxOctets_offset 0x68
1063#define XgRxPkts15xxtoMaxOctets_WIDTH 32
1064#define XgRxLengthError_offset 0x6C
1065#define XgRxLengthError_WIDTH 32
1066#define XgTxPkts_offset 0x80
1067#define XgTxPkts_WIDTH 32
1068#define XgTxOctets_offset 0x88
1069#define XgTxOctets_WIDTH 48
1070#define XgTxMulticastPkts_offset 0x90
1071#define XgTxMulticastPkts_WIDTH 32
1072#define XgTxBroadcastPkts_offset 0x94
1073#define XgTxBroadcastPkts_WIDTH 32
1074#define XgTxUnicastPkts_offset 0x98
1075#define XgTxUnicastPkts_WIDTH 32
1076#define XgTxControlPkts_offset 0x9C
1077#define XgTxControlPkts_WIDTH 32
1078#define XgTxPausePkts_offset 0xA0
1079#define XgTxPausePkts_WIDTH 32
1080#define XgTxPkts64Octets_offset 0xA4
1081#define XgTxPkts64Octets_WIDTH 32
1082#define XgTxPkts65to127Octets_offset 0xA8
1083#define XgTxPkts65to127Octets_WIDTH 32
1084#define XgTxPkts128to255Octets_offset 0xAC
1085#define XgTxPkts128to255Octets_WIDTH 32
1086#define XgTxPkts256to511Octets_offset 0xB0
1087#define XgTxPkts256to511Octets_WIDTH 32
1088#define XgTxPkts512to1023Octets_offset 0xB4
1089#define XgTxPkts512to1023Octets_WIDTH 32
1090#define XgTxPkts1024to15xxOctets_offset 0xB8
1091#define XgTxPkts1024to15xxOctets_WIDTH 32
1092#define XgTxPkts1519toMaxOctets_offset 0xBC
1093#define XgTxPkts1519toMaxOctets_WIDTH 32
1094#define XgTxUndersizePkts_offset 0xC0
1095#define XgTxUndersizePkts_WIDTH 32
1096#define XgTxOversizePkts_offset 0xC4
1097#define XgTxOversizePkts_WIDTH 32
1098#define XgTxNonTcpUdpPkt_offset 0xC8
1099#define XgTxNonTcpUdpPkt_WIDTH 16
1100#define XgTxMacSrcErrPkt_offset 0xCC
1101#define XgTxMacSrcErrPkt_WIDTH 16
1102#define XgTxIpSrcErrPkt_offset 0xD0
1103#define XgTxIpSrcErrPkt_WIDTH 16
1104#define XgDmaDone_offset 0xD4
1105
1106#define FALCON_STATS_NOT_DONE 0x00000000
1107#define FALCON_STATS_DONE 0xffffffff
1108
1109/* Interrupt status register bits */
1110#define FATAL_INT_LBN 64
1111#define FATAL_INT_WIDTH 1
1112#define INT_EVQS_LBN 40
1113#define INT_EVQS_WIDTH 4
1114
1115/**************************************************************************
1116 *
1117 * Falcon non-volatile configuration
1118 *
1119 **************************************************************************
1120 */
1121
1122/* Board configuration v2 (v1 is obsolete; later versions are compatible) */
1123struct falcon_nvconfig_board_v2 {
1124 __le16 nports;
1125 u8 port0_phy_addr;
1126 u8 port0_phy_type;
1127 u8 port1_phy_addr;
1128 u8 port1_phy_type;
1129 __le16 asic_sub_revision;
1130 __le16 board_revision;
Ben Hutchings24c28ed2008-05-16 21:19:21 +01001131} __packed;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001132
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001133/* Board configuration v3 extra information */
1134struct falcon_nvconfig_board_v3 {
1135 __le32 spi_device_type[2];
1136} __packed;
1137
1138/* Bit numbers for spi_device_type */
1139#define SPI_DEV_TYPE_SIZE_LBN 0
1140#define SPI_DEV_TYPE_SIZE_WIDTH 5
1141#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
1142#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
1143#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
1144#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
1145#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
1146#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
1147#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
1148#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
Ben Hutchingsa5150892008-09-01 12:48:55 +01001149#define SPI_DEV_TYPE_FIELD(type, field) \
1150 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001151
Ben Hutchings8c8661e2008-09-01 12:49:02 +01001152#define NVCONFIG_OFFSET 0x300
1153#define NVCONFIG_END 0x400
1154
Ben Hutchings8ceee662008-04-27 12:55:59 +01001155#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
1156struct falcon_nvconfig {
1157 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
1158 u8 mac_address[2][8]; /* 0x310 */
1159 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
1160 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
1161 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
1162 efx_oword_t hw_init_reg; /* 0x350 */
1163 efx_oword_t nic_stat_reg; /* 0x360 */
1164 efx_oword_t glb_ctl_reg; /* 0x370 */
1165 efx_oword_t srm_cfg_reg; /* 0x380 */
1166 efx_oword_t spare_reg; /* 0x390 */
1167 __le16 board_magic_num; /* 0x3A0 */
1168 __le16 board_struct_ver;
1169 __le16 board_checksum;
1170 struct falcon_nvconfig_board_v2 board_v2;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001171 efx_oword_t ee_base_page_reg; /* 0x3B0 */
1172 struct falcon_nvconfig_board_v3 board_v3;
Ben Hutchings24c28ed2008-05-16 21:19:21 +01001173} __packed;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001174
1175#endif /* EFX_FALCON_HWDEFS_H */