Michael Wu | eff1a59 | 2007-09-25 18:11:01 -0700 | [diff] [blame] | 1 | #ifndef PRISM54COMMON_H |
| 2 | #define PRISM54COMMON_H |
| 3 | |
| 4 | /* |
| 5 | * Common code specific definitions for mac80211 Prism54 drivers |
| 6 | * |
| 7 | * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> |
| 8 | * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de> |
| 9 | * |
| 10 | * Based on the islsm (softmac prism54) driver, which is: |
| 11 | * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | |
| 18 | struct bootrec { |
| 19 | __le32 code; |
| 20 | __le32 len; |
| 21 | u32 data[0]; |
| 22 | } __attribute__((packed)); |
| 23 | |
| 24 | struct bootrec_exp_if { |
| 25 | __le16 role; |
| 26 | __le16 if_id; |
| 27 | __le16 variant; |
| 28 | __le16 btm_compat; |
| 29 | __le16 top_compat; |
| 30 | } __attribute__((packed)); |
| 31 | |
| 32 | #define BR_CODE_MIN 0x80000000 |
| 33 | #define BR_CODE_COMPONENT_ID 0x80000001 |
| 34 | #define BR_CODE_COMPONENT_VERSION 0x80000002 |
| 35 | #define BR_CODE_DEPENDENT_IF 0x80000003 |
| 36 | #define BR_CODE_EXPOSED_IF 0x80000004 |
| 37 | #define BR_CODE_DESCR 0x80000101 |
| 38 | #define BR_CODE_MAX 0x8FFFFFFF |
| 39 | #define BR_CODE_END_OF_BRA 0xFF0000FF |
| 40 | #define LEGACY_BR_CODE_END_OF_BRA 0xFFFFFFFF |
| 41 | |
| 42 | #define FW_FMAC 0x464d4143 |
| 43 | #define FW_LM86 0x4c4d3836 |
| 44 | #define FW_LM87 0x4c4d3837 |
| 45 | #define FW_LM20 0x4c4d3230 |
| 46 | |
| 47 | /* PDA defines are Copyright (C) 2005 Nokia Corporation (taken from islsm_pda.h) */ |
| 48 | |
| 49 | struct pda_entry { |
| 50 | __le16 len; /* includes both code and data */ |
| 51 | __le16 code; |
| 52 | u8 data[0]; |
| 53 | } __attribute__ ((packed)); |
| 54 | |
| 55 | struct eeprom_pda_wrap { |
Johannes Berg | 8c28293 | 2008-02-29 13:56:33 +0100 | [diff] [blame] | 56 | __le32 magic; |
| 57 | __le16 pad; |
| 58 | __le16 len; |
| 59 | __le32 arm_opcode; |
Michael Wu | eff1a59 | 2007-09-25 18:11:01 -0700 | [diff] [blame] | 60 | u8 data[0]; |
| 61 | } __attribute__ ((packed)); |
| 62 | |
| 63 | struct pda_iq_autocal_entry { |
| 64 | __le16 freq; |
| 65 | __le16 iq_param[4]; |
| 66 | } __attribute__ ((packed)); |
| 67 | |
| 68 | struct pda_channel_output_limit { |
| 69 | __le16 freq; |
| 70 | u8 val_bpsk; |
| 71 | u8 val_qpsk; |
| 72 | u8 val_16qam; |
| 73 | u8 val_64qam; |
| 74 | u8 rate_set_mask; |
| 75 | u8 rate_set_size; |
| 76 | } __attribute__ ((packed)); |
| 77 | |
| 78 | struct pda_pa_curve_data_sample_rev0 { |
| 79 | u8 rf_power; |
| 80 | u8 pa_detector; |
| 81 | u8 pcv; |
| 82 | } __attribute__ ((packed)); |
| 83 | |
| 84 | struct pda_pa_curve_data_sample_rev1 { |
| 85 | u8 rf_power; |
| 86 | u8 pa_detector; |
| 87 | u8 data_barker; |
| 88 | u8 data_bpsk; |
| 89 | u8 data_qpsk; |
| 90 | u8 data_16qam; |
| 91 | u8 data_64qam; |
| 92 | u8 padding; |
| 93 | } __attribute__ ((packed)); |
| 94 | |
| 95 | struct pda_pa_curve_data { |
| 96 | u8 cal_method_rev; |
| 97 | u8 channels; |
| 98 | u8 points_per_channel; |
| 99 | u8 padding; |
| 100 | u8 data[0]; |
| 101 | } __attribute__ ((packed)); |
| 102 | |
| 103 | /* |
| 104 | * this defines the PDR codes used to build PDAs as defined in document |
| 105 | * number 553155. The current implementation mirrors version 1.1 of the |
| 106 | * document and lists only PDRs supported by the ARM platform. |
| 107 | */ |
| 108 | |
| 109 | /* common and choice range (0x0000 - 0x0fff) */ |
| 110 | #define PDR_END 0x0000 |
| 111 | #define PDR_MANUFACTURING_PART_NUMBER 0x0001 |
| 112 | #define PDR_PDA_VERSION 0x0002 |
| 113 | #define PDR_NIC_SERIAL_NUMBER 0x0003 |
| 114 | |
| 115 | #define PDR_MAC_ADDRESS 0x0101 |
| 116 | #define PDR_REGULATORY_DOMAIN_LIST 0x0103 |
| 117 | #define PDR_TEMPERATURE_TYPE 0x0107 |
| 118 | |
| 119 | #define PDR_PRISM_PCI_IDENTIFIER 0x0402 |
| 120 | |
| 121 | /* ARM range (0x1000 - 0x1fff) */ |
| 122 | #define PDR_COUNTRY_INFORMATION 0x1000 |
| 123 | #define PDR_INTERFACE_LIST 0x1001 |
| 124 | #define PDR_HARDWARE_PLATFORM_COMPONENT_ID 0x1002 |
| 125 | #define PDR_OEM_NAME 0x1003 |
| 126 | #define PDR_PRODUCT_NAME 0x1004 |
| 127 | #define PDR_UTF8_OEM_NAME 0x1005 |
| 128 | #define PDR_UTF8_PRODUCT_NAME 0x1006 |
| 129 | #define PDR_COUNTRY_LIST 0x1007 |
| 130 | #define PDR_DEFAULT_COUNTRY 0x1008 |
| 131 | |
| 132 | #define PDR_ANTENNA_GAIN 0x1100 |
| 133 | |
| 134 | #define PDR_PRISM_INDIGO_PA_CALIBRATION_DATA 0x1901 |
| 135 | #define PDR_RSSI_LINEAR_APPROXIMATION 0x1902 |
| 136 | #define PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS 0x1903 |
| 137 | #define PDR_PRISM_PA_CAL_CURVE_DATA 0x1904 |
| 138 | #define PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND 0x1905 |
| 139 | #define PDR_PRISM_ZIF_TX_IQ_CALIBRATION 0x1906 |
| 140 | #define PDR_REGULATORY_POWER_LIMITS 0x1907 |
| 141 | #define PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED 0x1908 |
| 142 | #define PDR_RADIATED_TRANSMISSION_CORRECTION 0x1909 |
| 143 | #define PDR_PRISM_TX_IQ_CALIBRATION 0x190a |
| 144 | |
| 145 | /* reserved range (0x2000 - 0x7fff) */ |
| 146 | |
| 147 | /* customer range (0x8000 - 0xffff) */ |
| 148 | #define PDR_BASEBAND_REGISTERS 0x8000 |
| 149 | #define PDR_PER_CHANNEL_BASEBAND_REGISTERS 0x8001 |
| 150 | |
| 151 | /* stored in skb->cb */ |
| 152 | struct memrecord { |
| 153 | u32 start_addr; |
| 154 | u32 end_addr; |
Michael Wu | eff1a59 | 2007-09-25 18:11:01 -0700 | [diff] [blame] | 155 | }; |
| 156 | |
| 157 | struct p54_eeprom_lm86 { |
| 158 | __le16 offset; |
| 159 | __le16 len; |
| 160 | u8 data[0]; |
| 161 | } __attribute__ ((packed)); |
| 162 | |
| 163 | struct p54_rx_hdr { |
| 164 | __le16 magic; |
| 165 | __le16 len; |
| 166 | __le16 freq; |
| 167 | u8 antenna; |
| 168 | u8 rate; |
| 169 | u8 rssi; |
| 170 | u8 quality; |
| 171 | u16 unknown2; |
| 172 | __le64 timestamp; |
| 173 | u8 data[0]; |
| 174 | } __attribute__ ((packed)); |
| 175 | |
| 176 | struct p54_frame_sent_hdr { |
| 177 | u8 status; |
| 178 | u8 retries; |
| 179 | __le16 ack_rssi; |
| 180 | __le16 seq; |
| 181 | u16 rate; |
| 182 | } __attribute__ ((packed)); |
| 183 | |
| 184 | struct p54_tx_control_allocdata { |
| 185 | u8 rateset[8]; |
| 186 | u16 padding; |
| 187 | u8 wep_key_present; |
| 188 | u8 wep_key_len; |
| 189 | u8 wep_key[16]; |
| 190 | __le32 frame_type; |
| 191 | u32 padding2; |
| 192 | __le16 magic4; |
| 193 | u8 antenna; |
| 194 | u8 output_power; |
| 195 | __le32 magic5; |
| 196 | u8 align[0]; |
| 197 | } __attribute__ ((packed)); |
| 198 | |
| 199 | struct p54_tx_control_filter { |
| 200 | __le16 filter_type; |
| 201 | u8 dst[ETH_ALEN]; |
| 202 | u8 src[ETH_ALEN]; |
| 203 | u8 antenna; |
| 204 | u8 debug; |
| 205 | __le32 magic3; |
| 206 | u8 rates[8]; // FIXME: what's this for? |
| 207 | __le32 rx_addr; |
| 208 | __le16 max_rx; |
| 209 | __le16 rxhw; |
| 210 | __le16 magic8; |
| 211 | __le16 magic9; |
| 212 | } __attribute__ ((packed)); |
| 213 | |
| 214 | struct p54_tx_control_channel { |
| 215 | __le16 magic1; |
| 216 | __le16 magic2; |
| 217 | u8 padding1[20]; |
| 218 | struct pda_iq_autocal_entry iq_autocal; |
| 219 | u8 pa_points_per_curve; |
| 220 | u8 val_barker; |
| 221 | u8 val_bpsk; |
| 222 | u8 val_qpsk; |
| 223 | u8 val_16qam; |
| 224 | u8 val_64qam; |
| 225 | struct pda_pa_curve_data_sample_rev1 curve_data[0]; |
| 226 | /* additional padding/data after curve_data */ |
| 227 | } __attribute__ ((packed)); |
| 228 | |
| 229 | struct p54_tx_control_led { |
| 230 | __le16 mode; |
| 231 | __le16 led_temporary; |
| 232 | __le16 led_permanent; |
| 233 | __le16 duration; |
| 234 | } __attribute__ ((packed)); |
| 235 | |
| 236 | struct p54_tx_vdcf_queues { |
| 237 | __le16 aifs; |
| 238 | __le16 cwmin; |
| 239 | __le16 cwmax; |
| 240 | __le16 txop; |
| 241 | } __attribute__ ((packed)); |
| 242 | |
| 243 | struct p54_tx_control_vdcf { |
| 244 | u8 padding; |
| 245 | u8 slottime; |
| 246 | u8 magic1; |
| 247 | u8 magic2; |
| 248 | struct p54_tx_vdcf_queues queue[8]; |
| 249 | u8 pad2[4]; |
| 250 | __le16 frameburst; |
| 251 | } __attribute__ ((packed)); |
| 252 | |
Michael Wu | eff1a59 | 2007-09-25 18:11:01 -0700 | [diff] [blame] | 253 | #endif /* PRISM54COMMON_H */ |