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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2003-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * Copyright 2003 Benjamin Herrenschmidt
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 *
Jeff Garzik953d1132005-08-26 19:46:24 -040030 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
46#include <linux/libata.h>
47
48#define DRV_NAME "sata_sil"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040049#define DRV_VERSION "2.3"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090052 SIL_MMIO_BAR = 5,
53
Tejun Heoe653a1e2006-03-05 16:03:52 +090054 /*
55 * host flags
56 */
Tejun Heo201ce852006-06-26 21:23:52 +090057 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
Tejun Heoe4e10e32006-02-25 13:52:30 +090058 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
Tejun Heoe4deec62005-08-23 07:27:25 +090059 SIL_FLAG_MOD15WRITE = (1 << 30),
Tejun Heo20888d82006-05-31 18:27:53 +090060
Jeff Garzikcca39742006-08-24 03:19:22 -040061 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo0c887582007-08-06 18:36:23 +090062 ATA_FLAG_MMIO,
Tejun Heoe4deec62005-08-23 07:27:25 +090063
Tejun Heoe653a1e2006-03-05 16:03:52 +090064 /*
65 * Controller IDs
66 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 sil_3112 = 0,
Tejun Heo201ce852006-06-26 21:23:52 +090068 sil_3112_no_sata_irq = 1,
69 sil_3512 = 2,
70 sil_3114 = 3,
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Tejun Heoe653a1e2006-03-05 16:03:52 +090072 /*
73 * Register offsets
74 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 SIL_SYSCFG = 0x48,
Tejun Heoe653a1e2006-03-05 16:03:52 +090076
77 /*
78 * Register bits
79 */
80 /* SYSCFG */
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 SIL_MASK_IDE0_INT = (1 << 22),
82 SIL_MASK_IDE1_INT = (1 << 23),
83 SIL_MASK_IDE2_INT = (1 << 24),
84 SIL_MASK_IDE3_INT = (1 << 25),
85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 SIL_MASK_4PORT = SIL_MASK_2PORT |
87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88
Tejun Heoe653a1e2006-03-05 16:03:52 +090089 /* BMDMA/BMDMA2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 SIL_INTR_STEERING = (1 << 1),
Tejun Heoe653a1e2006-03-05 16:03:52 +090091
Tejun Heo20888d82006-05-31 18:27:53 +090092 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
102
103 /* SIEN */
104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
105
Tejun Heoe653a1e2006-03-05 16:03:52 +0900106 /*
107 * Others
108 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 SIL_QUIRK_MOD15WRITE = (1 << 0),
110 SIL_QUIRK_UDMA5MAX = (1 << 1),
111};
112
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400113static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700114#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900115static int sil_pci_device_resume(struct pci_dev *pdev);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700116#endif
Alancd0d3bb2007-03-02 00:56:15 +0000117static void sil_dev_config(struct ata_device *dev);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900118static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
119static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
Tejun Heo02607312007-08-06 18:36:23 +0900120static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
Tejun Heof6aae272006-05-15 20:58:27 +0900121static void sil_freeze(struct ata_port *ap);
122static void sil_thaw(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
Jeff Garzik374b1872005-08-30 05:42:52 -0400124
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500125static const struct pci_device_id sil_pci_tbl[] = {
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400126 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
127 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
129 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
130 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
131 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
132 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
133
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 { } /* terminate list */
135};
136
137
138/* TODO firmware versions should be added - eric */
139static const struct sil_drivelist {
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400140 const char *product;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 unsigned int quirk;
142} sil_blacklist [] = {
143 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
144 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
145 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
146 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
148 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
150 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
154 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
155 { }
156};
157
158static struct pci_driver sil_pci_driver = {
159 .name = DRV_NAME,
160 .id_table = sil_pci_tbl,
161 .probe = sil_init_one,
162 .remove = ata_pci_remove_one,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700163#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900164 .suspend = ata_pci_device_suspend,
165 .resume = sil_pci_device_resume,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700166#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167};
168
Jeff Garzik193515d2005-11-07 00:59:37 -0500169static struct scsi_host_template sil_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900170 ATA_BMDMA_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171};
172
Tejun Heo029cfd62008-03-25 12:22:49 +0900173static struct ata_port_operations sil_ops = {
174 .inherits = &ata_bmdma_port_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 .dev_config = sil_dev_config,
Alan Cox9d2c7c72007-03-08 23:09:12 +0000176 .set_mode = sil_set_mode,
Tejun Heof6aae272006-05-15 20:58:27 +0900177 .freeze = sil_freeze,
178 .thaw = sil_thaw,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 .scr_read = sil_scr_read,
180 .scr_write = sil_scr_write,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181};
182
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100183static const struct ata_port_info sil_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 /* sil_3112 */
185 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400186 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
Tejun Heoe4deec62005-08-23 07:27:25 +0900187 .pio_mask = 0x1f, /* pio0-4 */
188 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400189 .udma_mask = ATA_UDMA5,
Tejun Heoe4deec62005-08-23 07:27:25 +0900190 .port_ops = &sil_ops,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900191 },
Tejun Heo201ce852006-06-26 21:23:52 +0900192 /* sil_3112_no_sata_irq */
193 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400194 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
Tejun Heo201ce852006-06-26 21:23:52 +0900195 SIL_FLAG_NO_SATA_IRQ,
196 .pio_mask = 0x1f, /* pio0-4 */
197 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400198 .udma_mask = ATA_UDMA5,
Tejun Heo201ce852006-06-26 21:23:52 +0900199 .port_ops = &sil_ops,
200 },
Tejun Heo0ee304d2006-02-25 13:52:30 +0900201 /* sil_3512 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400203 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900204 .pio_mask = 0x1f, /* pio0-4 */
205 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400206 .udma_mask = ATA_UDMA5,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900207 .port_ops = &sil_ops,
208 },
209 /* sil_3114 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400211 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 .pio_mask = 0x1f, /* pio0-4 */
213 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400214 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 .port_ops = &sil_ops,
216 },
217};
218
219/* per-port register offsets */
220/* TODO: we can probably calculate rather than use a table */
221static const struct {
222 unsigned long tf; /* ATA taskfile register block */
223 unsigned long ctl; /* ATA control/altstatus register block */
224 unsigned long bmdma; /* DMA register block */
Tejun Heo20888d82006-05-31 18:27:53 +0900225 unsigned long bmdma2; /* DMA register block #2 */
Tejun Heo48d4ef22006-03-05 16:03:52 +0900226 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227 unsigned long scr; /* SATA control register block */
228 unsigned long sien; /* SATA Interrupt Enable register */
229 unsigned long xfer_mode;/* data transfer mode register */
Tejun Heoe4e10e32006-02-25 13:52:30 +0900230 unsigned long sfis_cfg; /* SATA FIS reception config register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231} sil_port[] = {
232 /* port 0 ... */
Jeff Garzik5bcd7a002007-05-26 16:35:42 -0400233 /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
234 { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
235 { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
Tejun Heo20888d82006-05-31 18:27:53 +0900236 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
237 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 /* ... port 3 */
239};
240
241MODULE_AUTHOR("Jeff Garzik");
242MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
243MODULE_LICENSE("GPL");
244MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
245MODULE_VERSION(DRV_VERSION);
246
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400247static int slow_down;
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500248module_param(slow_down, int, 0444);
249MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
250
Jeff Garzik374b1872005-08-30 05:42:52 -0400251
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
253{
254 u8 cache_line = 0;
255 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
256 return cache_line;
257}
258
Alan Cox9d2c7c72007-03-08 23:09:12 +0000259/**
260 * sil_set_mode - wrap set_mode functions
Tejun Heo02607312007-08-06 18:36:23 +0900261 * @link: link to set up
Alan Cox9d2c7c72007-03-08 23:09:12 +0000262 * @r_failed: returned device when we fail
263 *
264 * Wrap the libata method for device setup as after the setup we need
265 * to inspect the results and do some configuration work
266 */
267
Tejun Heo02607312007-08-06 18:36:23 +0900268static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269{
Tejun Heo02607312007-08-06 18:36:23 +0900270 struct ata_port *ap = link->ap;
271 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heo0d5ff562007-02-01 15:06:36 +0900272 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
Tejun Heo02607312007-08-06 18:36:23 +0900273 struct ata_device *dev;
Tejun Heof58229f2007-08-06 18:36:23 +0900274 u32 tmp, dev_mode[2] = { };
Alan Cox9d2c7c72007-03-08 23:09:12 +0000275 int rc;
Jeff Garzika617c092007-05-21 20:14:23 -0400276
Tejun Heo02607312007-08-06 18:36:23 +0900277 rc = ata_do_set_mode(link, r_failed);
Alan Cox9d2c7c72007-03-08 23:09:12 +0000278 if (rc)
279 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280
Tejun Heo02607312007-08-06 18:36:23 +0900281 ata_link_for_each_dev(dev, link) {
Tejun Heoe1211e32006-04-01 01:38:18 +0900282 if (!ata_dev_enabled(dev))
Tejun Heof58229f2007-08-06 18:36:23 +0900283 dev_mode[dev->devno] = 0; /* PIO0/1/2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284 else if (dev->flags & ATA_DFLAG_PIO)
Tejun Heof58229f2007-08-06 18:36:23 +0900285 dev_mode[dev->devno] = 1; /* PIO3/4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 else
Tejun Heof58229f2007-08-06 18:36:23 +0900287 dev_mode[dev->devno] = 3; /* UDMA */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 /* value 2 indicates MDMA */
289 }
290
291 tmp = readl(addr);
292 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
293 tmp |= dev_mode[0];
294 tmp |= (dev_mode[1] << 4);
295 writel(tmp, addr);
296 readl(addr); /* flush */
Alan Cox9d2c7c72007-03-08 23:09:12 +0000297 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298}
299
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400300static inline void __iomem *sil_scr_addr(struct ata_port *ap,
301 unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900303 void __iomem *offset = ap->ioaddr.scr_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
305 switch (sc_reg) {
306 case SCR_STATUS:
307 return offset + 4;
308 case SCR_ERROR:
309 return offset + 8;
310 case SCR_CONTROL:
311 return offset;
312 default:
313 /* do nothing */
314 break;
315 }
316
Randy Dunlap8d9db2d2007-02-16 01:40:06 -0800317 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318}
319
Tejun Heoda3dbb12007-07-16 14:29:40 +0900320static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900322 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900323
324 if (mmio) {
325 *val = readl(mmio);
326 return 0;
327 }
328 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329}
330
Tejun Heoda3dbb12007-07-16 14:29:40 +0900331static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900333 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900334
335 if (mmio) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 writel(val, mmio);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900337 return 0;
338 }
339 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340}
341
Tejun Heocbe88fb2006-05-31 18:27:55 +0900342static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
343{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900344 struct ata_eh_info *ehi = &ap->link.eh_info;
345 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900346 u8 status;
347
Tejun Heoe5738902006-05-31 18:28:16 +0900348 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
Tejun Heod4c85322006-06-12 18:45:55 +0900349 u32 serror;
350
351 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
352 * controllers continue to assert IRQ as long as
353 * SError bits are pending. Clear SError immediately.
354 */
Tejun Heoda3dbb12007-07-16 14:29:40 +0900355 sil_scr_read(ap, SCR_ERROR, &serror);
Tejun Heod4c85322006-06-12 18:45:55 +0900356 sil_scr_write(ap, SCR_ERROR, serror);
357
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900358 /* Sometimes spurious interrupts occur, double check
359 * it's PHYRDY CHG.
Tejun Heod4c85322006-06-12 18:45:55 +0900360 */
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900361 if (serror & SERR_PHYRDY_CHG) {
Tejun Heof7fe7ad2007-12-08 08:47:01 +0900362 ap->link.eh_info.serror |= serror;
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900363 goto freeze;
Tejun Heod4c85322006-06-12 18:45:55 +0900364 }
365
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900366 if (!(bmdma2 & SIL_DMA_COMPLETE))
367 return;
Tejun Heoe5738902006-05-31 18:28:16 +0900368 }
369
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900370 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900371 /* this sometimes happens, just clear IRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900372 ap->ops->sff_check_status(ap);
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900373 return;
374 }
375
Tejun Heocbe88fb2006-05-31 18:27:55 +0900376 /* Check whether we are expecting interrupt in this state */
377 switch (ap->hsm_task_state) {
378 case HSM_ST_FIRST:
379 /* Some pre-ATAPI-4 devices assert INTRQ
380 * at this state when ready to receive CDB.
381 */
382
383 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
Tejun Heo405e66b2007-11-27 19:28:53 +0900384 * The flag was turned on only for atapi devices. No
385 * need to check ata_is_atapi(qc->tf.protocol) again.
Tejun Heocbe88fb2006-05-31 18:27:55 +0900386 */
387 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
388 goto err_hsm;
389 break;
390 case HSM_ST_LAST:
Tejun Heo405e66b2007-11-27 19:28:53 +0900391 if (ata_is_dma(qc->tf.protocol)) {
Tejun Heocbe88fb2006-05-31 18:27:55 +0900392 /* clear DMA-Start bit */
393 ap->ops->bmdma_stop(qc);
394
395 if (bmdma2 & SIL_DMA_ERROR) {
396 qc->err_mask |= AC_ERR_HOST_BUS;
397 ap->hsm_task_state = HSM_ST_ERR;
398 }
399 }
400 break;
401 case HSM_ST:
402 break;
403 default:
404 goto err_hsm;
405 }
406
407 /* check main status, clearing INTRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900408 status = ap->ops->sff_check_status(ap);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900409 if (unlikely(status & ATA_BUSY))
410 goto err_hsm;
411
412 /* ack bmdma irq events */
Tejun Heo9363c382008-04-07 22:47:16 +0900413 ata_sff_irq_clear(ap);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900414
415 /* kick HSM in the ass */
Tejun Heo9363c382008-04-07 22:47:16 +0900416 ata_sff_hsm_move(ap, qc, status, 0);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900417
Tejun Heo405e66b2007-11-27 19:28:53 +0900418 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
Tejun Heoea547632006-11-17 12:06:21 +0900419 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
420
Tejun Heocbe88fb2006-05-31 18:27:55 +0900421 return;
422
423 err_hsm:
424 qc->err_mask |= AC_ERR_HSM;
425 freeze:
426 ata_port_freeze(ap);
427}
428
David Howells7d12e782006-10-05 14:55:46 +0100429static irqreturn_t sil_interrupt(int irq, void *dev_instance)
Tejun Heocbe88fb2006-05-31 18:27:55 +0900430{
Jeff Garzikcca39742006-08-24 03:19:22 -0400431 struct ata_host *host = dev_instance;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900432 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900433 int handled = 0;
434 int i;
435
Jeff Garzikcca39742006-08-24 03:19:22 -0400436 spin_lock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900437
Jeff Garzikcca39742006-08-24 03:19:22 -0400438 for (i = 0; i < host->n_ports; i++) {
439 struct ata_port *ap = host->ports[i];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900440 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
441
442 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
443 continue;
444
Tejun Heo201ce852006-06-26 21:23:52 +0900445 /* turn off SATA_IRQ if not supported */
446 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
447 bmdma2 &= ~SIL_DMA_SATA_IRQ;
448
Tejun Heo23fa9612006-06-12 14:18:51 +0900449 if (bmdma2 == 0xffffffff ||
450 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900451 continue;
452
453 sil_host_intr(ap, bmdma2);
454 handled = 1;
455 }
456
Jeff Garzikcca39742006-08-24 03:19:22 -0400457 spin_unlock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900458
459 return IRQ_RETVAL(handled);
460}
461
Tejun Heof6aae272006-05-15 20:58:27 +0900462static void sil_freeze(struct ata_port *ap)
463{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900464 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900465 u32 tmp;
466
Tejun Heoe5738902006-05-31 18:28:16 +0900467 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
468 writel(0, mmio_base + sil_port[ap->port_no].sien);
469
Tejun Heof6aae272006-05-15 20:58:27 +0900470 /* plug IRQ */
471 tmp = readl(mmio_base + SIL_SYSCFG);
472 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
473 writel(tmp, mmio_base + SIL_SYSCFG);
474 readl(mmio_base + SIL_SYSCFG); /* flush */
475}
476
477static void sil_thaw(struct ata_port *ap)
478{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900479 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900480 u32 tmp;
481
482 /* clear IRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900483 ap->ops->sff_check_status(ap);
Tejun Heo9363c382008-04-07 22:47:16 +0900484 ata_sff_irq_clear(ap);
Tejun Heof6aae272006-05-15 20:58:27 +0900485
Tejun Heo201ce852006-06-26 21:23:52 +0900486 /* turn on SATA IRQ if supported */
487 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
488 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
Tejun Heoe5738902006-05-31 18:28:16 +0900489
Tejun Heof6aae272006-05-15 20:58:27 +0900490 /* turn on IRQ */
491 tmp = readl(mmio_base + SIL_SYSCFG);
492 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
493 writel(tmp, mmio_base + SIL_SYSCFG);
494}
495
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496/**
497 * sil_dev_config - Apply device/host-specific errata fixups
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498 * @dev: Device to be examined
499 *
500 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
501 * device is known to be present, this function is called.
502 * We apply two errata fixups which are specific to Silicon Image,
503 * a Seagate and a Maxtor fixup.
504 *
505 * For certain Seagate devices, we must limit the maximum sectors
506 * to under 8K.
507 *
508 * For certain Maxtor devices, we must not program the drive
509 * beyond udma5.
510 *
511 * Both fixups are unfairly pessimistic. As soon as I get more
512 * information on these errata, I will create a more exhaustive
513 * list, and apply the fixups to only the specific
514 * devices/hosts/firmwares that need it.
515 *
516 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
517 * The Maxtor quirk is in the blacklist, but I'm keeping the original
518 * pessimistic fix for the following reasons...
519 * - There seems to be less info on it, only one device gleaned off the
520 * Windows driver, maybe only one is affected. More info would be greatly
521 * appreciated.
522 * - But then again UDMA5 is hardly anything to complain about
523 */
Alancd0d3bb2007-03-02 00:56:15 +0000524static void sil_dev_config(struct ata_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900526 struct ata_port *ap = dev->link->ap;
527 int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 unsigned int n, quirks = 0;
Tejun Heoa0cf7332007-01-02 20:18:49 +0900529 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530
Tejun Heoa0cf7332007-01-02 20:18:49 +0900531 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532
Jeff Garzik8a60a072005-07-31 13:13:24 -0400533 for (n = 0; sil_blacklist[n].product; n++)
Tejun Heo2e026712006-02-12 22:47:04 +0900534 if (!strcmp(sil_blacklist[n].product, model_num)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535 quirks = sil_blacklist[n].quirk;
536 break;
537 }
Jeff Garzik8a60a072005-07-31 13:13:24 -0400538
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539 /* limit requests to 15 sectors */
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500540 if (slow_down ||
541 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
542 (quirks & SIL_QUIRK_MOD15WRITE))) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900543 if (print_info)
544 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
545 "errata fix (mod15write workaround)\n");
Tejun Heob00eec12006-02-12 23:32:59 +0900546 dev->max_sectors = 15;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 return;
548 }
549
550 /* limit to udma5 */
551 if (quirks & SIL_QUIRK_UDMA5MAX) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900552 if (print_info)
553 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
554 "errata fix %s\n", model_num);
Tejun Heo5a529132006-03-24 14:07:50 +0900555 dev->udma_mask &= ATA_UDMA5;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 return;
557 }
558}
559
Tejun Heo4447d352007-04-17 23:44:08 +0900560static void sil_init_controller(struct ata_host *host)
Tejun Heo3d8ec912006-07-03 16:07:27 +0900561{
Tejun Heo4447d352007-04-17 23:44:08 +0900562 struct pci_dev *pdev = to_pci_dev(host->dev);
563 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heo3d8ec912006-07-03 16:07:27 +0900564 u8 cls;
565 u32 tmp;
566 int i;
567
568 /* Initialize FIFO PCI bus arbitration */
569 cls = sil_get_device_cache_line(pdev);
570 if (cls) {
571 cls >>= 3;
572 cls++; /* cls = (line_size/8)+1 */
Tejun Heo4447d352007-04-17 23:44:08 +0900573 for (i = 0; i < host->n_ports; i++)
Tejun Heo3d8ec912006-07-03 16:07:27 +0900574 writew(cls << 8 | cls,
575 mmio_base + sil_port[i].fifo_cfg);
576 } else
577 dev_printk(KERN_WARNING, &pdev->dev,
578 "cache line size not set. Driver may not function\n");
579
580 /* Apply R_ERR on DMA activate FIS errata workaround */
Tejun Heo4447d352007-04-17 23:44:08 +0900581 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900582 int cnt;
583
Tejun Heo4447d352007-04-17 23:44:08 +0900584 for (i = 0, cnt = 0; i < host->n_ports; i++) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900585 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
586 if ((tmp & 0x3) != 0x01)
587 continue;
588 if (!cnt)
589 dev_printk(KERN_INFO, &pdev->dev,
590 "Applying R_ERR on DMA activate "
591 "FIS errata fix\n");
592 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
593 cnt++;
594 }
595 }
596
Tejun Heo4447d352007-04-17 23:44:08 +0900597 if (host->n_ports == 4) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900598 /* flip the magic "make 4 ports work" bit */
599 tmp = readl(mmio_base + sil_port[2].bmdma);
600 if ((tmp & SIL_INTR_STEERING) == 0)
601 writel(tmp | SIL_INTR_STEERING,
602 mmio_base + sil_port[2].bmdma);
603 }
604}
605
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400606static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607{
608 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +0900609 int board_id = ent->driver_data;
610 const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
611 struct ata_host *host;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400612 void __iomem *mmio_base;
Tejun Heo4447d352007-04-17 23:44:08 +0900613 int n_ports, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615
616 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500617 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618
Tejun Heo4447d352007-04-17 23:44:08 +0900619 /* allocate host */
620 n_ports = 2;
621 if (board_id == sil_3114)
622 n_ports = 4;
623
624 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
625 if (!host)
626 return -ENOMEM;
627
628 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900629 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630 if (rc)
631 return rc;
632
Tejun Heo0d5ff562007-02-01 15:06:36 +0900633 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
634 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900635 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900636 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900637 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +0900638 host->iomap = pcim_iomap_table(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639
640 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
641 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900642 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
644 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900645 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646
Tejun Heo4447d352007-04-17 23:44:08 +0900647 mmio_base = host->iomap[SIL_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648
Tejun Heo4447d352007-04-17 23:44:08 +0900649 for (i = 0; i < host->n_ports; i++) {
Tejun Heocbcdd872007-08-18 13:14:55 +0900650 struct ata_port *ap = host->ports[i];
651 struct ata_ioports *ioaddr = &ap->ioaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652
Tejun Heo4447d352007-04-17 23:44:08 +0900653 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
654 ioaddr->altstatus_addr =
655 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
656 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
657 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
Tejun Heo9363c382008-04-07 22:47:16 +0900658 ata_sff_std_ports(ioaddr);
Tejun Heocbcdd872007-08-18 13:14:55 +0900659
660 ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
661 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 }
663
Tejun Heo4447d352007-04-17 23:44:08 +0900664 /* initialize and activate */
665 sil_init_controller(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667 pci_set_master(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +0900668 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
669 &sil_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670}
671
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700672#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900673static int sil_pci_device_resume(struct pci_dev *pdev)
674{
Jeff Garzikcca39742006-08-24 03:19:22 -0400675 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo553c4aa2006-12-26 19:39:50 +0900676 int rc;
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900677
Tejun Heo553c4aa2006-12-26 19:39:50 +0900678 rc = ata_pci_device_do_resume(pdev);
679 if (rc)
680 return rc;
681
Tejun Heo4447d352007-04-17 23:44:08 +0900682 sil_init_controller(host);
Jeff Garzikcca39742006-08-24 03:19:22 -0400683 ata_host_resume(host);
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900684
685 return 0;
686}
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700687#endif
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900688
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689static int __init sil_init(void)
690{
Pavel Roskinb7887192006-08-10 18:13:18 +0900691 return pci_register_driver(&sil_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692}
693
694static void __exit sil_exit(void)
695{
696 pci_unregister_driver(&sil_pci_driver);
697}
698
699
700module_init(sil_init);
701module_exit(sil_exit);