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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 583553b28c8073b9c88316c1a01de4591af0d425 / . / arch / arm / boot / dts / tegra20.dtsi
blob: d2bc7e7ad06df7f6d1073b7812ee69d2d1c26412 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Stephen Warrend17adfd2012-01-25 14:43:27 -0700[diff] [blame]7 pmc@7000f400 {
8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]12 intc: interrupt-controller@50041000 {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]13 compatible = "arm,cortex-a9-gic";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]14 interrupt-controller;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]15 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 };
19
Stephen Warren583553b2012-02-27 18:26:36 -0700[diff] [blame^]20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 56 0x04
23 0 57 0x04>;
24 };
25
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]26 apbdma: dma@6000a000 {
27 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>;
29 interrupts = < 0 104 0x04
30 0 105 0x04
31 0 106 0x04
32 0 107 0x04
33 0 108 0x04
34 0 109 0x04
35 0 110 0x04
36 0 111 0x04
37 0 112 0x04
38 0 113 0x04
39 0 114 0x04
40 0 115 0x04
41 0 116 0x04
42 0 117 0x04
43 0 118 0x04
44 0 119 0x04 >;
45 };
46
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]47 i2c@7000c000 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 compatible = "nvidia,tegra20-i2c";
51 reg = <0x7000C000 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]52 interrupts = < 0 38 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]53 };
54
55 i2c@7000c400 {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 compatible = "nvidia,tegra20-i2c";
59 reg = <0x7000C400 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]60 interrupts = < 0 84 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]61 };
62
63 i2c@7000c500 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 compatible = "nvidia,tegra20-i2c";
67 reg = <0x7000C500 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]68 interrupts = < 0 92 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]69 };
70
71 i2c@7000d000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
Stephen Warren0bc2ecb2011-12-17 23:29:31 -0700[diff] [blame]74 compatible = "nvidia,tegra20-i2c-dvc";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]75 reg = <0x7000D000 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]76 interrupts = < 0 53 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]77 };
78
Stephen Warrenc404af02012-01-11 16:09:56 -0700[diff] [blame]79 tegra_i2s1: i2s@70002800 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]80 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]82 interrupts = < 0 13 0x04 >;
Stephen Warren5c8ee312012-01-11 16:09:55 -0700[diff] [blame]83 nvidia,dma-request-selector = < &apbdma 2 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]84 };
85
Stephen Warrenc404af02012-01-11 16:09:56 -0700[diff] [blame]86 tegra_i2s2: i2s@70002a00 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]87 compatible = "nvidia,tegra20-i2s";
88 reg = <0x70002a00 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]89 interrupts = < 0 3 0x04 >;
Stephen Warren5c8ee312012-01-11 16:09:55 -0700[diff] [blame]90 nvidia,dma-request-selector = < &apbdma 1 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]91 };
92
93 das@70000c00 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]94 compatible = "nvidia,tegra20-das";
95 reg = <0x70000c00 0x80>;
96 };
97
98 gpio: gpio@6000d000 {
99 compatible = "nvidia,tegra20-gpio";
100 reg = < 0x6000d000 0x1000 >;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]101 interrupts = < 0 32 0x04
102 0 33 0x04
103 0 34 0x04
104 0 35 0x04
105 0 55 0x04
106 0 87 0x04
107 0 89 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]108 #gpio-cells = <2>;
109 gpio-controller;
110 };
111
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]112 pinmux: pinmux@70000000 {
113 compatible = "nvidia,tegra20-pinmux";
114 reg = < 0x70000014 0x10 /* Tri-state registers */
115 0x70000080 0x20 /* Mux registers */
116 0x700000a0 0x14 /* Pull-up/down registers */
117 0x70000868 0xa8 >; /* Pad control registers */
118 };
119
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]120 serial@70006000 {
121 compatible = "nvidia,tegra20-uart";
122 reg = <0x70006000 0x40>;
123 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]124 interrupts = < 0 36 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]125 };
126
127 serial@70006040 {
128 compatible = "nvidia,tegra20-uart";
129 reg = <0x70006040 0x40>;
130 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]131 interrupts = < 0 37 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]132 };
133
134 serial@70006200 {
135 compatible = "nvidia,tegra20-uart";
136 reg = <0x70006200 0x100>;
137 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]138 interrupts = < 0 46 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]139 };
140
141 serial@70006300 {
142 compatible = "nvidia,tegra20-uart";
143 reg = <0x70006300 0x100>;
144 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]145 interrupts = < 0 90 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]146 };
147
148 serial@70006400 {
149 compatible = "nvidia,tegra20-uart";
150 reg = <0x70006400 0x100>;
151 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]152 interrupts = < 0 91 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]153 };
154
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]155 emc@7000f400 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "nvidia,tegra20-emc";
159 reg = <0x7000f400 0x200>;
160 };
161
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]162 sdhci@c8000000 {
163 compatible = "nvidia,tegra20-sdhci";
164 reg = <0xc8000000 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]165 interrupts = < 0 14 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]166 };
167
168 sdhci@c8000200 {
169 compatible = "nvidia,tegra20-sdhci";
170 reg = <0xc8000200 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]171 interrupts = < 0 15 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]172 };
173
174 sdhci@c8000400 {
175 compatible = "nvidia,tegra20-sdhci";
176 reg = <0xc8000400 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]177 interrupts = < 0 19 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]178 };
179
180 sdhci@c8000600 {
181 compatible = "nvidia,tegra20-sdhci";
182 reg = <0xc8000600 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]183 interrupts = < 0 31 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]184 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]185
186 usb@c5000000 {
187 compatible = "nvidia,tegra20-ehci", "usb-ehci";
188 reg = <0xc5000000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]189 interrupts = < 0 20 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]190 phy_type = "utmi";
191 };
192
193 usb@c5004000 {
194 compatible = "nvidia,tegra20-ehci", "usb-ehci";
195 reg = <0xc5004000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]196 interrupts = < 0 21 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]197 phy_type = "ulpi";
198 };
199
200 usb@c5008000 {
201 compatible = "nvidia,tegra20-ehci", "usb-ehci";
202 reg = <0xc5008000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]203 interrupts = < 0 97 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]204 phy_type = "utmi";
205 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]206};
207