Mark Brown | b35a28a | 2009-12-18 12:00:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * wm8955.c -- WM8955 ALSA SoC Audio driver |
| 3 | * |
| 4 | * Copyright 2009 Wolfson Microelectronics plc |
| 5 | * |
| 6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/moduleparam.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/pm.h> |
| 18 | #include <linux/i2c.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/regulator/consumer.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame^] | 21 | #include <linux/slab.h> |
Mark Brown | b35a28a | 2009-12-18 12:00:22 +0000 | [diff] [blame] | 22 | #include <sound/core.h> |
| 23 | #include <sound/pcm.h> |
| 24 | #include <sound/pcm_params.h> |
| 25 | #include <sound/soc.h> |
| 26 | #include <sound/soc-dapm.h> |
| 27 | #include <sound/initval.h> |
| 28 | #include <sound/tlv.h> |
| 29 | #include <sound/wm8955.h> |
| 30 | |
| 31 | #include "wm8955.h" |
| 32 | |
| 33 | static struct snd_soc_codec *wm8955_codec; |
| 34 | struct snd_soc_codec_device soc_codec_dev_wm8955; |
| 35 | |
| 36 | #define WM8955_NUM_SUPPLIES 4 |
| 37 | static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = { |
| 38 | "DCVDD", |
| 39 | "DBVDD", |
| 40 | "HPVDD", |
| 41 | "AVDD", |
| 42 | }; |
| 43 | |
| 44 | /* codec private data */ |
| 45 | struct wm8955_priv { |
| 46 | struct snd_soc_codec codec; |
| 47 | u16 reg_cache[WM8955_MAX_REGISTER + 1]; |
| 48 | |
| 49 | unsigned int mclk_rate; |
| 50 | |
| 51 | int deemph; |
| 52 | int fs; |
| 53 | |
| 54 | struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES]; |
| 55 | |
| 56 | struct wm8955_pdata *pdata; |
| 57 | }; |
| 58 | |
| 59 | static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = { |
| 60 | 0x0000, /* R0 */ |
| 61 | 0x0000, /* R1 */ |
| 62 | 0x0079, /* R2 - LOUT1 volume */ |
| 63 | 0x0079, /* R3 - ROUT1 volume */ |
| 64 | 0x0000, /* R4 */ |
| 65 | 0x0008, /* R5 - DAC Control */ |
| 66 | 0x0000, /* R6 */ |
| 67 | 0x000A, /* R7 - Audio Interface */ |
| 68 | 0x0000, /* R8 - Sample Rate */ |
| 69 | 0x0000, /* R9 */ |
| 70 | 0x00FF, /* R10 - Left DAC volume */ |
| 71 | 0x00FF, /* R11 - Right DAC volume */ |
| 72 | 0x000F, /* R12 - Bass control */ |
| 73 | 0x000F, /* R13 - Treble control */ |
| 74 | 0x0000, /* R14 */ |
| 75 | 0x0000, /* R15 - Reset */ |
| 76 | 0x0000, /* R16 */ |
| 77 | 0x0000, /* R17 */ |
| 78 | 0x0000, /* R18 */ |
| 79 | 0x0000, /* R19 */ |
| 80 | 0x0000, /* R20 */ |
| 81 | 0x0000, /* R21 */ |
| 82 | 0x0000, /* R22 */ |
| 83 | 0x00C1, /* R23 - Additional control (1) */ |
| 84 | 0x0000, /* R24 - Additional control (2) */ |
| 85 | 0x0000, /* R25 - Power Management (1) */ |
| 86 | 0x0000, /* R26 - Power Management (2) */ |
| 87 | 0x0000, /* R27 - Additional Control (3) */ |
| 88 | 0x0000, /* R28 */ |
| 89 | 0x0000, /* R29 */ |
| 90 | 0x0000, /* R30 */ |
| 91 | 0x0000, /* R31 */ |
| 92 | 0x0000, /* R32 */ |
| 93 | 0x0000, /* R33 */ |
| 94 | 0x0050, /* R34 - Left out Mix (1) */ |
| 95 | 0x0050, /* R35 - Left out Mix (2) */ |
| 96 | 0x0050, /* R36 - Right out Mix (1) */ |
| 97 | 0x0050, /* R37 - Right Out Mix (2) */ |
| 98 | 0x0050, /* R38 - Mono out Mix (1) */ |
| 99 | 0x0050, /* R39 - Mono out Mix (2) */ |
| 100 | 0x0079, /* R40 - LOUT2 volume */ |
| 101 | 0x0079, /* R41 - ROUT2 volume */ |
| 102 | 0x0079, /* R42 - MONOOUT volume */ |
| 103 | 0x0000, /* R43 - Clocking / PLL */ |
| 104 | 0x0103, /* R44 - PLL Control 1 */ |
| 105 | 0x0024, /* R45 - PLL Control 2 */ |
| 106 | 0x01BA, /* R46 - PLL Control 3 */ |
| 107 | 0x0000, /* R47 */ |
| 108 | 0x0000, /* R48 */ |
| 109 | 0x0000, /* R49 */ |
| 110 | 0x0000, /* R50 */ |
| 111 | 0x0000, /* R51 */ |
| 112 | 0x0000, /* R52 */ |
| 113 | 0x0000, /* R53 */ |
| 114 | 0x0000, /* R54 */ |
| 115 | 0x0000, /* R55 */ |
| 116 | 0x0000, /* R56 */ |
| 117 | 0x0000, /* R57 */ |
| 118 | 0x0000, /* R58 */ |
| 119 | 0x0000, /* R59 - PLL Control 4 */ |
| 120 | }; |
| 121 | |
| 122 | static int wm8955_reset(struct snd_soc_codec *codec) |
| 123 | { |
| 124 | return snd_soc_write(codec, WM8955_RESET, 0); |
| 125 | } |
| 126 | |
| 127 | struct pll_factors { |
| 128 | int n; |
| 129 | int k; |
| 130 | int outdiv; |
| 131 | }; |
| 132 | |
| 133 | /* The size in bits of the FLL divide multiplied by 10 |
| 134 | * to allow rounding later */ |
| 135 | #define FIXED_FLL_SIZE ((1 << 22) * 10) |
| 136 | |
| 137 | static int wm8995_pll_factors(struct device *dev, |
| 138 | int Fref, int Fout, struct pll_factors *pll) |
| 139 | { |
| 140 | u64 Kpart; |
| 141 | unsigned int K, Ndiv, Nmod, target; |
| 142 | |
| 143 | dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout); |
| 144 | |
| 145 | /* The oscilator should run at should be 90-100MHz, and |
| 146 | * there's a divide by 4 plus an optional divide by 2 in the |
| 147 | * output path to generate the system clock. The clock table |
| 148 | * is sortd so we should always generate a suitable target. */ |
| 149 | target = Fout * 4; |
| 150 | if (target < 90000000) { |
| 151 | pll->outdiv = 1; |
| 152 | target *= 2; |
| 153 | } else { |
| 154 | pll->outdiv = 0; |
| 155 | } |
| 156 | |
| 157 | WARN_ON(target < 90000000 || target > 100000000); |
| 158 | |
| 159 | dev_dbg(dev, "Fvco=%dHz\n", target); |
| 160 | |
| 161 | /* Now, calculate N.K */ |
| 162 | Ndiv = target / Fref; |
| 163 | |
| 164 | pll->n = Ndiv; |
| 165 | Nmod = target % Fref; |
| 166 | dev_dbg(dev, "Nmod=%d\n", Nmod); |
| 167 | |
| 168 | /* Calculate fractional part - scale up so we can round. */ |
| 169 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; |
| 170 | |
| 171 | do_div(Kpart, Fref); |
| 172 | |
| 173 | K = Kpart & 0xFFFFFFFF; |
| 174 | |
| 175 | if ((K % 10) >= 5) |
| 176 | K += 5; |
| 177 | |
| 178 | /* Move down to proper range now rounding is done */ |
| 179 | pll->k = K / 10; |
| 180 | |
| 181 | dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); |
| 182 | |
| 183 | return 0; |
| 184 | } |
| 185 | |
| 186 | /* Lookup table specifiying SRATE (table 25 in datasheet); some of the |
| 187 | * output frequencies have been rounded to the standard frequencies |
| 188 | * they are intended to match where the error is slight. */ |
| 189 | static struct { |
| 190 | int mclk; |
| 191 | int fs; |
| 192 | int usb; |
| 193 | int sr; |
| 194 | } clock_cfgs[] = { |
| 195 | { 18432000, 8000, 0, 3, }, |
| 196 | { 18432000, 12000, 0, 9, }, |
| 197 | { 18432000, 16000, 0, 11, }, |
| 198 | { 18432000, 24000, 0, 29, }, |
| 199 | { 18432000, 32000, 0, 13, }, |
| 200 | { 18432000, 48000, 0, 1, }, |
| 201 | { 18432000, 96000, 0, 15, }, |
| 202 | |
| 203 | { 16934400, 8018, 0, 19, }, |
| 204 | { 16934400, 11025, 0, 25, }, |
| 205 | { 16934400, 22050, 0, 27, }, |
| 206 | { 16934400, 44100, 0, 17, }, |
| 207 | { 16934400, 88200, 0, 31, }, |
| 208 | |
| 209 | { 12000000, 8000, 1, 2, }, |
| 210 | { 12000000, 11025, 1, 25, }, |
| 211 | { 12000000, 12000, 1, 8, }, |
| 212 | { 12000000, 16000, 1, 10, }, |
| 213 | { 12000000, 22050, 1, 27, }, |
| 214 | { 12000000, 24000, 1, 28, }, |
| 215 | { 12000000, 32000, 1, 12, }, |
| 216 | { 12000000, 44100, 1, 17, }, |
| 217 | { 12000000, 48000, 1, 0, }, |
| 218 | { 12000000, 88200, 1, 31, }, |
| 219 | { 12000000, 96000, 1, 14, }, |
| 220 | |
| 221 | { 12288000, 8000, 0, 2, }, |
| 222 | { 12288000, 12000, 0, 8, }, |
| 223 | { 12288000, 16000, 0, 10, }, |
| 224 | { 12288000, 24000, 0, 28, }, |
| 225 | { 12288000, 32000, 0, 12, }, |
| 226 | { 12288000, 48000, 0, 0, }, |
| 227 | { 12288000, 96000, 0, 14, }, |
| 228 | |
| 229 | { 12289600, 8018, 0, 18, }, |
| 230 | { 12289600, 11025, 0, 24, }, |
| 231 | { 12289600, 22050, 0, 26, }, |
| 232 | { 11289600, 44100, 0, 16, }, |
| 233 | { 11289600, 88200, 0, 31, }, |
| 234 | }; |
| 235 | |
| 236 | static int wm8955_configure_clocking(struct snd_soc_codec *codec) |
| 237 | { |
| 238 | struct wm8955_priv *wm8955 = codec->private_data; |
| 239 | int i, ret, val; |
| 240 | int clocking = 0; |
| 241 | int srate = 0; |
| 242 | int sr = -1; |
| 243 | struct pll_factors pll; |
| 244 | |
| 245 | /* If we're not running a sample rate currently just pick one */ |
| 246 | if (wm8955->fs == 0) |
| 247 | wm8955->fs = 8000; |
| 248 | |
| 249 | /* Can we generate an exact output? */ |
| 250 | for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) { |
| 251 | if (wm8955->fs != clock_cfgs[i].fs) |
| 252 | continue; |
| 253 | sr = i; |
| 254 | |
| 255 | if (wm8955->mclk_rate == clock_cfgs[i].mclk) |
| 256 | break; |
| 257 | } |
| 258 | |
| 259 | /* We should never get here with an unsupported sample rate */ |
| 260 | if (sr == -1) { |
| 261 | dev_err(codec->dev, "Sample rate %dHz unsupported\n", |
| 262 | wm8955->fs); |
| 263 | WARN_ON(sr == -1); |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | |
| 267 | if (i == ARRAY_SIZE(clock_cfgs)) { |
| 268 | /* If we can't generate the right clock from MCLK then |
| 269 | * we should configure the PLL to supply us with an |
| 270 | * appropriate clock. |
| 271 | */ |
| 272 | clocking |= WM8955_MCLKSEL; |
| 273 | |
| 274 | /* Use the last divider configuration we saw for the |
| 275 | * sample rate. */ |
| 276 | ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate, |
| 277 | clock_cfgs[sr].mclk, &pll); |
| 278 | if (ret != 0) { |
| 279 | dev_err(codec->dev, |
| 280 | "Unable to generate %dHz from %dHz MCLK\n", |
| 281 | wm8955->fs, wm8955->mclk_rate); |
| 282 | return -EINVAL; |
| 283 | } |
| 284 | |
| 285 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1, |
| 286 | WM8955_N_MASK | WM8955_K_21_18_MASK, |
| 287 | (pll.n << WM8955_N_SHIFT) | |
| 288 | pll.k >> 18); |
| 289 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2, |
| 290 | WM8955_K_17_9_MASK, |
| 291 | (pll.k >> 9) & WM8955_K_17_9_MASK); |
| 292 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2, |
| 293 | WM8955_K_8_0_MASK, |
| 294 | pll.k & WM8955_K_8_0_MASK); |
| 295 | if (pll.k) |
| 296 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4, |
| 297 | WM8955_KEN, WM8955_KEN); |
| 298 | else |
| 299 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4, |
| 300 | WM8955_KEN, 0); |
| 301 | |
| 302 | if (pll.outdiv) |
| 303 | val = WM8955_PLL_RB | WM8955_PLLOUTDIV2; |
| 304 | else |
| 305 | val = WM8955_PLL_RB; |
| 306 | |
| 307 | /* Now start the PLL running */ |
| 308 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, |
| 309 | WM8955_PLL_RB | WM8955_PLLOUTDIV2, val); |
| 310 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, |
| 311 | WM8955_PLLEN, WM8955_PLLEN); |
| 312 | } |
| 313 | |
| 314 | srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT); |
| 315 | |
| 316 | snd_soc_update_bits(codec, WM8955_SAMPLE_RATE, |
| 317 | WM8955_USB | WM8955_SR_MASK, srate); |
| 318 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, |
| 319 | WM8955_MCLKSEL, clocking); |
| 320 | |
| 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | static int wm8955_sysclk(struct snd_soc_dapm_widget *w, |
| 325 | struct snd_kcontrol *kcontrol, int event) |
| 326 | { |
| 327 | struct snd_soc_codec *codec = w->codec; |
| 328 | int ret = 0; |
| 329 | |
| 330 | /* Always disable the clocks - if we're doing reconfiguration this |
| 331 | * avoids misclocking. |
| 332 | */ |
| 333 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, |
| 334 | WM8955_DIGENB, 0); |
| 335 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, |
| 336 | WM8955_PLL_RB | WM8955_PLLEN, 0); |
| 337 | |
| 338 | switch (event) { |
| 339 | case SND_SOC_DAPM_POST_PMD: |
| 340 | break; |
| 341 | case SND_SOC_DAPM_PRE_PMU: |
| 342 | ret = wm8955_configure_clocking(codec); |
| 343 | break; |
| 344 | default: |
| 345 | ret = -EINVAL; |
| 346 | break; |
| 347 | } |
| 348 | |
| 349 | return ret; |
| 350 | } |
| 351 | |
| 352 | static int deemph_settings[] = { 0, 32000, 44100, 48000 }; |
| 353 | |
| 354 | static int wm8955_set_deemph(struct snd_soc_codec *codec) |
| 355 | { |
| 356 | struct wm8955_priv *wm8955 = codec->private_data; |
| 357 | int val, i, best; |
| 358 | |
| 359 | /* If we're using deemphasis select the nearest available sample |
| 360 | * rate. |
| 361 | */ |
| 362 | if (wm8955->deemph) { |
| 363 | best = 1; |
| 364 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { |
| 365 | if (abs(deemph_settings[i] - wm8955->fs) < |
| 366 | abs(deemph_settings[best] - wm8955->fs)) |
| 367 | best = i; |
| 368 | } |
| 369 | |
| 370 | val = best << WM8955_DEEMPH_SHIFT; |
| 371 | } else { |
| 372 | val = 0; |
| 373 | } |
| 374 | |
| 375 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); |
| 376 | |
| 377 | return snd_soc_update_bits(codec, WM8955_DAC_CONTROL, |
| 378 | WM8955_DEEMPH_MASK, val); |
| 379 | } |
| 380 | |
| 381 | static int wm8955_get_deemph(struct snd_kcontrol *kcontrol, |
| 382 | struct snd_ctl_elem_value *ucontrol) |
| 383 | { |
| 384 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 385 | struct wm8955_priv *wm8955 = codec->private_data; |
| 386 | |
| 387 | return wm8955->deemph; |
| 388 | } |
| 389 | |
| 390 | static int wm8955_put_deemph(struct snd_kcontrol *kcontrol, |
| 391 | struct snd_ctl_elem_value *ucontrol) |
| 392 | { |
| 393 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 394 | struct wm8955_priv *wm8955 = codec->private_data; |
| 395 | int deemph = ucontrol->value.enumerated.item[0]; |
| 396 | |
| 397 | if (deemph > 1) |
| 398 | return -EINVAL; |
| 399 | |
| 400 | wm8955->deemph = deemph; |
| 401 | |
| 402 | return wm8955_set_deemph(codec); |
| 403 | } |
| 404 | |
| 405 | static const char *bass_mode_text[] = { |
| 406 | "Linear", "Adaptive", |
| 407 | }; |
| 408 | |
| 409 | static const struct soc_enum bass_mode = |
| 410 | SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text); |
| 411 | |
| 412 | static const char *bass_cutoff_text[] = { |
| 413 | "Low", "High" |
| 414 | }; |
| 415 | |
| 416 | static const struct soc_enum bass_cutoff = |
| 417 | SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text); |
| 418 | |
| 419 | static const char *treble_cutoff_text[] = { |
| 420 | "High", "Low" |
| 421 | }; |
| 422 | |
| 423 | static const struct soc_enum treble_cutoff = |
| 424 | SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text); |
| 425 | |
| 426 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); |
| 427 | static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0); |
| 428 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); |
| 429 | static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0); |
| 430 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); |
| 431 | static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1); |
| 432 | |
| 433 | static const struct snd_kcontrol_new wm8955_snd_controls[] = { |
| 434 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME, |
| 435 | WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv), |
| 436 | SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1, |
| 437 | atten_tlv), |
| 438 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, |
| 439 | wm8955_get_deemph, wm8955_put_deemph), |
| 440 | |
| 441 | SOC_ENUM("Bass Mode", bass_mode), |
| 442 | SOC_ENUM("Bass Cutoff", bass_cutoff), |
| 443 | SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1), |
| 444 | |
| 445 | SOC_ENUM("Treble Cutoff", treble_cutoff), |
| 446 | SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv), |
| 447 | |
| 448 | SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1, |
| 449 | bypass_tlv), |
| 450 | SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1, |
| 451 | bypass_tlv), |
| 452 | |
| 453 | SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1, |
| 454 | bypass_tlv), |
| 455 | SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1, |
| 456 | bypass_tlv), |
| 457 | |
| 458 | /* Not a stereo pair so they line up with the DAPM switches */ |
| 459 | SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1, |
| 460 | mono_tlv), |
| 461 | SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1, |
| 462 | mono_tlv), |
| 463 | |
| 464 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME, |
| 465 | WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv), |
| 466 | SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME, |
| 467 | WM8955_ROUT1_VOLUME, 7, 1, 0), |
| 468 | |
| 469 | SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME, |
| 470 | WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv), |
| 471 | SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME, |
| 472 | WM8955_ROUT2_VOLUME, 7, 1, 0), |
| 473 | |
| 474 | SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv), |
| 475 | SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0), |
| 476 | }; |
| 477 | |
| 478 | static const struct snd_kcontrol_new lmixer[] = { |
| 479 | SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0), |
| 480 | SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0), |
| 481 | SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0), |
| 482 | SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0), |
| 483 | }; |
| 484 | |
| 485 | static const struct snd_kcontrol_new rmixer[] = { |
| 486 | SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0), |
| 487 | SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0), |
| 488 | SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0), |
| 489 | SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0), |
| 490 | }; |
| 491 | |
| 492 | static const struct snd_kcontrol_new mmixer[] = { |
| 493 | SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0), |
| 494 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0), |
| 495 | SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0), |
| 496 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0), |
| 497 | }; |
| 498 | |
| 499 | static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = { |
| 500 | SND_SOC_DAPM_INPUT("MONOIN-"), |
| 501 | SND_SOC_DAPM_INPUT("MONOIN+"), |
| 502 | SND_SOC_DAPM_INPUT("LINEINR"), |
| 503 | SND_SOC_DAPM_INPUT("LINEINL"), |
| 504 | |
| 505 | SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 506 | |
| 507 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk, |
| 508 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 509 | SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0), |
| 510 | |
| 511 | SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0), |
| 512 | SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0), |
| 513 | |
| 514 | SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0), |
| 515 | SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0), |
| 516 | SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0), |
| 517 | SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0), |
| 518 | SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0), |
| 519 | SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0), |
| 520 | |
| 521 | /* The names are chosen to make the control names nice */ |
| 522 | SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0, |
| 523 | lmixer, ARRAY_SIZE(lmixer)), |
| 524 | SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0, |
| 525 | rmixer, ARRAY_SIZE(rmixer)), |
| 526 | SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0, |
| 527 | mmixer, ARRAY_SIZE(mmixer)), |
| 528 | |
| 529 | SND_SOC_DAPM_OUTPUT("LOUT1"), |
| 530 | SND_SOC_DAPM_OUTPUT("ROUT1"), |
| 531 | SND_SOC_DAPM_OUTPUT("LOUT2"), |
| 532 | SND_SOC_DAPM_OUTPUT("ROUT2"), |
| 533 | SND_SOC_DAPM_OUTPUT("MONOOUT"), |
| 534 | SND_SOC_DAPM_OUTPUT("OUT3"), |
| 535 | }; |
| 536 | |
| 537 | static const struct snd_soc_dapm_route wm8955_intercon[] = { |
| 538 | { "DACL", NULL, "SYSCLK" }, |
| 539 | { "DACR", NULL, "SYSCLK" }, |
| 540 | |
| 541 | { "Mono Input", NULL, "MONOIN-" }, |
| 542 | { "Mono Input", NULL, "MONOIN+" }, |
| 543 | |
| 544 | { "Left", "Playback Switch", "DACL" }, |
| 545 | { "Left", "Right Playback Switch", "DACR" }, |
| 546 | { "Left", "Bypass Switch", "LINEINL" }, |
| 547 | { "Left", "Mono Switch", "Mono Input" }, |
| 548 | |
| 549 | { "Right", "Playback Switch", "DACR" }, |
| 550 | { "Right", "Left Playback Switch", "DACL" }, |
| 551 | { "Right", "Bypass Switch", "LINEINR" }, |
| 552 | { "Right", "Mono Switch", "Mono Input" }, |
| 553 | |
| 554 | { "Mono", "Left Playback Switch", "DACL" }, |
| 555 | { "Mono", "Right Playback Switch", "DACR" }, |
| 556 | { "Mono", "Left Bypass Switch", "LINEINL" }, |
| 557 | { "Mono", "Right Bypass Switch", "LINEINR" }, |
| 558 | |
| 559 | { "LOUT1 PGA", NULL, "Left" }, |
| 560 | { "LOUT1", NULL, "TSDEN" }, |
| 561 | { "LOUT1", NULL, "LOUT1 PGA" }, |
| 562 | |
| 563 | { "ROUT1 PGA", NULL, "Right" }, |
| 564 | { "ROUT1", NULL, "TSDEN" }, |
| 565 | { "ROUT1", NULL, "ROUT1 PGA" }, |
| 566 | |
| 567 | { "LOUT2 PGA", NULL, "Left" }, |
| 568 | { "LOUT2", NULL, "TSDEN" }, |
| 569 | { "LOUT2", NULL, "LOUT2 PGA" }, |
| 570 | |
| 571 | { "ROUT2 PGA", NULL, "Right" }, |
| 572 | { "ROUT2", NULL, "TSDEN" }, |
| 573 | { "ROUT2", NULL, "ROUT2 PGA" }, |
| 574 | |
| 575 | { "MOUT PGA", NULL, "Mono" }, |
| 576 | { "MONOOUT", NULL, "MOUT PGA" }, |
| 577 | |
| 578 | /* OUT3 not currently implemented */ |
| 579 | { "OUT3", NULL, "OUT3 PGA" }, |
| 580 | }; |
| 581 | |
| 582 | static int wm8955_add_widgets(struct snd_soc_codec *codec) |
| 583 | { |
| 584 | snd_soc_add_controls(codec, wm8955_snd_controls, |
| 585 | ARRAY_SIZE(wm8955_snd_controls)); |
| 586 | |
| 587 | snd_soc_dapm_new_controls(codec, wm8955_dapm_widgets, |
| 588 | ARRAY_SIZE(wm8955_dapm_widgets)); |
| 589 | |
| 590 | snd_soc_dapm_add_routes(codec, wm8955_intercon, |
| 591 | ARRAY_SIZE(wm8955_intercon)); |
| 592 | |
| 593 | return 0; |
| 594 | } |
| 595 | |
| 596 | static int wm8955_hw_params(struct snd_pcm_substream *substream, |
| 597 | struct snd_pcm_hw_params *params, |
| 598 | struct snd_soc_dai *dai) |
| 599 | { |
| 600 | struct snd_soc_codec *codec = dai->codec; |
| 601 | struct wm8955_priv *wm8955 = codec->private_data; |
| 602 | int ret; |
| 603 | int wl; |
| 604 | |
| 605 | switch (params_format(params)) { |
| 606 | case SNDRV_PCM_FORMAT_S16_LE: |
| 607 | wl = 0; |
| 608 | break; |
| 609 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 610 | wl = 0x4; |
| 611 | break; |
| 612 | case SNDRV_PCM_FORMAT_S24_LE: |
| 613 | wl = 0x8; |
| 614 | break; |
| 615 | case SNDRV_PCM_FORMAT_S32_LE: |
| 616 | wl = 0xc; |
| 617 | break; |
| 618 | default: |
| 619 | return -EINVAL; |
| 620 | } |
| 621 | snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE, |
| 622 | WM8955_WL_MASK, wl); |
| 623 | |
| 624 | wm8955->fs = params_rate(params); |
| 625 | wm8955_set_deemph(codec); |
| 626 | |
| 627 | /* If the chip is clocked then disable the clocks and force a |
| 628 | * reconfiguration, otherwise DAPM will power up the |
| 629 | * clocks for us later. */ |
| 630 | ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1); |
| 631 | if (ret < 0) |
| 632 | return ret; |
| 633 | if (ret & WM8955_DIGENB) { |
| 634 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, |
| 635 | WM8955_DIGENB, 0); |
| 636 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, |
| 637 | WM8955_PLL_RB | WM8955_PLLEN, 0); |
| 638 | |
| 639 | wm8955_configure_clocking(codec); |
| 640 | } |
| 641 | |
| 642 | return 0; |
| 643 | } |
| 644 | |
| 645 | |
| 646 | static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
| 647 | unsigned int freq, int dir) |
| 648 | { |
| 649 | struct snd_soc_codec *codec = dai->codec; |
| 650 | struct wm8955_priv *priv = codec->private_data; |
| 651 | int div; |
| 652 | |
| 653 | switch (clk_id) { |
| 654 | case WM8955_CLK_MCLK: |
| 655 | if (freq > 15000000) { |
| 656 | priv->mclk_rate = freq /= 2; |
| 657 | div = WM8955_MCLKDIV2; |
| 658 | } else { |
| 659 | priv->mclk_rate = freq; |
| 660 | div = 0; |
| 661 | } |
| 662 | |
| 663 | snd_soc_update_bits(codec, WM8955_SAMPLE_RATE, |
| 664 | WM8955_MCLKDIV2, div); |
| 665 | break; |
| 666 | |
| 667 | default: |
| 668 | return -EINVAL; |
| 669 | } |
| 670 | |
| 671 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); |
| 672 | |
| 673 | return 0; |
| 674 | } |
| 675 | |
| 676 | static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 677 | { |
| 678 | struct snd_soc_codec *codec = dai->codec; |
| 679 | u16 aif = 0; |
| 680 | |
| 681 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 682 | case SND_SOC_DAIFMT_CBS_CFS: |
| 683 | break; |
| 684 | case SND_SOC_DAIFMT_CBM_CFM: |
| 685 | aif |= WM8955_MS; |
| 686 | break; |
| 687 | default: |
| 688 | return -EINVAL; |
| 689 | } |
| 690 | |
| 691 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 692 | case SND_SOC_DAIFMT_DSP_B: |
| 693 | aif |= WM8955_LRP; |
| 694 | case SND_SOC_DAIFMT_DSP_A: |
| 695 | aif |= 0x3; |
| 696 | break; |
| 697 | case SND_SOC_DAIFMT_I2S: |
| 698 | aif |= 0x2; |
| 699 | break; |
| 700 | case SND_SOC_DAIFMT_RIGHT_J: |
| 701 | break; |
| 702 | case SND_SOC_DAIFMT_LEFT_J: |
| 703 | aif |= 0x1; |
| 704 | break; |
| 705 | default: |
| 706 | return -EINVAL; |
| 707 | } |
| 708 | |
| 709 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 710 | case SND_SOC_DAIFMT_DSP_A: |
| 711 | case SND_SOC_DAIFMT_DSP_B: |
| 712 | /* frame inversion not valid for DSP modes */ |
| 713 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 714 | case SND_SOC_DAIFMT_NB_NF: |
| 715 | break; |
| 716 | case SND_SOC_DAIFMT_IB_NF: |
| 717 | aif |= WM8955_BCLKINV; |
| 718 | break; |
| 719 | default: |
| 720 | return -EINVAL; |
| 721 | } |
| 722 | break; |
| 723 | |
| 724 | case SND_SOC_DAIFMT_I2S: |
| 725 | case SND_SOC_DAIFMT_RIGHT_J: |
| 726 | case SND_SOC_DAIFMT_LEFT_J: |
| 727 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 728 | case SND_SOC_DAIFMT_NB_NF: |
| 729 | break; |
| 730 | case SND_SOC_DAIFMT_IB_IF: |
| 731 | aif |= WM8955_BCLKINV | WM8955_LRP; |
| 732 | break; |
| 733 | case SND_SOC_DAIFMT_IB_NF: |
| 734 | aif |= WM8955_BCLKINV; |
| 735 | break; |
| 736 | case SND_SOC_DAIFMT_NB_IF: |
| 737 | aif |= WM8955_LRP; |
| 738 | break; |
| 739 | default: |
| 740 | return -EINVAL; |
| 741 | } |
| 742 | break; |
| 743 | default: |
| 744 | return -EINVAL; |
| 745 | } |
| 746 | |
| 747 | snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE, |
| 748 | WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV | |
| 749 | WM8955_LRP, aif); |
| 750 | |
| 751 | return 0; |
| 752 | } |
| 753 | |
| 754 | |
| 755 | static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute) |
| 756 | { |
| 757 | struct snd_soc_codec *codec = codec_dai->codec; |
| 758 | int val; |
| 759 | |
| 760 | if (mute) |
| 761 | val = WM8955_DACMU; |
| 762 | else |
| 763 | val = 0; |
| 764 | |
| 765 | snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val); |
| 766 | |
| 767 | return 0; |
| 768 | } |
| 769 | |
| 770 | static int wm8955_set_bias_level(struct snd_soc_codec *codec, |
| 771 | enum snd_soc_bias_level level) |
| 772 | { |
| 773 | struct wm8955_priv *wm8955 = codec->private_data; |
| 774 | int ret, i; |
| 775 | |
| 776 | switch (level) { |
| 777 | case SND_SOC_BIAS_ON: |
| 778 | break; |
| 779 | |
| 780 | case SND_SOC_BIAS_PREPARE: |
| 781 | /* VMID resistance 2*50k */ |
| 782 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, |
| 783 | WM8955_VMIDSEL_MASK, |
| 784 | 0x1 << WM8955_VMIDSEL_SHIFT); |
| 785 | |
| 786 | /* Default bias current */ |
| 787 | snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1, |
| 788 | WM8955_VSEL_MASK, |
| 789 | 0x2 << WM8955_VSEL_SHIFT); |
| 790 | break; |
| 791 | |
| 792 | case SND_SOC_BIAS_STANDBY: |
| 793 | if (codec->bias_level == SND_SOC_BIAS_OFF) { |
| 794 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), |
| 795 | wm8955->supplies); |
| 796 | if (ret != 0) { |
| 797 | dev_err(codec->dev, |
| 798 | "Failed to enable supplies: %d\n", |
| 799 | ret); |
| 800 | return ret; |
| 801 | } |
| 802 | |
| 803 | /* Sync back cached values if they're |
| 804 | * different from the hardware default. |
| 805 | */ |
| 806 | for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) { |
| 807 | if (i == WM8955_RESET) |
| 808 | continue; |
| 809 | |
| 810 | if (wm8955->reg_cache[i] == wm8955_reg[i]) |
| 811 | continue; |
| 812 | |
| 813 | snd_soc_write(codec, i, wm8955->reg_cache[i]); |
| 814 | } |
| 815 | |
| 816 | /* Enable VREF and VMID */ |
| 817 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, |
| 818 | WM8955_VREF | |
| 819 | WM8955_VMIDSEL_MASK, |
| 820 | WM8955_VREF | |
| 821 | 0x3 << WM8955_VREF_SHIFT); |
| 822 | |
| 823 | /* Let VMID ramp */ |
| 824 | msleep(500); |
| 825 | |
| 826 | /* High resistance VROI to maintain outputs */ |
| 827 | snd_soc_update_bits(codec, |
| 828 | WM8955_ADDITIONAL_CONTROL_3, |
| 829 | WM8955_VROI, WM8955_VROI); |
| 830 | } |
| 831 | |
| 832 | /* Maintain VMID with 2*250k */ |
| 833 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, |
| 834 | WM8955_VMIDSEL_MASK, |
| 835 | 0x2 << WM8955_VMIDSEL_SHIFT); |
| 836 | |
| 837 | /* Minimum bias current */ |
| 838 | snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1, |
| 839 | WM8955_VSEL_MASK, 0); |
| 840 | break; |
| 841 | |
| 842 | case SND_SOC_BIAS_OFF: |
| 843 | /* Low resistance VROI to help discharge */ |
| 844 | snd_soc_update_bits(codec, |
| 845 | WM8955_ADDITIONAL_CONTROL_3, |
| 846 | WM8955_VROI, 0); |
| 847 | |
| 848 | /* Turn off VMID and VREF */ |
| 849 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, |
| 850 | WM8955_VREF | |
| 851 | WM8955_VMIDSEL_MASK, 0); |
| 852 | |
| 853 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), |
| 854 | wm8955->supplies); |
| 855 | break; |
| 856 | } |
| 857 | codec->bias_level = level; |
| 858 | return 0; |
| 859 | } |
| 860 | |
| 861 | #define WM8955_RATES SNDRV_PCM_RATE_8000_96000 |
| 862 | |
| 863 | #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
| 864 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 865 | |
| 866 | static struct snd_soc_dai_ops wm8955_dai_ops = { |
| 867 | .set_sysclk = wm8955_set_sysclk, |
| 868 | .set_fmt = wm8955_set_fmt, |
| 869 | .hw_params = wm8955_hw_params, |
| 870 | .digital_mute = wm8955_digital_mute, |
| 871 | }; |
| 872 | |
| 873 | struct snd_soc_dai wm8955_dai = { |
| 874 | .name = "WM8955", |
| 875 | .playback = { |
| 876 | .stream_name = "Playback", |
| 877 | .channels_min = 2, |
| 878 | .channels_max = 2, |
| 879 | .rates = WM8955_RATES, |
| 880 | .formats = WM8955_FORMATS, |
| 881 | }, |
| 882 | .ops = &wm8955_dai_ops, |
| 883 | }; |
| 884 | EXPORT_SYMBOL_GPL(wm8955_dai); |
| 885 | |
| 886 | #ifdef CONFIG_PM |
| 887 | static int wm8955_suspend(struct platform_device *pdev, pm_message_t state) |
| 888 | { |
| 889 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
| 890 | struct snd_soc_codec *codec = socdev->card->codec; |
| 891 | |
| 892 | wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 893 | |
| 894 | return 0; |
| 895 | } |
| 896 | |
| 897 | static int wm8955_resume(struct platform_device *pdev) |
| 898 | { |
| 899 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
| 900 | struct snd_soc_codec *codec = socdev->card->codec; |
| 901 | |
| 902 | wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 903 | |
| 904 | return 0; |
| 905 | } |
| 906 | #else |
| 907 | #define wm8955_suspend NULL |
| 908 | #define wm8955_resume NULL |
| 909 | #endif |
| 910 | |
| 911 | static int wm8955_probe(struct platform_device *pdev) |
| 912 | { |
| 913 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
| 914 | struct snd_soc_codec *codec; |
| 915 | int ret = 0; |
| 916 | |
| 917 | if (wm8955_codec == NULL) { |
| 918 | dev_err(&pdev->dev, "Codec device not registered\n"); |
| 919 | return -ENODEV; |
| 920 | } |
| 921 | |
| 922 | socdev->card->codec = wm8955_codec; |
| 923 | codec = wm8955_codec; |
| 924 | |
| 925 | /* register pcms */ |
| 926 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); |
| 927 | if (ret < 0) { |
| 928 | dev_err(codec->dev, "failed to create pcms: %d\n", ret); |
| 929 | goto pcm_err; |
| 930 | } |
| 931 | |
| 932 | wm8955_add_widgets(codec); |
| 933 | |
| 934 | return ret; |
| 935 | |
| 936 | pcm_err: |
| 937 | return ret; |
| 938 | } |
| 939 | |
| 940 | static int wm8955_remove(struct platform_device *pdev) |
| 941 | { |
| 942 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
| 943 | |
| 944 | snd_soc_free_pcms(socdev); |
| 945 | snd_soc_dapm_free(socdev); |
| 946 | |
| 947 | return 0; |
| 948 | } |
| 949 | |
| 950 | struct snd_soc_codec_device soc_codec_dev_wm8955 = { |
| 951 | .probe = wm8955_probe, |
| 952 | .remove = wm8955_remove, |
| 953 | .suspend = wm8955_suspend, |
| 954 | .resume = wm8955_resume, |
| 955 | }; |
| 956 | EXPORT_SYMBOL_GPL(soc_codec_dev_wm8955); |
| 957 | |
| 958 | static int wm8955_register(struct wm8955_priv *wm8955, |
| 959 | enum snd_soc_control_type control) |
| 960 | { |
| 961 | int ret; |
| 962 | struct snd_soc_codec *codec = &wm8955->codec; |
| 963 | int i; |
| 964 | |
| 965 | if (wm8955_codec) { |
| 966 | dev_err(codec->dev, "Another WM8955 is registered\n"); |
| 967 | return -EINVAL; |
| 968 | } |
| 969 | |
| 970 | mutex_init(&codec->mutex); |
| 971 | INIT_LIST_HEAD(&codec->dapm_widgets); |
| 972 | INIT_LIST_HEAD(&codec->dapm_paths); |
| 973 | |
| 974 | codec->private_data = wm8955; |
| 975 | codec->name = "WM8955"; |
| 976 | codec->owner = THIS_MODULE; |
| 977 | codec->bias_level = SND_SOC_BIAS_OFF; |
| 978 | codec->set_bias_level = wm8955_set_bias_level; |
| 979 | codec->dai = &wm8955_dai; |
| 980 | codec->num_dai = 1; |
| 981 | codec->reg_cache_size = WM8955_MAX_REGISTER; |
| 982 | codec->reg_cache = &wm8955->reg_cache; |
| 983 | |
| 984 | memcpy(codec->reg_cache, wm8955_reg, sizeof(wm8955_reg)); |
| 985 | |
| 986 | ret = snd_soc_codec_set_cache_io(codec, 7, 9, control); |
| 987 | if (ret != 0) { |
| 988 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
| 989 | goto err; |
| 990 | } |
| 991 | |
| 992 | for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++) |
| 993 | wm8955->supplies[i].supply = wm8955_supply_names[i]; |
| 994 | |
| 995 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies), |
| 996 | wm8955->supplies); |
| 997 | if (ret != 0) { |
| 998 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); |
| 999 | goto err; |
| 1000 | } |
| 1001 | |
| 1002 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), |
| 1003 | wm8955->supplies); |
| 1004 | if (ret != 0) { |
| 1005 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); |
| 1006 | goto err_get; |
| 1007 | } |
| 1008 | |
| 1009 | ret = wm8955_reset(codec); |
| 1010 | if (ret < 0) { |
| 1011 | dev_err(codec->dev, "Failed to issue reset: %d\n", ret); |
| 1012 | goto err_enable; |
| 1013 | } |
| 1014 | |
| 1015 | wm8955_dai.dev = codec->dev; |
| 1016 | |
| 1017 | /* Change some default settings - latch VU and enable ZC */ |
| 1018 | wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU; |
| 1019 | wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU; |
| 1020 | wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC; |
| 1021 | wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC; |
| 1022 | wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC; |
| 1023 | wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC; |
| 1024 | wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC; |
| 1025 | |
| 1026 | /* Also enable adaptive bass boost by default */ |
| 1027 | wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB; |
| 1028 | |
| 1029 | /* Set platform data values */ |
| 1030 | if (wm8955->pdata) { |
| 1031 | if (wm8955->pdata->out2_speaker) |
| 1032 | wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2] |
| 1033 | |= WM8955_ROUT2INV; |
| 1034 | |
| 1035 | if (wm8955->pdata->monoin_diff) |
| 1036 | wm8955->reg_cache[WM8955_MONO_OUT_MIX_1] |
| 1037 | |= WM8955_DMEN; |
| 1038 | } |
| 1039 | |
| 1040 | wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1041 | |
| 1042 | /* Bias level configuration will have done an extra enable */ |
| 1043 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); |
| 1044 | |
| 1045 | wm8955_codec = codec; |
| 1046 | |
| 1047 | ret = snd_soc_register_codec(codec); |
| 1048 | if (ret != 0) { |
| 1049 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); |
| 1050 | return ret; |
| 1051 | } |
| 1052 | |
| 1053 | ret = snd_soc_register_dai(&wm8955_dai); |
| 1054 | if (ret != 0) { |
| 1055 | dev_err(codec->dev, "Failed to register DAI: %d\n", ret); |
| 1056 | snd_soc_unregister_codec(codec); |
| 1057 | return ret; |
| 1058 | } |
| 1059 | |
| 1060 | return 0; |
| 1061 | |
| 1062 | err_enable: |
| 1063 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); |
| 1064 | err_get: |
| 1065 | regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); |
| 1066 | err: |
| 1067 | kfree(wm8955); |
| 1068 | return ret; |
| 1069 | } |
| 1070 | |
| 1071 | static void wm8955_unregister(struct wm8955_priv *wm8955) |
| 1072 | { |
| 1073 | wm8955_set_bias_level(&wm8955->codec, SND_SOC_BIAS_OFF); |
| 1074 | regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); |
| 1075 | snd_soc_unregister_dai(&wm8955_dai); |
| 1076 | snd_soc_unregister_codec(&wm8955->codec); |
| 1077 | kfree(wm8955); |
| 1078 | wm8955_codec = NULL; |
| 1079 | } |
| 1080 | |
| 1081 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1082 | static __devinit int wm8955_i2c_probe(struct i2c_client *i2c, |
| 1083 | const struct i2c_device_id *id) |
| 1084 | { |
| 1085 | struct wm8955_priv *wm8955; |
| 1086 | struct snd_soc_codec *codec; |
| 1087 | |
| 1088 | wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL); |
| 1089 | if (wm8955 == NULL) |
| 1090 | return -ENOMEM; |
| 1091 | |
| 1092 | codec = &wm8955->codec; |
| 1093 | codec->hw_write = (hw_write_t)i2c_master_send; |
| 1094 | |
| 1095 | i2c_set_clientdata(i2c, wm8955); |
| 1096 | codec->control_data = i2c; |
| 1097 | wm8955->pdata = i2c->dev.platform_data; |
| 1098 | |
| 1099 | codec->dev = &i2c->dev; |
| 1100 | |
| 1101 | return wm8955_register(wm8955, SND_SOC_I2C); |
| 1102 | } |
| 1103 | |
| 1104 | static __devexit int wm8955_i2c_remove(struct i2c_client *client) |
| 1105 | { |
| 1106 | struct wm8955_priv *wm8955 = i2c_get_clientdata(client); |
| 1107 | wm8955_unregister(wm8955); |
| 1108 | return 0; |
| 1109 | } |
| 1110 | |
| 1111 | static const struct i2c_device_id wm8955_i2c_id[] = { |
| 1112 | { "wm8955", 0 }, |
| 1113 | { } |
| 1114 | }; |
| 1115 | MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id); |
| 1116 | |
| 1117 | static struct i2c_driver wm8955_i2c_driver = { |
| 1118 | .driver = { |
| 1119 | .name = "wm8955", |
| 1120 | .owner = THIS_MODULE, |
| 1121 | }, |
| 1122 | .probe = wm8955_i2c_probe, |
| 1123 | .remove = __devexit_p(wm8955_i2c_remove), |
| 1124 | .id_table = wm8955_i2c_id, |
| 1125 | }; |
| 1126 | #endif |
| 1127 | |
| 1128 | static int __init wm8955_modinit(void) |
| 1129 | { |
| 1130 | int ret; |
| 1131 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1132 | ret = i2c_add_driver(&wm8955_i2c_driver); |
| 1133 | if (ret != 0) { |
| 1134 | printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n", |
| 1135 | ret); |
| 1136 | } |
| 1137 | #endif |
| 1138 | return 0; |
| 1139 | } |
| 1140 | module_init(wm8955_modinit); |
| 1141 | |
| 1142 | static void __exit wm8955_exit(void) |
| 1143 | { |
| 1144 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 1145 | i2c_del_driver(&wm8955_i2c_driver); |
| 1146 | #endif |
| 1147 | } |
| 1148 | module_exit(wm8955_exit); |
| 1149 | |
| 1150 | MODULE_DESCRIPTION("ASoC WM8955 driver"); |
| 1151 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); |
| 1152 | MODULE_LICENSE("GPL"); |