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gerrit-public.fairphone.software / fp2-dev / kernel / msm / 5a66c0805000db10ecb6b97a980e4c2e21dcf47a / . / arch / arm / mach-msm / clock-8226.c
blob: 19993790141f7c8b0cae6f104ff9ab12bbca4bc7 [file] [log] [blame]
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/iopoll.h>
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]22#include <linux/regulator/consumer.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]23
24#include <mach/rpm-regulator-smd.h>
25#include <mach/socinfo.h>
26#include <mach/rpm-smd.h>
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]27#include <mach/clock-generic.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]28
29#include "clock-local2.h"
30#include "clock-pll.h"
31#include "clock-rpm.h"
32#include "clock-voter.h"
33#include "clock-mdss-8974.h"
34#include "clock.h"
35
36enum {
37 GCC_BASE,
38 MMSS_BASE,
39 LPASS_BASE,
40 APCS_BASE,
41 APCS_PLL_BASE,
42 N_BASES,
43};
44
45static void __iomem *virt_bases[N_BASES];
46
47#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
48#define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x))
49#define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x))
50#define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x))
51
52/* Mux source select values */
53#define xo_source_val 0
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]54#define xo_a_clk_source_val 0
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]55#define gpll0_source_val 1
56#define gpll1_source_val 2
57
58#define xo_mm_source_val 0
59#define mmpll0_pll_mm_source_val 1
60#define mmpll1_pll_mm_source_val 2
61#define mmpll2_pll_mm_source_val 3
62#define gpll0_mm_source_val 5
63#define dsipll_750_mm_source_val 1
64#define dsipll_667_mm_source_val 1
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]65#define dsipll0_byte_mm_source_val 1
66#define dsipll0_pixel_mm_source_val 1
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]67
68#define gpll1_hsic_source_val 4
69
70#define xo_lpass_source_val 0
71#define lpaaudio_pll_lpass_source_val 1
72#define gpll0_lpass_source_val 5
73
74/* Prevent a divider of -1 */
75#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
76
77#define F_GCC(f, s, div, m, n) \
78 { \
79 .freq_hz = (f), \
80 .src_clk = &s.c, \
81 .m_val = (m), \
82 .n_val = ~((n)-(m)) * !!(n), \
83 .d_val = ~(n),\
84 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
85 | BVAL(10, 8, s##_source_val), \
86 }
87
88#define F_MMSS(f, s, div, m, n) \
89 { \
90 .freq_hz = (f), \
91 .src_clk = &s.c, \
92 .m_val = (m), \
93 .n_val = ~((n)-(m)) * !!(n), \
94 .d_val = ~(n),\
95 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
96 | BVAL(10, 8, s##_mm_source_val), \
97 }
98
99#define F_MDSS(f, s, div, m, n) \
100 { \
101 .freq_hz = (f), \
102 .m_val = (m), \
103 .n_val = ~((n)-(m)) * !!(n), \
104 .d_val = ~(n),\
105 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
106 | BVAL(10, 8, s##_mm_source_val), \
107 }
108
109#define F_HSIC(f, s, div, m, n) \
110 { \
111 .freq_hz = (f), \
112 .src_clk = &s.c, \
113 .m_val = (m), \
114 .n_val = ~((n)-(m)) * !!(n), \
115 .d_val = ~(n),\
116 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
117 | BVAL(10, 8, s##_hsic_source_val), \
118 }
119
120#define F_LPASS(f, s, div, m, n) \
121 { \
122 .freq_hz = (f), \
123 .src_clk = &s.c, \
124 .m_val = (m), \
125 .n_val = ~((n)-(m)) * !!(n), \
126 .d_val = ~(n),\
127 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
128 | BVAL(10, 8, s##_lpass_source_val), \
129 }
130
131#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \
132 { \
133 .freq_hz = (f), \
134 .l_val = (l), \
135 .m_val = (m), \
136 .n_val = (n), \
137 .pre_div_val = BVAL(12, 12, (pre_div)), \
138 .post_div_val = BVAL(9, 8, (post_div)), \
139 .vco_val = BVAL(29, 28, (vco)), \
140 }
141
142#define VDD_DIG_FMAX_MAP1(l1, f1) \
143 .vdd_class = &vdd_dig, \
144 .fmax = (unsigned long[VDD_DIG_NUM]) { \
145 [VDD_DIG_##l1] = (f1), \
146 }, \
147 .num_fmax = VDD_DIG_NUM
148
149#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
150 .vdd_class = &vdd_dig, \
151 .fmax = (unsigned long[VDD_DIG_NUM]) { \
152 [VDD_DIG_##l1] = (f1), \
153 [VDD_DIG_##l2] = (f2), \
154 }, \
155 .num_fmax = VDD_DIG_NUM
156
157#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
158 .vdd_class = &vdd_dig, \
159 .fmax = (unsigned long[VDD_DIG_NUM]) { \
160 [VDD_DIG_##l1] = (f1), \
161 [VDD_DIG_##l2] = (f2), \
162 [VDD_DIG_##l3] = (f3), \
163 }, \
164 .num_fmax = VDD_DIG_NUM
165
166enum vdd_dig_levels {
167 VDD_DIG_NONE,
168 VDD_DIG_LOW,
169 VDD_DIG_NOMINAL,
170 VDD_DIG_HIGH,
171 VDD_DIG_NUM
172};
173
Junjie Wubb5a79e2013-05-15 13:12:39 -0700[diff] [blame]174static int vdd_corner[] = {
175 RPM_REGULATOR_CORNER_NONE, /* VDD_DIG_NONE */
176 RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_DIG_LOW */
177 RPM_REGULATOR_CORNER_NORMAL, /* VDD_DIG_NOMINAL */
178 RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_DIG_HIGH */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]179};
180
Patrick Daly653c0b52013-04-16 17:18:28 -0700[diff] [blame]181static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]182
183#define RPM_MISC_CLK_TYPE 0x306b6c63
184#define RPM_BUS_CLK_TYPE 0x316b6c63
185#define RPM_MEM_CLK_TYPE 0x326b6c63
186
187#define RPM_SMD_KEY_ENABLE 0x62616E45
188
189#define CXO_ID 0x0
190#define QDSS_ID 0x1
191
192#define PNOC_ID 0x0
193#define SNOC_ID 0x1
194#define CNOC_ID 0x2
195#define MMSSNOC_AHB_ID 0x3
196
197#define BIMC_ID 0x0
198#define OXILI_ID 0x1
199#define OCMEM_ID 0x2
200
201#define D0_ID 1
202#define D1_ID 2
203#define A0_ID 4
204#define A1_ID 5
205#define A2_ID 6
206#define DIFF_CLK_ID 7
207#define DIV_CLK1_ID 11
208#define DIV_CLK2_ID 12
209
210DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL);
211DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
212DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL);
213DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE,
214 MMSSNOC_AHB_ID, NULL);
215
216DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
217DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID,
218 NULL);
219DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID,
220 NULL);
221
222DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk,
223 RPM_MISC_CLK_TYPE, CXO_ID, 19200000);
224DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
225
226DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID);
227DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID);
228DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID);
229DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID);
230DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID);
231DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID);
232DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID);
233DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID);
234
235DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID);
236DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID);
237DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID);
238DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID);
239DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID);
240
241struct measure_mux_entry {
242 struct clk *c;
243 int base;
244 u32 debug_mux;
245};
246
247static struct branch_clk oxilicx_axi_clk;
248
249#define MSS_DEBUG_CLOCK_CTL 0x0078
250#define LPASS_DEBUG_CLK_CTL 0x29000
251#define GLB_CLK_DIAG 0x01C
252#define GLB_TEST_BUS_SEL 0x020
253
254#define MMPLL0_PLL_MODE (0x0000)
255#define MMPLL0_PLL_L_VAL (0x0004)
256#define MMPLL0_PLL_M_VAL (0x0008)
257#define MMPLL0_PLL_N_VAL (0x000C)
258#define MMPLL0_PLL_USER_CTL (0x0010)
259#define MMPLL0_PLL_STATUS (0x001C)
260#define MMPLL1_PLL_MODE (0x0040)
261#define MMPLL1_PLL_L_VAL (0x0044)
262#define MMPLL1_PLL_M_VAL (0x0048)
263#define MMPLL1_PLL_N_VAL (0x004C)
264#define MMPLL1_PLL_USER_CTL (0x0050)
265#define MMPLL1_PLL_STATUS (0x005C)
266#define MMSS_PLL_VOTE_APCS (0x0100)
267#define VCODEC0_CMD_RCGR (0x1000)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]268#define VENUS0_BCR (0x1020)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]269#define VENUS0_VCODEC0_CBCR (0x1028)
270#define VENUS0_AHB_CBCR (0x1030)
271#define VENUS0_AXI_CBCR (0x1034)
272#define PCLK0_CMD_RCGR (0x2000)
273#define MDP_CMD_RCGR (0x2040)
274#define VSYNC_CMD_RCGR (0x2080)
275#define BYTE0_CMD_RCGR (0x2120)
276#define ESC0_CMD_RCGR (0x2160)
277#define MDSS_AHB_CBCR (0x2308)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]278#define MDSS_BCR (0x2300)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]279#define MDSS_AXI_CBCR (0x2310)
280#define MDSS_PCLK0_CBCR (0x2314)
281#define MDSS_MDP_CBCR (0x231C)
282#define MDSS_MDP_LUT_CBCR (0x2320)
283#define MDSS_VSYNC_CBCR (0x2328)
284#define MDSS_BYTE0_CBCR (0x233C)
285#define MDSS_ESC0_CBCR (0x2344)
286#define CSI0PHYTIMER_CMD_RCGR (0x3000)
287#define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024)
288#define CSI1PHYTIMER_CMD_RCGR (0x3030)
289#define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054)
290#define CSI0_CMD_RCGR (0x3090)
291#define CAMSS_CSI0_CBCR (0x30B4)
292#define CAMSS_CSI0_AHB_CBCR (0x30BC)
293#define CAMSS_CSI0PHY_CBCR (0x30C4)
294#define CAMSS_CSI0RDI_CBCR (0x30D4)
295#define CAMSS_CSI0PIX_CBCR (0x30E4)
296#define CSI1_CMD_RCGR (0x3100)
297#define CAMSS_CSI1_CBCR (0x3124)
298#define CAMSS_CSI1_AHB_CBCR (0x3128)
299#define CAMSS_CSI1PHY_CBCR (0x3134)
300#define CAMSS_CSI1RDI_CBCR (0x3144)
301#define CAMSS_CSI1PIX_CBCR (0x3154)
302#define CAMSS_ISPIF_AHB_CBCR (0x3224)
303#define CCI_CMD_RCGR (0x3300)
304#define CAMSS_CCI_CCI_CBCR (0x3344)
305#define CAMSS_CCI_CCI_AHB_CBCR (0x3348)
306#define MCLK0_CMD_RCGR (0x3360)
307#define CAMSS_MCLK0_CBCR (0x3384)
308#define MCLK1_CMD_RCGR (0x3390)
309#define CAMSS_MCLK1_CBCR (0x33B4)
310#define MMSS_GP0_CMD_RCGR (0x3420)
311#define CAMSS_GP0_CBCR (0x3444)
312#define MMSS_GP1_CMD_RCGR (0x3450)
313#define CAMSS_GP1_CBCR (0x3474)
314#define CAMSS_TOP_AHB_CBCR (0x3484)
315#define CAMSS_MICRO_AHB_CBCR (0x3494)
316#define JPEG0_CMD_RCGR (0x3500)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]317#define CAMSS_JPEG_BCR (0x35A0)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]318#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
319#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
320#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
321#define VFE0_CMD_RCGR (0x3600)
322#define CPP_CMD_RCGR (0x3640)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]323#define CAMSS_VFE_BCR (0x36A0)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]324#define CAMSS_VFE_VFE0_CBCR (0x36A8)
325#define CAMSS_VFE_CPP_CBCR (0x36B0)
326#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
327#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
328#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]329#define CAMSS_CSI_VFE0_BCR (0x3700)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]330#define CAMSS_CSI_VFE0_CBCR (0x3704)
331#define OXILI_GFX3D_CBCR (0x4028)
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]332#define OXILICX_BCR (0x4030)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]333#define OXILICX_AXI_CBCR (0x4038)
334#define OXILICX_AHB_CBCR (0x403C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]335#define MMPLL2_PLL_MODE (0x4100)
336#define MMPLL2_PLL_STATUS (0x411C)
337#define MMSS_MMSSNOC_AHB_CBCR (0x5024)
338#define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028)
339#define MMSS_MISC_AHB_CBCR (0x502C)
340#define AXI_CMD_RCGR (0x5040)
341#define MMSS_S0_AXI_CBCR (0x5064)
342#define MMSS_MMSSNOC_AXI_CBCR (0x506C)
343#define MMSS_DEBUG_CLK_CTL (0x0900)
344#define GPLL0_MODE (0x0000)
345#define GPLL0_L_VAL (0x0004)
346#define GPLL0_M_VAL (0x0008)
347#define GPLL0_N_VAL (0x000C)
348#define GPLL0_USER_CTL (0x0010)
349#define GPLL0_STATUS (0x001C)
350#define GPLL1_MODE (0x0040)
351#define GPLL1_L_VAL (0x0044)
352#define GPLL1_M_VAL (0x0048)
353#define GPLL1_N_VAL (0x004C)
354#define GPLL1_USER_CTL (0x0050)
355#define GPLL1_STATUS (0x005C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]356#define NOC_CONF_XPU_AHB_CBCR (0x01C0)
357#define MMSS_NOC_CFG_AHB_CBCR (0x024C)
358#define MSS_CFG_AHB_CBCR (0x0280)
359#define MSS_Q6_BIMC_AXI_CBCR (0x0284)
360#define USB_HS_HSIC_BCR (0x0400)
361#define USB_HSIC_AHB_CBCR (0x0408)
362#define USB_HSIC_SYSTEM_CMD_RCGR (0x041C)
363#define USB_HSIC_SYSTEM_CBCR (0x040C)
364#define USB_HSIC_CMD_RCGR (0x0440)
365#define USB_HSIC_CBCR (0x0410)
366#define USB_HSIC_IO_CAL_CMD_RCGR (0x0458)
367#define USB_HSIC_IO_CAL_CBCR (0x0414)
368#define USB_HS_BCR (0x0480)
369#define USB_HS_SYSTEM_CBCR (0x0484)
370#define USB_HS_AHB_CBCR (0x0488)
371#define USB_HS_SYSTEM_CMD_RCGR (0x0490)
372#define USB2A_PHY_SLEEP_CBCR (0x04AC)
373#define SDCC1_APPS_CMD_RCGR (0x04D0)
374#define SDCC1_APPS_CBCR (0x04C4)
375#define SDCC1_AHB_CBCR (0x04C8)
376#define SDCC2_APPS_CMD_RCGR (0x0510)
377#define SDCC2_APPS_CBCR (0x0504)
378#define SDCC2_AHB_CBCR (0x0508)
379#define SDCC3_APPS_CMD_RCGR (0x0550)
380#define SDCC3_APPS_CBCR (0x0544)
381#define SDCC3_AHB_CBCR (0x0548)
382#define BLSP1_AHB_CBCR (0x05C4)
383#define BLSP1_QUP1_SPI_APPS_CBCR (0x0644)
384#define BLSP1_QUP1_I2C_APPS_CBCR (0x0648)
385#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660)
386#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0)
387#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760)
388#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0)
389#define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860)
390#define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0)
391#define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C)
392#define BLSP1_UART1_APPS_CBCR (0x0684)
393#define BLSP1_UART1_APPS_CMD_RCGR (0x068C)
394#define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4)
395#define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8)
396#define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC)
397#define BLSP1_UART2_APPS_CBCR (0x0704)
398#define BLSP1_UART2_APPS_CMD_RCGR (0x070C)
399#define BLSP1_QUP3_SPI_APPS_CBCR (0x0744)
400#define BLSP1_QUP3_I2C_APPS_CBCR (0x0748)
401#define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C)
402#define BLSP1_UART3_APPS_CBCR (0x0784)
403#define BLSP1_UART3_APPS_CMD_RCGR (0x078C)
404#define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4)
405#define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8)
406#define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC)
407#define BLSP1_UART4_APPS_CBCR (0x0804)
408#define BLSP1_UART4_APPS_CMD_RCGR (0x080C)
409#define BLSP1_QUP5_SPI_APPS_CBCR (0x0844)
410#define BLSP1_QUP5_I2C_APPS_CBCR (0x0848)
411#define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C)
412#define BLSP1_UART5_APPS_CBCR (0x0884)
413#define BLSP1_UART5_APPS_CMD_RCGR (0x088C)
414#define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4)
415#define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8)
416#define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC)
417#define BLSP1_UART6_APPS_CBCR (0x0904)
418#define BLSP1_UART6_APPS_CMD_RCGR (0x090C)
419#define PDM_AHB_CBCR (0x0CC4)
420#define PDM_XO4_CBCR (0x0CC8)
421#define PDM2_CBCR (0x0CCC)
422#define PDM2_CMD_RCGR (0x0CD0)
423#define PRNG_AHB_CBCR (0x0D04)
424#define BAM_DMA_AHB_CBCR (0x0D44)
425#define BOOT_ROM_AHB_CBCR (0x0E04)
426#define CE1_CMD_RCGR (0x1050)
427#define CE1_CBCR (0x1044)
428#define CE1_AXI_CBCR (0x1048)
429#define CE1_AHB_CBCR (0x104C)
430#define GCC_XO_DIV4_CBCR (0x10C8)
431#define LPASS_Q6_AXI_CBCR (0x11C0)
432#define APCS_GPLL_ENA_VOTE (0x1480)
433#define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484)
434#define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488)
435#define GCC_DEBUG_CLK_CTL (0x1880)
436#define CLOCK_FRQ_MEASURE_CTL (0x1884)
437#define CLOCK_FRQ_MEASURE_STATUS (0x1888)
438#define PLLTEST_PAD_CFG (0x188C)
439#define GP1_CBCR (0x1900)
440#define GP1_CMD_RCGR (0x1904)
441#define GP2_CBCR (0x1940)
442#define GP2_CMD_RCGR (0x1944)
443#define GP3_CBCR (0x1980)
444#define GP3_CMD_RCGR (0x1984)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]445#define Q6SS_BCR (0x6000)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]446#define Q6SS_AHB_LFABIF_CBCR (0x22000)
447#define Q6SS_AHBM_CBCR (0x22004)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]448#define Q6SS_XO_CBCR (0x26000)
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]449#define KPSS_AHB_CMD_RCGR (0x120C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]450
451static unsigned int soft_vote_gpll0;
452
453static struct pll_vote_clk gpll0 = {
454 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
455 .en_mask = BIT(0),
456 .status_reg = (void __iomem *)GPLL0_STATUS,
457 .status_mask = BIT(17),
458 .soft_vote = &soft_vote_gpll0,
459 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
460 .base = &virt_bases[GCC_BASE],
461 .c = {
462 .rate = 600000000,
463 .parent = &xo.c,
464 .dbg_name = "gpll0",
465 .ops = &clk_ops_pll_acpu_vote,
466 CLK_INIT(gpll0.c),
467 },
468};
469
470/*Don't vote for xo if using this clock to allow xo shutdown*/
471static struct pll_vote_clk gpll0_ao = {
472 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
473 .en_mask = BIT(0),
474 .status_reg = (void __iomem *)GPLL0_STATUS,
475 .status_mask = BIT(17),
476 .soft_vote = &soft_vote_gpll0,
477 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
478 .base = &virt_bases[GCC_BASE],
479 .c = {
480 .rate = 600000000,
481 .dbg_name = "gpll0_ao",
482 .ops = &clk_ops_pll_acpu_vote,
483 CLK_INIT(gpll0_ao.c),
484 },
485};
486
487static struct pll_vote_clk gpll1 = {
488 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
489 .en_mask = BIT(1),
490 .status_reg = (void __iomem *)GPLL1_STATUS,
491 .status_mask = BIT(17),
492 .base = &virt_bases[GCC_BASE],
493 .c = {
494 .rate = 480000000,
495 .parent = &xo.c,
496 .dbg_name = "gpll1",
497 .ops = &clk_ops_pll_vote,
498 CLK_INIT(gpll1.c),
499 },
500};
501
502static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]503 F_GCC( 19200000, xo, 1, 0, 0),
504 F_GCC( 50000000, gpll0, 12, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]505 F_END
506};
507
508static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
509 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
510 .set_rate = set_rate_hid,
511 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
512 .current_freq = &rcg_dummy_freq,
513 .base = &virt_bases[GCC_BASE],
514 .c = {
515 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
516 .ops = &clk_ops_rcg,
517 VDD_DIG_FMAX_MAP1(LOW, 50000000),
518 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
519 },
520};
521
522static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
523 F_GCC( 960000, xo, 10, 1, 2),
524 F_GCC( 4800000, xo, 4, 0, 0),
525 F_GCC( 9600000, xo, 2, 0, 0),
526 F_GCC( 15000000, gpll0, 10, 1, 4),
527 F_GCC( 19200000, xo, 1, 0, 0),
528 F_GCC( 25000000, gpll0, 12, 1, 2),
529 F_GCC( 50000000, gpll0, 12, 0, 0),
530 F_END
531};
532
533static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
534 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
535 .set_rate = set_rate_mnd,
536 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
537 .current_freq = &rcg_dummy_freq,
538 .base = &virt_bases[GCC_BASE],
539 .c = {
540 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
541 .ops = &clk_ops_rcg_mnd,
542 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
543 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
544 },
545};
546
547static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
548 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
549 .set_rate = set_rate_hid,
550 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
551 .current_freq = &rcg_dummy_freq,
552 .base = &virt_bases[GCC_BASE],
553 .c = {
554 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
555 .ops = &clk_ops_rcg,
556 VDD_DIG_FMAX_MAP1(LOW, 50000000),
557 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
558 },
559};
560
561static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
562 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
563 .set_rate = set_rate_mnd,
564 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
565 .current_freq = &rcg_dummy_freq,
566 .base = &virt_bases[GCC_BASE],
567 .c = {
568 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
569 .ops = &clk_ops_rcg_mnd,
570 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
571 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
572 },
573};
574
575static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
576 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
577 .set_rate = set_rate_hid,
578 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
579 .current_freq = &rcg_dummy_freq,
580 .base = &virt_bases[GCC_BASE],
581 .c = {
582 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
583 .ops = &clk_ops_rcg,
584 VDD_DIG_FMAX_MAP1(LOW, 50000000),
585 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
586 },
587};
588
589static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
590 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
591 .set_rate = set_rate_mnd,
592 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
593 .current_freq = &rcg_dummy_freq,
594 .base = &virt_bases[GCC_BASE],
595 .c = {
596 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
597 .ops = &clk_ops_rcg_mnd,
598 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
599 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
600 },
601};
602
603static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
604 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
605 .set_rate = set_rate_hid,
606 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
607 .current_freq = &rcg_dummy_freq,
608 .base = &virt_bases[GCC_BASE],
609 .c = {
610 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
611 .ops = &clk_ops_rcg,
612 VDD_DIG_FMAX_MAP1(LOW, 50000000),
613 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
614 },
615};
616
617static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
618 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
619 .set_rate = set_rate_mnd,
620 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
621 .current_freq = &rcg_dummy_freq,
622 .base = &virt_bases[GCC_BASE],
623 .c = {
624 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
625 .ops = &clk_ops_rcg_mnd,
626 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
627 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
628 },
629};
630
631static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
632 .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR,
633 .set_rate = set_rate_hid,
634 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
635 .current_freq = &rcg_dummy_freq,
636 .base = &virt_bases[GCC_BASE],
637 .c = {
638 .dbg_name = "blsp1_qup5_i2c_apps_clk_src",
639 .ops = &clk_ops_rcg,
640 VDD_DIG_FMAX_MAP1(LOW, 50000000),
641 CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
642 },
643};
644
645static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
646 .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR,
647 .set_rate = set_rate_mnd,
648 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
649 .current_freq = &rcg_dummy_freq,
650 .base = &virt_bases[GCC_BASE],
651 .c = {
652 .dbg_name = "blsp1_qup5_spi_apps_clk_src",
653 .ops = &clk_ops_rcg_mnd,
654 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
655 CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
656 },
657};
658
659static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
660 .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR,
661 .set_rate = set_rate_hid,
662 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
663 .current_freq = &rcg_dummy_freq,
664 .base = &virt_bases[GCC_BASE],
665 .c = {
666 .dbg_name = "blsp1_qup6_i2c_apps_clk_src",
667 .ops = &clk_ops_rcg,
668 VDD_DIG_FMAX_MAP1(LOW, 50000000),
669 CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
670 },
671};
672
673static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
674 .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR,
675 .set_rate = set_rate_mnd,
676 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
677 .current_freq = &rcg_dummy_freq,
678 .base = &virt_bases[GCC_BASE],
679 .c = {
680 .dbg_name = "blsp1_qup6_spi_apps_clk_src",
681 .ops = &clk_ops_rcg_mnd,
682 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
683 CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
684 },
685};
686
687static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
688 F_GCC( 3686400, gpll0, 1, 96, 15625),
689 F_GCC( 7372800, gpll0, 1, 192, 15625),
690 F_GCC( 14745600, gpll0, 1, 384, 15625),
691 F_GCC( 16000000, gpll0, 5, 2, 15),
692 F_GCC( 19200000, xo, 1, 0, 0),
693 F_GCC( 24000000, gpll0, 5, 1, 5),
694 F_GCC( 32000000, gpll0, 1, 4, 75),
695 F_GCC( 40000000, gpll0, 15, 0, 0),
696 F_GCC( 46400000, gpll0, 1, 29, 375),
697 F_GCC( 48000000, gpll0, 12.5, 0, 0),
698 F_GCC( 51200000, gpll0, 1, 32, 375),
699 F_GCC( 56000000, gpll0, 1, 7, 75),
700 F_GCC( 58982400, gpll0, 1, 1536, 15625),
701 F_GCC( 60000000, gpll0, 10, 0, 0),
702 F_END
703};
704
705static struct rcg_clk blsp1_uart1_apps_clk_src = {
706 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
707 .set_rate = set_rate_mnd,
708 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
709 .current_freq = &rcg_dummy_freq,
710 .base = &virt_bases[GCC_BASE],
711 .c = {
712 .dbg_name = "blsp1_uart1_apps_clk_src",
713 .ops = &clk_ops_rcg_mnd,
714 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
715 CLK_INIT(blsp1_uart1_apps_clk_src.c),
716 },
717};
718
719static struct rcg_clk blsp1_uart2_apps_clk_src = {
720 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
721 .set_rate = set_rate_mnd,
722 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
723 .current_freq = &rcg_dummy_freq,
724 .base = &virt_bases[GCC_BASE],
725 .c = {
726 .dbg_name = "blsp1_uart2_apps_clk_src",
727 .ops = &clk_ops_rcg_mnd,
728 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
729 CLK_INIT(blsp1_uart2_apps_clk_src.c),
730 },
731};
732
733static struct rcg_clk blsp1_uart3_apps_clk_src = {
734 .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR,
735 .set_rate = set_rate_mnd,
736 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
737 .current_freq = &rcg_dummy_freq,
738 .base = &virt_bases[GCC_BASE],
739 .c = {
740 .dbg_name = "blsp1_uart3_apps_clk_src",
741 .ops = &clk_ops_rcg_mnd,
742 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
743 CLK_INIT(blsp1_uart3_apps_clk_src.c),
744 },
745};
746
747static struct rcg_clk blsp1_uart4_apps_clk_src = {
748 .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR,
749 .set_rate = set_rate_mnd,
750 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
751 .current_freq = &rcg_dummy_freq,
752 .base = &virt_bases[GCC_BASE],
753 .c = {
754 .dbg_name = "blsp1_uart4_apps_clk_src",
755 .ops = &clk_ops_rcg_mnd,
756 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
757 CLK_INIT(blsp1_uart4_apps_clk_src.c),
758 },
759};
760
761static struct rcg_clk blsp1_uart5_apps_clk_src = {
762 .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR,
763 .set_rate = set_rate_mnd,
764 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
765 .current_freq = &rcg_dummy_freq,
766 .base = &virt_bases[GCC_BASE],
767 .c = {
768 .dbg_name = "blsp1_uart5_apps_clk_src",
769 .ops = &clk_ops_rcg_mnd,
770 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
771 CLK_INIT(blsp1_uart5_apps_clk_src.c),
772 },
773};
774
775static struct rcg_clk blsp1_uart6_apps_clk_src = {
776 .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR,
777 .set_rate = set_rate_mnd,
778 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
779 .current_freq = &rcg_dummy_freq,
780 .base = &virt_bases[GCC_BASE],
781 .c = {
782 .dbg_name = "blsp1_uart6_apps_clk_src",
783 .ops = &clk_ops_rcg_mnd,
784 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
785 CLK_INIT(blsp1_uart6_apps_clk_src.c),
786 },
787};
788
789static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
790 F_GCC( 50000000, gpll0, 12, 0, 0),
791 F_GCC( 100000000, gpll0, 6, 0, 0),
792 F_END
793};
794
795static struct rcg_clk ce1_clk_src = {
796 .cmd_rcgr_reg = CE1_CMD_RCGR,
797 .set_rate = set_rate_hid,
798 .freq_tbl = ftbl_gcc_ce1_clk,
799 .current_freq = &rcg_dummy_freq,
800 .base = &virt_bases[GCC_BASE],
801 .c = {
802 .dbg_name = "ce1_clk_src",
803 .ops = &clk_ops_rcg,
804 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
805 CLK_INIT(ce1_clk_src.c),
806 },
807};
808
809static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
810 F_GCC( 19200000, xo, 1, 0, 0),
811 F_END
812};
813
814static struct rcg_clk gp1_clk_src = {
815 .cmd_rcgr_reg = GP1_CMD_RCGR,
816 .set_rate = set_rate_mnd,
817 .freq_tbl = ftbl_gcc_gp1_3_clk,
818 .current_freq = &rcg_dummy_freq,
819 .base = &virt_bases[GCC_BASE],
820 .c = {
821 .dbg_name = "gp1_clk_src",
822 .ops = &clk_ops_rcg_mnd,
823 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
824 CLK_INIT(gp1_clk_src.c),
825 },
826};
827
828static struct rcg_clk gp2_clk_src = {
829 .cmd_rcgr_reg = GP2_CMD_RCGR,
830 .set_rate = set_rate_mnd,
831 .freq_tbl = ftbl_gcc_gp1_3_clk,
832 .current_freq = &rcg_dummy_freq,
833 .base = &virt_bases[GCC_BASE],
834 .c = {
835 .dbg_name = "gp2_clk_src",
836 .ops = &clk_ops_rcg_mnd,
837 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
838 CLK_INIT(gp2_clk_src.c),
839 },
840};
841
842static struct rcg_clk gp3_clk_src = {
843 .cmd_rcgr_reg = GP3_CMD_RCGR,
844 .set_rate = set_rate_mnd,
845 .freq_tbl = ftbl_gcc_gp1_3_clk,
846 .current_freq = &rcg_dummy_freq,
847 .base = &virt_bases[GCC_BASE],
848 .c = {
849 .dbg_name = "gp3_clk_src",
850 .ops = &clk_ops_rcg_mnd,
851 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
852 CLK_INIT(gp3_clk_src.c),
853 },
854};
855
856static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
857 F_GCC( 60000000, gpll0, 10, 0, 0),
858 F_END
859};
860
861static struct rcg_clk pdm2_clk_src = {
862 .cmd_rcgr_reg = PDM2_CMD_RCGR,
863 .set_rate = set_rate_hid,
864 .freq_tbl = ftbl_gcc_pdm2_clk,
865 .current_freq = &rcg_dummy_freq,
866 .base = &virt_bases[GCC_BASE],
867 .c = {
868 .dbg_name = "pdm2_clk_src",
869 .ops = &clk_ops_rcg,
870 VDD_DIG_FMAX_MAP1(LOW, 60000000),
871 CLK_INIT(pdm2_clk_src.c),
872 },
873};
874
875static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = {
876 F_GCC( 144000, xo, 16, 3, 25),
877 F_GCC( 400000, xo, 12, 1, 4),
878 F_GCC( 20000000, gpll0, 15, 1, 2),
879 F_GCC( 25000000, gpll0, 12, 1, 2),
880 F_GCC( 50000000, gpll0, 12, 0, 0),
881 F_GCC( 100000000, gpll0, 6, 0, 0),
882 F_GCC( 200000000, gpll0, 3, 0, 0),
883 F_END
884};
885
886static struct rcg_clk sdcc1_apps_clk_src = {
887 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
888 .set_rate = set_rate_mnd,
889 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
890 .current_freq = &rcg_dummy_freq,
891 .base = &virt_bases[GCC_BASE],
892 .c = {
893 .dbg_name = "sdcc1_apps_clk_src",
894 .ops = &clk_ops_rcg_mnd,
895 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
896 CLK_INIT(sdcc1_apps_clk_src.c),
897 },
898};
899
900static struct rcg_clk sdcc2_apps_clk_src = {
901 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
902 .set_rate = set_rate_mnd,
903 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
904 .current_freq = &rcg_dummy_freq,
905 .base = &virt_bases[GCC_BASE],
906 .c = {
907 .dbg_name = "sdcc2_apps_clk_src",
908 .ops = &clk_ops_rcg_mnd,
909 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
910 CLK_INIT(sdcc2_apps_clk_src.c),
911 },
912};
913
914static struct rcg_clk sdcc3_apps_clk_src = {
915 .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,
916 .set_rate = set_rate_mnd,
917 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
918 .current_freq = &rcg_dummy_freq,
919 .base = &virt_bases[GCC_BASE],
920 .c = {
921 .dbg_name = "sdcc3_apps_clk_src",
922 .ops = &clk_ops_rcg_mnd,
923 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
924 CLK_INIT(sdcc3_apps_clk_src.c),
925 },
926};
927
928static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
929 F_GCC( 75000000, gpll0, 8, 0, 0),
930 F_END
931};
932
933static struct rcg_clk usb_hs_system_clk_src = {
934 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
935 .set_rate = set_rate_hid,
936 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
937 .current_freq = &rcg_dummy_freq,
938 .base = &virt_bases[GCC_BASE],
939 .c = {
940 .dbg_name = "usb_hs_system_clk_src",
941 .ops = &clk_ops_rcg,
942 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
943 CLK_INIT(usb_hs_system_clk_src.c),
944 },
945};
946
947static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = {
948 F_HSIC( 480000000, gpll1, 0, 0, 0),
949 F_END
950};
951
952static struct rcg_clk usb_hsic_clk_src = {
953 .cmd_rcgr_reg = USB_HSIC_CMD_RCGR,
954 .set_rate = set_rate_hid,
955 .freq_tbl = ftbl_gcc_usb_hsic_clk,
956 .current_freq = &rcg_dummy_freq,
957 .base = &virt_bases[GCC_BASE],
958 .c = {
959 .dbg_name = "usb_hsic_clk_src",
960 .ops = &clk_ops_rcg,
961 VDD_DIG_FMAX_MAP1(LOW, 480000000),
962 CLK_INIT(usb_hsic_clk_src.c),
963 },
964};
965
966static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
967 F_GCC( 9600000, xo, 2, 0, 0),
968 F_END
969};
970
971static struct rcg_clk usb_hsic_io_cal_clk_src = {
972 .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR,
973 .set_rate = set_rate_hid,
974 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
975 .current_freq = &rcg_dummy_freq,
976 .base = &virt_bases[GCC_BASE],
977 .c = {
978 .dbg_name = "usb_hsic_io_cal_clk_src",
979 .ops = &clk_ops_rcg,
980 VDD_DIG_FMAX_MAP1(LOW, 9600000),
981 CLK_INIT(usb_hsic_io_cal_clk_src.c),
982 },
983};
984
985static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
986 F_GCC( 75000000, gpll0, 8, 0, 0),
987 F_END
988};
989
990static struct rcg_clk usb_hsic_system_clk_src = {
991 .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR,
992 .set_rate = set_rate_hid,
993 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
994 .current_freq = &rcg_dummy_freq,
995 .base = &virt_bases[GCC_BASE],
996 .c = {
997 .dbg_name = "usb_hsic_system_clk_src",
998 .ops = &clk_ops_rcg,
999 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
1000 CLK_INIT(usb_hsic_system_clk_src.c),
1001 },
1002};
1003
1004static struct local_vote_clk gcc_bam_dma_ahb_clk = {
1005 .cbcr_reg = BAM_DMA_AHB_CBCR,
1006 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1007 .en_mask = BIT(12),
1008 .base = &virt_bases[GCC_BASE],
1009 .c = {
1010 .dbg_name = "gcc_bam_dma_ahb_clk",
1011 .ops = &clk_ops_vote,
1012 CLK_INIT(gcc_bam_dma_ahb_clk.c),
1013 },
1014};
1015
1016static struct local_vote_clk gcc_blsp1_ahb_clk = {
1017 .cbcr_reg = BLSP1_AHB_CBCR,
1018 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1019 .en_mask = BIT(17),
1020 .base = &virt_bases[GCC_BASE],
1021 .c = {
1022 .dbg_name = "gcc_blsp1_ahb_clk",
1023 .ops = &clk_ops_vote,
1024 CLK_INIT(gcc_blsp1_ahb_clk.c),
1025 },
1026};
1027
1028static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1029 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1030 .has_sibling = 0,
1031 .base = &virt_bases[GCC_BASE],
1032 .c = {
1033 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1034 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1035 .ops = &clk_ops_branch,
1036 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1037 },
1038};
1039
1040static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1041 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1042 .has_sibling = 0,
1043 .base = &virt_bases[GCC_BASE],
1044 .c = {
1045 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1046 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1047 .ops = &clk_ops_branch,
1048 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1049 },
1050};
1051
1052static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1053 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1054 .has_sibling = 0,
1055 .base = &virt_bases[GCC_BASE],
1056 .c = {
1057 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1058 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1059 .ops = &clk_ops_branch,
1060 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1061 },
1062};
1063
1064static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1065 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1066 .has_sibling = 0,
1067 .base = &virt_bases[GCC_BASE],
1068 .c = {
1069 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1070 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1071 .ops = &clk_ops_branch,
1072 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1073 },
1074};
1075
1076static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1077 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1078 .has_sibling = 0,
1079 .base = &virt_bases[GCC_BASE],
1080 .c = {
1081 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1082 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1083 .ops = &clk_ops_branch,
1084 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1085 },
1086};
1087
1088static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1089 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1090 .has_sibling = 0,
1091 .base = &virt_bases[GCC_BASE],
1092 .c = {
1093 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1094 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1095 .ops = &clk_ops_branch,
1096 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1097 },
1098};
1099
1100static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
1101 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
1102 .has_sibling = 0,
1103 .base = &virt_bases[GCC_BASE],
1104 .c = {
1105 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
1106 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
1107 .ops = &clk_ops_branch,
1108 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
1109 },
1110};
1111
1112static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
1113 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
1114 .has_sibling = 0,
1115 .base = &virt_bases[GCC_BASE],
1116 .c = {
1117 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
1118 .parent = &blsp1_qup4_spi_apps_clk_src.c,
1119 .ops = &clk_ops_branch,
1120 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
1121 },
1122};
1123
1124static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
1125 .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
1126 .has_sibling = 0,
1127 .base = &virt_bases[GCC_BASE],
1128 .c = {
1129 .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
1130 .parent = &blsp1_qup5_i2c_apps_clk_src.c,
1131 .ops = &clk_ops_branch,
1132 CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
1133 },
1134};
1135
1136static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
1137 .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
1138 .has_sibling = 0,
1139 .base = &virt_bases[GCC_BASE],
1140 .c = {
1141 .dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
1142 .parent = &blsp1_qup5_spi_apps_clk_src.c,
1143 .ops = &clk_ops_branch,
1144 CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
1145 },
1146};
1147
1148static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
1149 .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
1150 .has_sibling = 0,
1151 .base = &virt_bases[GCC_BASE],
1152 .c = {
1153 .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
1154 .parent = &blsp1_qup6_i2c_apps_clk_src.c,
1155 .ops = &clk_ops_branch,
1156 CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
1157 },
1158};
1159
1160static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
1161 .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
1162 .has_sibling = 0,
1163 .base = &virt_bases[GCC_BASE],
1164 .c = {
1165 .dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
1166 .parent = &blsp1_qup6_spi_apps_clk_src.c,
1167 .ops = &clk_ops_branch,
1168 CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
1169 },
1170};
1171
1172static struct branch_clk gcc_blsp1_uart1_apps_clk = {
1173 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
1174 .has_sibling = 0,
1175 .base = &virt_bases[GCC_BASE],
1176 .c = {
1177 .dbg_name = "gcc_blsp1_uart1_apps_clk",
1178 .parent = &blsp1_uart1_apps_clk_src.c,
1179 .ops = &clk_ops_branch,
1180 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
1181 },
1182};
1183
1184static struct branch_clk gcc_blsp1_uart2_apps_clk = {
1185 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
1186 .has_sibling = 0,
1187 .base = &virt_bases[GCC_BASE],
1188 .c = {
1189 .dbg_name = "gcc_blsp1_uart2_apps_clk",
1190 .parent = &blsp1_uart2_apps_clk_src.c,
1191 .ops = &clk_ops_branch,
1192 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
1193 },
1194};
1195
1196static struct branch_clk gcc_blsp1_uart3_apps_clk = {
1197 .cbcr_reg = BLSP1_UART3_APPS_CBCR,
1198 .has_sibling = 0,
1199 .base = &virt_bases[GCC_BASE],
1200 .c = {
1201 .dbg_name = "gcc_blsp1_uart3_apps_clk",
1202 .parent = &blsp1_uart3_apps_clk_src.c,
1203 .ops = &clk_ops_branch,
1204 CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
1205 },
1206};
1207
1208static struct branch_clk gcc_blsp1_uart4_apps_clk = {
1209 .cbcr_reg = BLSP1_UART4_APPS_CBCR,
1210 .has_sibling = 0,
1211 .base = &virt_bases[GCC_BASE],
1212 .c = {
1213 .dbg_name = "gcc_blsp1_uart4_apps_clk",
1214 .parent = &blsp1_uart4_apps_clk_src.c,
1215 .ops = &clk_ops_branch,
1216 CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
1217 },
1218};
1219
1220static struct branch_clk gcc_blsp1_uart5_apps_clk = {
1221 .cbcr_reg = BLSP1_UART5_APPS_CBCR,
1222 .has_sibling = 0,
1223 .base = &virt_bases[GCC_BASE],
1224 .c = {
1225 .dbg_name = "gcc_blsp1_uart5_apps_clk",
1226 .parent = &blsp1_uart5_apps_clk_src.c,
1227 .ops = &clk_ops_branch,
1228 CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
1229 },
1230};
1231
1232static struct branch_clk gcc_blsp1_uart6_apps_clk = {
1233 .cbcr_reg = BLSP1_UART6_APPS_CBCR,
1234 .has_sibling = 0,
1235 .base = &virt_bases[GCC_BASE],
1236 .c = {
1237 .dbg_name = "gcc_blsp1_uart6_apps_clk",
1238 .parent = &blsp1_uart6_apps_clk_src.c,
1239 .ops = &clk_ops_branch,
1240 CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
1241 },
1242};
1243
1244static struct local_vote_clk gcc_boot_rom_ahb_clk = {
1245 .cbcr_reg = BOOT_ROM_AHB_CBCR,
1246 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1247 .en_mask = BIT(10),
1248 .base = &virt_bases[GCC_BASE],
1249 .c = {
1250 .dbg_name = "gcc_boot_rom_ahb_clk",
1251 .ops = &clk_ops_vote,
1252 CLK_INIT(gcc_boot_rom_ahb_clk.c),
1253 },
1254};
1255
1256static struct local_vote_clk gcc_ce1_ahb_clk = {
1257 .cbcr_reg = CE1_AHB_CBCR,
1258 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1259 .en_mask = BIT(3),
1260 .base = &virt_bases[GCC_BASE],
1261 .c = {
1262 .dbg_name = "gcc_ce1_ahb_clk",
1263 .ops = &clk_ops_vote,
1264 CLK_INIT(gcc_ce1_ahb_clk.c),
1265 },
1266};
1267
1268static struct local_vote_clk gcc_ce1_axi_clk = {
1269 .cbcr_reg = CE1_AXI_CBCR,
1270 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1271 .en_mask = BIT(4),
1272 .base = &virt_bases[GCC_BASE],
1273 .c = {
1274 .dbg_name = "gcc_ce1_axi_clk",
1275 .ops = &clk_ops_vote,
1276 CLK_INIT(gcc_ce1_axi_clk.c),
1277 },
1278};
1279
1280static struct local_vote_clk gcc_ce1_clk = {
1281 .cbcr_reg = CE1_CBCR,
1282 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1283 .en_mask = BIT(5),
1284 .base = &virt_bases[GCC_BASE],
1285 .c = {
1286 .dbg_name = "gcc_ce1_clk",
1287 .ops = &clk_ops_vote,
1288 CLK_INIT(gcc_ce1_clk.c),
1289 },
1290};
1291
1292static struct branch_clk gcc_gp1_clk = {
1293 .cbcr_reg = GP1_CBCR,
1294 .has_sibling = 0,
1295 .base = &virt_bases[GCC_BASE],
1296 .c = {
1297 .dbg_name = "gcc_gp1_clk",
1298 .parent = &gp1_clk_src.c,
1299 .ops = &clk_ops_branch,
1300 CLK_INIT(gcc_gp1_clk.c),
1301 },
1302};
1303
1304static struct branch_clk gcc_gp2_clk = {
1305 .cbcr_reg = GP2_CBCR,
1306 .has_sibling = 0,
1307 .base = &virt_bases[GCC_BASE],
1308 .c = {
1309 .dbg_name = "gcc_gp2_clk",
1310 .parent = &gp2_clk_src.c,
1311 .ops = &clk_ops_branch,
1312 CLK_INIT(gcc_gp2_clk.c),
1313 },
1314};
1315
1316static struct branch_clk gcc_gp3_clk = {
1317 .cbcr_reg = GP3_CBCR,
1318 .has_sibling = 0,
1319 .base = &virt_bases[GCC_BASE],
1320 .c = {
1321 .dbg_name = "gcc_gp3_clk",
1322 .parent = &gp3_clk_src.c,
1323 .ops = &clk_ops_branch,
1324 CLK_INIT(gcc_gp3_clk.c),
1325 },
1326};
1327
1328static struct branch_clk gcc_lpass_q6_axi_clk = {
1329 .cbcr_reg = LPASS_Q6_AXI_CBCR,
1330 .has_sibling = 1,
1331 .base = &virt_bases[GCC_BASE],
1332 .c = {
1333 .dbg_name = "gcc_lpass_q6_axi_clk",
1334 .ops = &clk_ops_branch,
1335 CLK_INIT(gcc_lpass_q6_axi_clk.c),
1336 },
1337};
1338
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1339static struct branch_clk gcc_mss_cfg_ahb_clk = {
1340 .cbcr_reg = MSS_CFG_AHB_CBCR,
1341 .has_sibling = 1,
1342 .base = &virt_bases[GCC_BASE],
1343 .c = {
1344 .dbg_name = "gcc_mss_cfg_ahb_clk",
1345 .ops = &clk_ops_branch,
1346 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
1347 },
1348};
1349
1350static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
1351 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
1352 .has_sibling = 1,
1353 .base = &virt_bases[GCC_BASE],
1354 .c = {
1355 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
1356 .ops = &clk_ops_branch,
1357 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
1358 },
1359};
1360
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1361static struct branch_clk gcc_pdm2_clk = {
1362 .cbcr_reg = PDM2_CBCR,
1363 .has_sibling = 0,
1364 .base = &virt_bases[GCC_BASE],
1365 .c = {
1366 .dbg_name = "gcc_pdm2_clk",
1367 .parent = &pdm2_clk_src.c,
1368 .ops = &clk_ops_branch,
1369 CLK_INIT(gcc_pdm2_clk.c),
1370 },
1371};
1372
1373static struct branch_clk gcc_pdm_ahb_clk = {
1374 .cbcr_reg = PDM_AHB_CBCR,
1375 .has_sibling = 1,
1376 .base = &virt_bases[GCC_BASE],
1377 .c = {
1378 .dbg_name = "gcc_pdm_ahb_clk",
1379 .ops = &clk_ops_branch,
1380 CLK_INIT(gcc_pdm_ahb_clk.c),
1381 },
1382};
1383
1384static struct branch_clk gcc_pdm_xo4_clk = {
1385 .cbcr_reg = PDM_XO4_CBCR,
1386 .has_sibling = 1,
1387 .base = &virt_bases[GCC_BASE],
1388 .c = {
1389 .dbg_name = "gcc_pdm_xo4_clk",
1390 .parent = &xo.c,
1391 .ops = &clk_ops_branch,
1392 CLK_INIT(gcc_pdm_xo4_clk.c),
1393 },
1394};
1395
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1396static struct local_vote_clk gcc_prng_ahb_clk = {
1397 .cbcr_reg = PRNG_AHB_CBCR,
1398 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1399 .en_mask = BIT(13),
1400 .base = &virt_bases[GCC_BASE],
1401 .c = {
1402 .dbg_name = "gcc_prng_ahb_clk",
1403 .ops = &clk_ops_vote,
1404 CLK_INIT(gcc_prng_ahb_clk.c),
1405 },
1406};
1407
1408static struct branch_clk gcc_sdcc1_ahb_clk = {
1409 .cbcr_reg = SDCC1_AHB_CBCR,
1410 .has_sibling = 1,
1411 .base = &virt_bases[GCC_BASE],
1412 .c = {
1413 .dbg_name = "gcc_sdcc1_ahb_clk",
1414 .ops = &clk_ops_branch,
1415 CLK_INIT(gcc_sdcc1_ahb_clk.c),
1416 },
1417};
1418
1419static struct branch_clk gcc_sdcc1_apps_clk = {
1420 .cbcr_reg = SDCC1_APPS_CBCR,
1421 .has_sibling = 0,
1422 .base = &virt_bases[GCC_BASE],
1423 .c = {
1424 .dbg_name = "gcc_sdcc1_apps_clk",
1425 .parent = &sdcc1_apps_clk_src.c,
1426 .ops = &clk_ops_branch,
1427 CLK_INIT(gcc_sdcc1_apps_clk.c),
1428 },
1429};
1430
1431static struct branch_clk gcc_sdcc2_ahb_clk = {
1432 .cbcr_reg = SDCC2_AHB_CBCR,
1433 .has_sibling = 1,
1434 .base = &virt_bases[GCC_BASE],
1435 .c = {
1436 .dbg_name = "gcc_sdcc2_ahb_clk",
1437 .ops = &clk_ops_branch,
1438 CLK_INIT(gcc_sdcc2_ahb_clk.c),
1439 },
1440};
1441
1442static struct branch_clk gcc_sdcc2_apps_clk = {
1443 .cbcr_reg = SDCC2_APPS_CBCR,
1444 .has_sibling = 0,
1445 .base = &virt_bases[GCC_BASE],
1446 .c = {
1447 .dbg_name = "gcc_sdcc2_apps_clk",
1448 .parent = &sdcc2_apps_clk_src.c,
1449 .ops = &clk_ops_branch,
1450 CLK_INIT(gcc_sdcc2_apps_clk.c),
1451 },
1452};
1453
1454static struct branch_clk gcc_sdcc3_ahb_clk = {
1455 .cbcr_reg = SDCC3_AHB_CBCR,
1456 .has_sibling = 1,
1457 .base = &virt_bases[GCC_BASE],
1458 .c = {
1459 .dbg_name = "gcc_sdcc3_ahb_clk",
1460 .ops = &clk_ops_branch,
1461 CLK_INIT(gcc_sdcc3_ahb_clk.c),
1462 },
1463};
1464
1465static struct branch_clk gcc_sdcc3_apps_clk = {
1466 .cbcr_reg = SDCC3_APPS_CBCR,
1467 .has_sibling = 0,
1468 .base = &virt_bases[GCC_BASE],
1469 .c = {
1470 .dbg_name = "gcc_sdcc3_apps_clk",
1471 .parent = &sdcc3_apps_clk_src.c,
1472 .ops = &clk_ops_branch,
1473 CLK_INIT(gcc_sdcc3_apps_clk.c),
1474 },
1475};
1476
1477static struct branch_clk gcc_usb2a_phy_sleep_clk = {
1478 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
1479 .has_sibling = 1,
1480 .base = &virt_bases[GCC_BASE],
1481 .c = {
1482 .dbg_name = "gcc_usb2a_phy_sleep_clk",
1483 .ops = &clk_ops_branch,
1484 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
1485 },
1486};
1487
1488static struct branch_clk gcc_usb_hs_ahb_clk = {
1489 .cbcr_reg = USB_HS_AHB_CBCR,
1490 .has_sibling = 1,
1491 .base = &virt_bases[GCC_BASE],
1492 .c = {
1493 .dbg_name = "gcc_usb_hs_ahb_clk",
1494 .ops = &clk_ops_branch,
1495 CLK_INIT(gcc_usb_hs_ahb_clk.c),
1496 },
1497};
1498
1499static struct branch_clk gcc_usb_hs_system_clk = {
1500 .cbcr_reg = USB_HS_SYSTEM_CBCR,
1501 .has_sibling = 0,
1502 .bcr_reg = USB_HS_BCR,
1503 .base = &virt_bases[GCC_BASE],
1504 .c = {
1505 .dbg_name = "gcc_usb_hs_system_clk",
1506 .parent = &usb_hs_system_clk_src.c,
1507 .ops = &clk_ops_branch,
1508 CLK_INIT(gcc_usb_hs_system_clk.c),
1509 },
1510};
1511
1512static struct branch_clk gcc_usb_hsic_ahb_clk = {
1513 .cbcr_reg = USB_HSIC_AHB_CBCR,
1514 .has_sibling = 1,
1515 .base = &virt_bases[GCC_BASE],
1516 .c = {
1517 .dbg_name = "gcc_usb_hsic_ahb_clk",
1518 .ops = &clk_ops_branch,
1519 CLK_INIT(gcc_usb_hsic_ahb_clk.c),
1520 },
1521};
1522
1523static struct branch_clk gcc_usb_hsic_clk = {
1524 .cbcr_reg = USB_HSIC_CBCR,
1525 .has_sibling = 0,
1526 .bcr_reg = USB_HS_HSIC_BCR,
1527 .base = &virt_bases[GCC_BASE],
1528 .c = {
1529 .dbg_name = "gcc_usb_hsic_clk",
1530 .parent = &usb_hsic_clk_src.c,
1531 .ops = &clk_ops_branch,
1532 CLK_INIT(gcc_usb_hsic_clk.c),
1533 },
1534};
1535
1536static struct branch_clk gcc_usb_hsic_io_cal_clk = {
1537 .cbcr_reg = USB_HSIC_IO_CAL_CBCR,
1538 .has_sibling = 0,
1539 .base = &virt_bases[GCC_BASE],
1540 .c = {
1541 .dbg_name = "gcc_usb_hsic_io_cal_clk",
1542 .parent = &usb_hsic_io_cal_clk_src.c,
1543 .ops = &clk_ops_branch,
1544 CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
1545 },
1546};
1547
1548static struct branch_clk gcc_usb_hsic_system_clk = {
1549 .cbcr_reg = USB_HSIC_SYSTEM_CBCR,
1550 .has_sibling = 0,
1551 .bcr_reg = USB_HS_HSIC_BCR,
1552 .base = &virt_bases[GCC_BASE],
1553 .c = {
1554 .dbg_name = "gcc_usb_hsic_system_clk",
1555 .parent = &usb_hsic_system_clk_src.c,
1556 .ops = &clk_ops_branch,
1557 CLK_INIT(gcc_usb_hsic_system_clk.c),
1558 },
1559};
1560
1561static struct measure_mux_entry measure_mux_GCC[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1562 { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 },
1563 { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 },
1564 { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 },
1565 { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 },
1566 { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a },
1567 { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b },
1568 { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 },
1569 { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 },
1570 { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 },
1571 { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 },
1572 { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 },
1573 { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 },
1574 { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 },
1575 { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 },
1576 { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 },
1577 { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 },
1578 { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a },
1579 { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b },
1580 { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c },
1581 { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e },
1582 { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 },
1583 { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 },
1584 { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 },
1585 { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 },
1586 { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 },
1587 { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 },
1588 { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 },
1589 { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a },
1590 { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c },
1591 { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d },
1592 { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e },
1593 { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 },
1594 { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 },
1595 { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 },
1596 { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 },
1597 { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 },
1598 { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 },
1599 { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 },
1600 { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 },
1601 { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 },
1602 { &gcc_ce1_clk.c, GCC_BASE, 0x0138 },
1603 { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 },
1604 { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a },
1605 { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 },
Patrick Daly2a4ba832013-07-17 12:52:40 -0700[diff] [blame]1606 { &pnoc_clk.c, GCC_BASE, 0x010},
1607 { &snoc_clk.c, GCC_BASE, 0x000},
1608 { &cnoc_clk.c, GCC_BASE, 0x008},
1609 /*
1610 * measure the gcc_bimc_kpss_axi_clk instead to account for the DDR
1611 * rate being gcc_bimc_clk/2.
1612 */
1613 { &bimc_clk.c, GCC_BASE, 0x155},
1614 { &dummy_clk, N_BASES, 0x0000},
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1615};
1616
1617static struct pll_vote_clk mmpll0_pll = {
1618 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1619 .en_mask = BIT(0),
1620 .status_reg = (void __iomem *)MMPLL0_PLL_STATUS,
1621 .status_mask = BIT(17),
1622 .base = &virt_bases[MMSS_BASE],
1623 .c = {
1624 .rate = 800000000,
1625 .parent = &xo.c,
1626 .dbg_name = "mmpll0_pll",
1627 .ops = &clk_ops_pll_vote,
1628 CLK_INIT(mmpll0_pll.c),
1629 },
1630};
1631
1632static struct pll_vote_clk mmpll1_pll = {
1633 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1634 .en_mask = BIT(1),
1635 .status_reg = (void __iomem *)MMPLL1_PLL_STATUS,
1636 .status_mask = BIT(17),
1637 .base = &virt_bases[MMSS_BASE],
1638 .c = {
1639 .rate = 1000000000,
1640 .parent = &xo.c,
1641 .dbg_name = "mmpll1_pll",
1642 .ops = &clk_ops_pll_vote,
1643 CLK_INIT(mmpll1_pll.c),
1644 },
1645};
1646
1647static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = {
1648 F_MMSS( 19200000, xo, 1, 0, 0),
1649 F_MMSS( 37500000, gpll0, 16, 0, 0),
1650 F_MMSS( 50000000, gpll0, 12, 0, 0),
1651 F_MMSS( 75000000, gpll0, 8, 0, 0),
1652 F_MMSS( 100000000, gpll0, 6, 0, 0),
1653 F_MMSS( 150000000, gpll0, 4, 0, 0),
1654 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
pfang948c93e2013-03-20 17:04:18 -0700[diff] [blame]1655 F_MMSS( 266666666, mmpll0_pll, 3, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1656 F_END
1657};
1658
1659static struct rcg_clk axi_clk_src = {
1660 .cmd_rcgr_reg = AXI_CMD_RCGR,
1661 .set_rate = set_rate_hid,
1662 .freq_tbl = ftbl_mmss_mmssnoc_axi_clk,
1663 .current_freq = &rcg_dummy_freq,
1664 .base = &virt_bases[MMSS_BASE],
1665 .c = {
1666 .dbg_name = "axi_clk_src",
1667 .ops = &clk_ops_rcg,
1668 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1669 266670000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1670 CLK_INIT(axi_clk_src.c),
1671 },
1672};
1673
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1674static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = {
1675 F_MMSS( 100000000, gpll0, 6, 0, 0),
1676 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1677 F_END
1678};
1679
1680static struct rcg_clk csi0_clk_src = {
1681 .cmd_rcgr_reg = CSI0_CMD_RCGR,
1682 .set_rate = set_rate_hid,
1683 .freq_tbl = ftbl_camss_csi0_1_clk,
1684 .current_freq = &rcg_dummy_freq,
1685 .base = &virt_bases[MMSS_BASE],
1686 .c = {
1687 .dbg_name = "csi0_clk_src",
1688 .ops = &clk_ops_rcg,
1689 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1690 CLK_INIT(csi0_clk_src.c),
1691 },
1692};
1693
1694static struct rcg_clk csi1_clk_src = {
1695 .cmd_rcgr_reg = CSI1_CMD_RCGR,
1696 .set_rate = set_rate_hid,
1697 .freq_tbl = ftbl_camss_csi0_1_clk,
1698 .current_freq = &rcg_dummy_freq,
1699 .base = &virt_bases[MMSS_BASE],
1700 .c = {
1701 .dbg_name = "csi1_clk_src",
1702 .ops = &clk_ops_rcg,
1703 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1704 CLK_INIT(csi1_clk_src.c),
1705 },
1706};
1707
1708static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = {
1709 F_MMSS( 37500000, gpll0, 16, 0, 0),
1710 F_MMSS( 50000000, gpll0, 12, 0, 0),
1711 F_MMSS( 60000000, gpll0, 10, 0, 0),
1712 F_MMSS( 80000000, gpll0, 7.5, 0, 0),
1713 F_MMSS( 100000000, gpll0, 6, 0, 0),
1714 F_MMSS( 109090000, gpll0, 5.5, 0, 0),
1715 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1716 F_MMSS( 150000000, gpll0, 4, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1717 F_MMSS( 200000000, gpll0, 3, 0, 0),
1718 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1719 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1720 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1721 F_MMSS( 400000000, mmpll0_pll, 2, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1722 F_END
1723};
1724
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]1725static unsigned long camss_vfe_vfe0_fmax_v2[VDD_DIG_NUM] = {
1726 150000000, 320000000, 400000000,
1727};
1728
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1729static struct rcg_clk vfe0_clk_src = {
1730 .cmd_rcgr_reg = VFE0_CMD_RCGR,
1731 .set_rate = set_rate_hid,
1732 .freq_tbl = ftbl_camss_vfe_vfe0_clk,
1733 .current_freq = &rcg_dummy_freq,
1734 .base = &virt_bases[MMSS_BASE],
1735 .c = {
1736 .dbg_name = "vfe0_clk_src",
1737 .ops = &clk_ops_rcg,
1738 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1739 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1740 CLK_INIT(vfe0_clk_src.c),
1741 },
1742};
1743
1744static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = {
1745 F_MMSS( 37500000, gpll0, 16, 0, 0),
1746 F_MMSS( 60000000, gpll0, 10, 0, 0),
1747 F_MMSS( 75000000, gpll0, 8, 0, 0),
1748 F_MMSS( 92310000, gpll0, 6.5, 0, 0),
1749 F_MMSS( 100000000, gpll0, 6, 0, 0),
1750 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
1751 F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0),
1752 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1753 F_END
1754};
1755
1756static struct rcg_clk mdp_clk_src = {
1757 .cmd_rcgr_reg = MDP_CMD_RCGR,
1758 .set_rate = set_rate_hid,
1759 .freq_tbl = ftbl_mdss_mdp_clk,
1760 .current_freq = &rcg_dummy_freq,
1761 .base = &virt_bases[MMSS_BASE],
1762 .c = {
1763 .dbg_name = "mdp_clk_src",
1764 .ops = &clk_ops_rcg,
1765 VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1766 200000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1767 CLK_INIT(mdp_clk_src.c),
1768 },
1769};
1770
1771static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = {
1772 F_MMSS( 75000000, gpll0, 8, 0, 0),
1773 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1774 F_MMSS( 200000000, gpll0, 3, 0, 0),
1775 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1776 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1777 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1778 F_END
1779};
1780
1781static struct rcg_clk jpeg0_clk_src = {
1782 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1783 .set_rate = set_rate_hid,
1784 .freq_tbl = ftbl_camss_jpeg_jpeg0_clk,
1785 .current_freq = &rcg_dummy_freq,
1786 .base = &virt_bases[MMSS_BASE],
1787 .c = {
1788 .dbg_name = "jpeg0_clk_src",
1789 .ops = &clk_ops_rcg,
1790 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1791 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1792 CLK_INIT(jpeg0_clk_src.c),
1793 },
1794};
1795
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1796struct clk_ops clk_ops_pixel_clock;
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1797
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1798static long round_rate_pixel(struct clk *clk, unsigned long rate)
1799{
1800 int frac_num[] = {3, 2, 4, 1};
1801 int frac_den[] = {8, 9, 9, 1};
1802 int delta = 100000;
1803 int i;
1804
1805 for (i = 0; i < ARRAY_SIZE(frac_num); i++) {
1806 unsigned long request = (rate * frac_den[i]) / frac_num[i];
1807 unsigned long src_rate;
1808
1809 src_rate = clk_round_rate(clk->parent, request);
1810 if ((src_rate < (request - delta)) ||
1811 (src_rate > (request + delta)))
1812 continue;
1813
1814 return (src_rate * frac_num[i]) / frac_den[i];
1815 }
1816
1817 return -EINVAL;
1818}
1819
1820
1821static int set_rate_pixel(struct clk *clk, unsigned long rate)
1822{
1823 struct rcg_clk *rcg = to_rcg_clk(clk);
1824 struct clk_freq_tbl *pixel_freq = rcg->current_freq;
1825 int frac_num[] = {3, 2, 4, 1};
1826 int frac_den[] = {8, 9, 9, 1};
1827 int delta = 100000;
1828 int i, rc;
1829
1830 for (i = 0; i < ARRAY_SIZE(frac_num); i++) {
1831 unsigned long request = (rate * frac_den[i]) / frac_num[i];
1832 unsigned long src_rate;
1833
1834 src_rate = clk_round_rate(clk->parent, request);
1835 if ((src_rate < (request - delta)) ||
1836 (src_rate > (request + delta)))
1837 continue;
1838
1839 rc = clk_set_rate(clk->parent, src_rate);
1840 if (rc)
1841 return rc;
1842
1843 pixel_freq->div_src_val &= ~BM(4, 0);
1844 if (frac_den[i] == frac_num[i]) {
1845 pixel_freq->m_val = 0;
1846 pixel_freq->n_val = 0;
1847 } else {
1848 pixel_freq->m_val = frac_num[i];
1849 pixel_freq->n_val = ~(frac_den[i] - frac_num[i]);
1850 pixel_freq->d_val = ~frac_den[i];
1851 }
1852 set_rate_mnd(rcg, pixel_freq);
1853 return 0;
1854 }
1855 return -EINVAL;
1856}
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1857
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1858static struct clk_freq_tbl pixel_freq_tbl[] = {
1859 {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1860 .src_clk = &pixel_clk_src_8226.c,
1861 .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val)
1862 | BVAL(4, 0, 0),
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1863 },
1864 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1865};
1866
1867static struct rcg_clk pclk0_clk_src = {
1868 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]1869 .current_freq = pixel_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1870 .base = &virt_bases[MMSS_BASE],
1871 .c = {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]1872 .parent = &pixel_clk_src_8226.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1873 .dbg_name = "pclk0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1874 .ops = &clk_ops_pixel,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1875 VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000),
1876 CLK_INIT(pclk0_clk_src.c),
1877 },
1878};
1879
1880static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = {
1881 F_MMSS( 66700000, gpll0, 9, 0, 0),
1882 F_MMSS( 100000000, gpll0, 6, 0, 0),
1883 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]1884 F_MMSS( 160000000, mmpll0_pll, 5, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1885 F_END
1886};
1887
1888static struct rcg_clk vcodec0_clk_src = {
1889 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
1890 .set_rate = set_rate_mnd,
1891 .freq_tbl = ftbl_venus0_vcodec0_clk,
1892 .current_freq = &rcg_dummy_freq,
1893 .base = &virt_bases[MMSS_BASE],
1894 .c = {
1895 .dbg_name = "vcodec0_clk_src",
1896 .ops = &clk_ops_rcg_mnd,
Patrick Daly59c74322013-06-07 12:00:42 -0700[diff] [blame]1897 VDD_DIG_FMAX_MAP3(LOW, 66700000, NOMINAL, 133330000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1898 160000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1899 CLK_INIT(vcodec0_clk_src.c),
1900 },
1901};
1902
1903static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = {
1904 F_MMSS( 19200000, xo, 1, 0, 0),
1905 F_END
1906};
1907
1908static struct rcg_clk cci_clk_src = {
1909 .cmd_rcgr_reg = CCI_CMD_RCGR,
1910 .set_rate = set_rate_mnd,
1911 .freq_tbl = ftbl_camss_cci_cci_clk,
1912 .current_freq = &rcg_dummy_freq,
1913 .base = &virt_bases[MMSS_BASE],
1914 .c = {
1915 .dbg_name = "cci_clk_src",
1916 .ops = &clk_ops_rcg_mnd,
1917 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
1918 CLK_INIT(cci_clk_src.c),
1919 },
1920};
1921
1922static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = {
1923 F_MMSS( 10000, xo, 16, 1, 120),
1924 F_MMSS( 24000, xo, 16, 1, 50),
1925 F_MMSS( 6000000, gpll0, 10, 1, 10),
1926 F_MMSS( 12000000, gpll0, 10, 1, 5),
1927 F_MMSS( 13000000, gpll0, 4, 13, 150),
1928 F_MMSS( 24000000, gpll0, 5, 1, 5),
1929 F_END
1930};
1931
1932static struct rcg_clk mmss_gp0_clk_src = {
1933 .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR,
1934 .set_rate = set_rate_mnd,
1935 .freq_tbl = ftbl_camss_gp0_1_clk,
1936 .current_freq = &rcg_dummy_freq,
1937 .base = &virt_bases[MMSS_BASE],
1938 .c = {
1939 .dbg_name = "mmss_gp0_clk_src",
1940 .ops = &clk_ops_rcg_mnd,
1941 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1942 CLK_INIT(mmss_gp0_clk_src.c),
1943 },
1944};
1945
1946static struct rcg_clk mmss_gp1_clk_src = {
1947 .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR,
1948 .set_rate = set_rate_mnd,
1949 .freq_tbl = ftbl_camss_gp0_1_clk,
1950 .current_freq = &rcg_dummy_freq,
1951 .base = &virt_bases[MMSS_BASE],
1952 .c = {
1953 .dbg_name = "mmss_gp1_clk_src",
1954 .ops = &clk_ops_rcg_mnd,
1955 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1956 CLK_INIT(mmss_gp1_clk_src.c),
1957 },
1958};
1959
1960static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = {
Patrick Daly42d2b7a2013-03-07 17:12:33 -0800[diff] [blame]1961 F_MMSS( 19200000, xo, 1, 0, 0),
1962 F_MMSS( 24000000, gpll0, 5, 1, 5),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1963 F_MMSS( 66670000, gpll0, 9, 0, 0),
1964 F_END
1965};
1966
1967static struct rcg_clk mclk0_clk_src = {
1968 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1969 .set_rate = set_rate_mnd,
1970 .freq_tbl = ftbl_camss_mclk0_1_clk,
1971 .current_freq = &rcg_dummy_freq,
1972 .base = &virt_bases[MMSS_BASE],
1973 .c = {
1974 .dbg_name = "mclk0_clk_src",
1975 .ops = &clk_ops_rcg_mnd,
1976 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1977 CLK_INIT(mclk0_clk_src.c),
1978 },
1979};
1980
1981static struct rcg_clk mclk1_clk_src = {
1982 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1983 .set_rate = set_rate_mnd,
1984 .freq_tbl = ftbl_camss_mclk0_1_clk,
1985 .current_freq = &rcg_dummy_freq,
1986 .base = &virt_bases[MMSS_BASE],
1987 .c = {
1988 .dbg_name = "mclk1_clk_src",
1989 .ops = &clk_ops_rcg_mnd,
1990 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1991 CLK_INIT(mclk1_clk_src.c),
1992 },
1993};
1994
1995static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = {
1996 F_MMSS( 100000000, gpll0, 6, 0, 0),
1997 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1998 F_END
1999};
2000
2001static struct rcg_clk csi0phytimer_clk_src = {
2002 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
2003 .set_rate = set_rate_hid,
2004 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
2005 .current_freq = &rcg_dummy_freq,
2006 .base = &virt_bases[MMSS_BASE],
2007 .c = {
2008 .dbg_name = "csi0phytimer_clk_src",
2009 .ops = &clk_ops_rcg,
2010 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
2011 CLK_INIT(csi0phytimer_clk_src.c),
2012 },
2013};
2014
2015static struct rcg_clk csi1phytimer_clk_src = {
2016 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
2017 .set_rate = set_rate_hid,
2018 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
2019 .current_freq = &rcg_dummy_freq,
2020 .base = &virt_bases[MMSS_BASE],
2021 .c = {
2022 .dbg_name = "csi1phytimer_clk_src",
2023 .ops = &clk_ops_rcg,
2024 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
2025 CLK_INIT(csi1phytimer_clk_src.c),
2026 },
2027};
2028
2029static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = {
2030 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2031 F_MMSS( 150000000, gpll0, 4, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2032 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
2033 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2034 F_MMSS( 400000000, mmpll0_pll, 2, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2035 F_END
2036};
2037
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]2038static unsigned long camss_vfe_cpp_fmax_v2[VDD_DIG_NUM] = {
2039 150000000, 320000000, 400000000,
2040};
2041
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2042static struct rcg_clk cpp_clk_src = {
2043 .cmd_rcgr_reg = CPP_CMD_RCGR,
2044 .set_rate = set_rate_hid,
2045 .freq_tbl = ftbl_camss_vfe_cpp_clk,
2046 .current_freq = &rcg_dummy_freq,
2047 .base = &virt_bases[MMSS_BASE],
2048 .c = {
2049 .dbg_name = "cpp_clk_src",
2050 .ops = &clk_ops_rcg,
2051 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]2052 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2053 CLK_INIT(cpp_clk_src.c),
2054 },
2055};
2056
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2057static struct clk_freq_tbl byte_freq_tbl[] = {
2058 {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]2059 .src_clk = &byte_clk_src_8226.c,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2060 .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
2061 },
2062 F_END
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2063};
2064
2065static struct rcg_clk byte0_clk_src = {
2066 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
Vikram Mulukutlaae13f3c2013-03-20 18:03:29 -0700[diff] [blame]2067 .current_freq = byte_freq_tbl,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2068 .base = &virt_bases[MMSS_BASE],
2069 .c = {
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]2070 .parent = &byte_clk_src_8226.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2071 .dbg_name = "byte0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2072 .ops = &clk_ops_byte,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2073 VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000),
2074 CLK_INIT(byte0_clk_src.c),
2075 },
2076};
2077
2078static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = {
2079 F_MDSS( 19200000, xo, 1, 0, 0),
2080 F_END
2081};
2082
2083static struct rcg_clk esc0_clk_src = {
2084 .cmd_rcgr_reg = ESC0_CMD_RCGR,
2085 .set_rate = set_rate_hid,
2086 .freq_tbl = ftbl_mdss_esc0_clk,
2087 .current_freq = &rcg_dummy_freq,
2088 .base = &virt_bases[MMSS_BASE],
2089 .c = {
2090 .dbg_name = "esc0_clk_src",
2091 .ops = &clk_ops_rcg,
2092 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2093 CLK_INIT(esc0_clk_src.c),
2094 },
2095};
2096
2097static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
2098 F_MDSS( 19200000, xo, 1, 0, 0),
2099 F_END
2100};
2101
2102static struct rcg_clk vsync_clk_src = {
2103 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
2104 .set_rate = set_rate_hid,
2105 .freq_tbl = ftbl_mdss_vsync_clk,
2106 .current_freq = &rcg_dummy_freq,
2107 .base = &virt_bases[MMSS_BASE],
2108 .c = {
2109 .dbg_name = "vsync_clk_src",
2110 .ops = &clk_ops_rcg,
2111 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2112 CLK_INIT(vsync_clk_src.c),
2113 },
2114};
2115
2116static struct branch_clk camss_cci_cci_ahb_clk = {
2117 .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
2118 .has_sibling = 1,
2119 .base = &virt_bases[MMSS_BASE],
2120 .c = {
2121 .dbg_name = "camss_cci_cci_ahb_clk",
2122 .ops = &clk_ops_branch,
2123 CLK_INIT(camss_cci_cci_ahb_clk.c),
2124 },
2125};
2126
2127static struct branch_clk camss_cci_cci_clk = {
2128 .cbcr_reg = CAMSS_CCI_CCI_CBCR,
2129 .has_sibling = 0,
2130 .base = &virt_bases[MMSS_BASE],
2131 .c = {
2132 .dbg_name = "camss_cci_cci_clk",
2133 .parent = &cci_clk_src.c,
2134 .ops = &clk_ops_branch,
2135 CLK_INIT(camss_cci_cci_clk.c),
2136 },
2137};
2138
2139static struct branch_clk camss_csi0_ahb_clk = {
2140 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2141 .has_sibling = 1,
2142 .base = &virt_bases[MMSS_BASE],
2143 .c = {
2144 .dbg_name = "camss_csi0_ahb_clk",
2145 .ops = &clk_ops_branch,
2146 CLK_INIT(camss_csi0_ahb_clk.c),
2147 },
2148};
2149
2150static struct branch_clk camss_csi0_clk = {
2151 .cbcr_reg = CAMSS_CSI0_CBCR,
2152 .has_sibling = 1,
2153 .base = &virt_bases[MMSS_BASE],
2154 .c = {
2155 .dbg_name = "camss_csi0_clk",
2156 .parent = &csi0_clk_src.c,
2157 .ops = &clk_ops_branch,
2158 CLK_INIT(camss_csi0_clk.c),
2159 },
2160};
2161
2162static struct branch_clk camss_csi0phy_clk = {
2163 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2164 .has_sibling = 1,
2165 .base = &virt_bases[MMSS_BASE],
2166 .c = {
2167 .dbg_name = "camss_csi0phy_clk",
2168 .parent = &csi0_clk_src.c,
2169 .ops = &clk_ops_branch,
2170 CLK_INIT(camss_csi0phy_clk.c),
2171 },
2172};
2173
2174static struct branch_clk camss_csi0pix_clk = {
2175 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2176 .has_sibling = 1,
2177 .base = &virt_bases[MMSS_BASE],
2178 .c = {
2179 .dbg_name = "camss_csi0pix_clk",
2180 .parent = &csi0_clk_src.c,
2181 .ops = &clk_ops_branch,
2182 CLK_INIT(camss_csi0pix_clk.c),
2183 },
2184};
2185
2186static struct branch_clk camss_csi0rdi_clk = {
2187 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2188 .has_sibling = 1,
2189 .base = &virt_bases[MMSS_BASE],
2190 .c = {
2191 .dbg_name = "camss_csi0rdi_clk",
2192 .parent = &csi0_clk_src.c,
2193 .ops = &clk_ops_branch,
2194 CLK_INIT(camss_csi0rdi_clk.c),
2195 },
2196};
2197
2198static struct branch_clk camss_csi1_ahb_clk = {
2199 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2200 .has_sibling = 1,
2201 .base = &virt_bases[MMSS_BASE],
2202 .c = {
2203 .dbg_name = "camss_csi1_ahb_clk",
2204 .ops = &clk_ops_branch,
2205 CLK_INIT(camss_csi1_ahb_clk.c),
2206 },
2207};
2208
2209static struct branch_clk camss_csi1_clk = {
2210 .cbcr_reg = CAMSS_CSI1_CBCR,
2211 .has_sibling = 1,
2212 .base = &virt_bases[MMSS_BASE],
2213 .c = {
2214 .dbg_name = "camss_csi1_clk",
2215 .parent = &csi1_clk_src.c,
2216 .ops = &clk_ops_branch,
2217 CLK_INIT(camss_csi1_clk.c),
2218 },
2219};
2220
2221static struct branch_clk camss_csi1phy_clk = {
2222 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2223 .has_sibling = 1,
2224 .base = &virt_bases[MMSS_BASE],
2225 .c = {
2226 .dbg_name = "camss_csi1phy_clk",
2227 .parent = &csi1_clk_src.c,
2228 .ops = &clk_ops_branch,
2229 CLK_INIT(camss_csi1phy_clk.c),
2230 },
2231};
2232
2233static struct branch_clk camss_csi1pix_clk = {
2234 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2235 .has_sibling = 1,
2236 .base = &virt_bases[MMSS_BASE],
2237 .c = {
2238 .dbg_name = "camss_csi1pix_clk",
2239 .parent = &csi1_clk_src.c,
2240 .ops = &clk_ops_branch,
2241 CLK_INIT(camss_csi1pix_clk.c),
2242 },
2243};
2244
2245static struct branch_clk camss_csi1rdi_clk = {
2246 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2247 .has_sibling = 1,
2248 .base = &virt_bases[MMSS_BASE],
2249 .c = {
2250 .dbg_name = "camss_csi1rdi_clk",
2251 .parent = &csi1_clk_src.c,
2252 .ops = &clk_ops_branch,
2253 CLK_INIT(camss_csi1rdi_clk.c),
2254 },
2255};
2256
2257static struct branch_clk camss_csi_vfe0_clk = {
2258 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2259 .bcr_reg = CAMSS_CSI_VFE0_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2260 .has_sibling = 1,
2261 .base = &virt_bases[MMSS_BASE],
2262 .c = {
2263 .dbg_name = "camss_csi_vfe0_clk",
2264 .parent = &vfe0_clk_src.c,
2265 .ops = &clk_ops_branch,
2266 CLK_INIT(camss_csi_vfe0_clk.c),
2267 },
2268};
2269
2270static struct branch_clk camss_gp0_clk = {
2271 .cbcr_reg = CAMSS_GP0_CBCR,
2272 .has_sibling = 0,
2273 .base = &virt_bases[MMSS_BASE],
2274 .c = {
2275 .dbg_name = "camss_gp0_clk",
2276 .parent = &mmss_gp0_clk_src.c,
2277 .ops = &clk_ops_branch,
2278 CLK_INIT(camss_gp0_clk.c),
2279 },
2280};
2281
2282static struct branch_clk camss_gp1_clk = {
2283 .cbcr_reg = CAMSS_GP1_CBCR,
2284 .has_sibling = 0,
2285 .base = &virt_bases[MMSS_BASE],
2286 .c = {
2287 .dbg_name = "camss_gp1_clk",
2288 .parent = &mmss_gp1_clk_src.c,
2289 .ops = &clk_ops_branch,
2290 CLK_INIT(camss_gp1_clk.c),
2291 },
2292};
2293
2294static struct branch_clk camss_ispif_ahb_clk = {
2295 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2296 .has_sibling = 1,
2297 .base = &virt_bases[MMSS_BASE],
2298 .c = {
2299 .dbg_name = "camss_ispif_ahb_clk",
2300 .ops = &clk_ops_branch,
2301 CLK_INIT(camss_ispif_ahb_clk.c),
2302 },
2303};
2304
2305static struct branch_clk camss_jpeg_jpeg0_clk = {
2306 .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2307 .bcr_reg = CAMSS_JPEG_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2308 .has_sibling = 0,
2309 .base = &virt_bases[MMSS_BASE],
2310 .c = {
2311 .dbg_name = "camss_jpeg_jpeg0_clk",
2312 .parent = &jpeg0_clk_src.c,
2313 .ops = &clk_ops_branch,
2314 CLK_INIT(camss_jpeg_jpeg0_clk.c),
2315 },
2316};
2317
2318static struct branch_clk camss_jpeg_jpeg_ahb_clk = {
2319 .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
2320 .has_sibling = 1,
2321 .base = &virt_bases[MMSS_BASE],
2322 .c = {
2323 .dbg_name = "camss_jpeg_jpeg_ahb_clk",
2324 .ops = &clk_ops_branch,
2325 CLK_INIT(camss_jpeg_jpeg_ahb_clk.c),
2326 },
2327};
2328
2329static struct branch_clk camss_jpeg_jpeg_axi_clk = {
2330 .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
2331 .has_sibling = 1,
2332 .base = &virt_bases[MMSS_BASE],
2333 .c = {
2334 .dbg_name = "camss_jpeg_jpeg_axi_clk",
2335 .parent = &axi_clk_src.c,
2336 .ops = &clk_ops_branch,
2337 CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
2338 },
2339};
2340
2341static struct branch_clk camss_mclk0_clk = {
2342 .cbcr_reg = CAMSS_MCLK0_CBCR,
2343 .has_sibling = 0,
2344 .base = &virt_bases[MMSS_BASE],
2345 .c = {
2346 .dbg_name = "camss_mclk0_clk",
2347 .parent = &mclk0_clk_src.c,
2348 .ops = &clk_ops_branch,
2349 CLK_INIT(camss_mclk0_clk.c),
2350 },
2351};
2352
2353static struct branch_clk camss_mclk1_clk = {
2354 .cbcr_reg = CAMSS_MCLK1_CBCR,
2355 .has_sibling = 0,
2356 .base = &virt_bases[MMSS_BASE],
2357 .c = {
2358 .dbg_name = "camss_mclk1_clk",
2359 .parent = &mclk1_clk_src.c,
2360 .ops = &clk_ops_branch,
2361 CLK_INIT(camss_mclk1_clk.c),
2362 },
2363};
2364
2365static struct branch_clk camss_micro_ahb_clk = {
2366 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2367 .has_sibling = 1,
2368 .base = &virt_bases[MMSS_BASE],
2369 .c = {
2370 .dbg_name = "camss_micro_ahb_clk",
2371 .ops = &clk_ops_branch,
2372 CLK_INIT(camss_micro_ahb_clk.c),
2373 },
2374};
2375
2376static struct branch_clk camss_phy0_csi0phytimer_clk = {
2377 .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
2378 .has_sibling = 0,
2379 .base = &virt_bases[MMSS_BASE],
2380 .c = {
2381 .dbg_name = "camss_phy0_csi0phytimer_clk",
2382 .parent = &csi0phytimer_clk_src.c,
2383 .ops = &clk_ops_branch,
2384 CLK_INIT(camss_phy0_csi0phytimer_clk.c),
2385 },
2386};
2387
2388static struct branch_clk camss_phy1_csi1phytimer_clk = {
2389 .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
2390 .has_sibling = 0,
2391 .base = &virt_bases[MMSS_BASE],
2392 .c = {
2393 .dbg_name = "camss_phy1_csi1phytimer_clk",
2394 .parent = &csi1phytimer_clk_src.c,
2395 .ops = &clk_ops_branch,
2396 CLK_INIT(camss_phy1_csi1phytimer_clk.c),
2397 },
2398};
2399
2400static struct branch_clk camss_top_ahb_clk = {
2401 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2402 .has_sibling = 1,
2403 .base = &virt_bases[MMSS_BASE],
2404 .c = {
2405 .dbg_name = "camss_top_ahb_clk",
2406 .ops = &clk_ops_branch,
2407 CLK_INIT(camss_top_ahb_clk.c),
2408 },
2409};
2410
2411static struct branch_clk camss_vfe_cpp_ahb_clk = {
2412 .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
2413 .has_sibling = 1,
2414 .base = &virt_bases[MMSS_BASE],
2415 .c = {
2416 .dbg_name = "camss_vfe_cpp_ahb_clk",
2417 .ops = &clk_ops_branch,
2418 CLK_INIT(camss_vfe_cpp_ahb_clk.c),
2419 },
2420};
2421
2422static struct branch_clk camss_vfe_cpp_clk = {
2423 .cbcr_reg = CAMSS_VFE_CPP_CBCR,
2424 .has_sibling = 0,
2425 .base = &virt_bases[MMSS_BASE],
2426 .c = {
2427 .dbg_name = "camss_vfe_cpp_clk",
2428 .parent = &cpp_clk_src.c,
2429 .ops = &clk_ops_branch,
2430 CLK_INIT(camss_vfe_cpp_clk.c),
2431 },
2432};
2433
2434static struct branch_clk camss_vfe_vfe0_clk = {
2435 .cbcr_reg = CAMSS_VFE_VFE0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2436 .bcr_reg = CAMSS_VFE_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2437 .has_sibling = 1,
2438 .base = &virt_bases[MMSS_BASE],
2439 .c = {
2440 .dbg_name = "camss_vfe_vfe0_clk",
2441 .parent = &vfe0_clk_src.c,
2442 .ops = &clk_ops_branch,
2443 CLK_INIT(camss_vfe_vfe0_clk.c),
2444 },
2445};
2446
2447static struct branch_clk camss_vfe_vfe_ahb_clk = {
2448 .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
2449 .has_sibling = 1,
2450 .base = &virt_bases[MMSS_BASE],
2451 .c = {
2452 .dbg_name = "camss_vfe_vfe_ahb_clk",
2453 .ops = &clk_ops_branch,
2454 CLK_INIT(camss_vfe_vfe_ahb_clk.c),
2455 },
2456};
2457
2458static struct branch_clk camss_vfe_vfe_axi_clk = {
2459 .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
2460 .has_sibling = 1,
2461 .base = &virt_bases[MMSS_BASE],
2462 .c = {
2463 .dbg_name = "camss_vfe_vfe_axi_clk",
2464 .parent = &axi_clk_src.c,
2465 .ops = &clk_ops_branch,
2466 CLK_INIT(camss_vfe_vfe_axi_clk.c),
2467 },
2468};
2469
2470static struct branch_clk mdss_ahb_clk = {
2471 .cbcr_reg = MDSS_AHB_CBCR,
2472 .has_sibling = 1,
2473 .base = &virt_bases[MMSS_BASE],
2474 .c = {
2475 .dbg_name = "mdss_ahb_clk",
2476 .ops = &clk_ops_branch,
2477 CLK_INIT(mdss_ahb_clk.c),
2478 },
2479};
2480
2481static struct branch_clk mdss_axi_clk = {
2482 .cbcr_reg = MDSS_AXI_CBCR,
2483 .has_sibling = 1,
2484 .base = &virt_bases[MMSS_BASE],
2485 .c = {
2486 .dbg_name = "mdss_axi_clk",
2487 .parent = &axi_clk_src.c,
2488 .ops = &clk_ops_branch,
2489 CLK_INIT(mdss_axi_clk.c),
2490 },
2491};
2492
2493static struct branch_clk mdss_byte0_clk = {
2494 .cbcr_reg = MDSS_BYTE0_CBCR,
2495 .has_sibling = 0,
2496 .base = &virt_bases[MMSS_BASE],
2497 .c = {
2498 .dbg_name = "mdss_byte0_clk",
2499 .parent = &byte0_clk_src.c,
2500 .ops = &clk_ops_branch,
2501 CLK_INIT(mdss_byte0_clk.c),
2502 },
2503};
2504
2505static struct branch_clk mdss_esc0_clk = {
2506 .cbcr_reg = MDSS_ESC0_CBCR,
2507 .has_sibling = 0,
2508 .base = &virt_bases[MMSS_BASE],
2509 .c = {
2510 .dbg_name = "mdss_esc0_clk",
2511 .parent = &esc0_clk_src.c,
2512 .ops = &clk_ops_branch,
2513 CLK_INIT(mdss_esc0_clk.c),
2514 },
2515};
2516
2517static struct branch_clk mdss_mdp_clk = {
2518 .cbcr_reg = MDSS_MDP_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2519 .bcr_reg = MDSS_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2520 .has_sibling = 1,
2521 .base = &virt_bases[MMSS_BASE],
2522 .c = {
2523 .dbg_name = "mdss_mdp_clk",
2524 .parent = &mdp_clk_src.c,
2525 .ops = &clk_ops_branch,
2526 CLK_INIT(mdss_mdp_clk.c),
2527 },
2528};
2529
2530static struct branch_clk mdss_mdp_lut_clk = {
2531 .cbcr_reg = MDSS_MDP_LUT_CBCR,
2532 .has_sibling = 1,
2533 .base = &virt_bases[MMSS_BASE],
2534 .c = {
2535 .dbg_name = "mdss_mdp_lut_clk",
2536 .parent = &mdp_clk_src.c,
2537 .ops = &clk_ops_branch,
2538 CLK_INIT(mdss_mdp_lut_clk.c),
2539 },
2540};
2541
2542static struct branch_clk mdss_pclk0_clk = {
2543 .cbcr_reg = MDSS_PCLK0_CBCR,
2544 .has_sibling = 0,
2545 .base = &virt_bases[MMSS_BASE],
2546 .c = {
2547 .dbg_name = "mdss_pclk0_clk",
2548 .parent = &pclk0_clk_src.c,
2549 .ops = &clk_ops_branch,
2550 CLK_INIT(mdss_pclk0_clk.c),
2551 },
2552};
2553
2554static struct branch_clk mdss_vsync_clk = {
2555 .cbcr_reg = MDSS_VSYNC_CBCR,
2556 .has_sibling = 0,
2557 .base = &virt_bases[MMSS_BASE],
2558 .c = {
2559 .dbg_name = "mdss_vsync_clk",
2560 .parent = &vsync_clk_src.c,
2561 .ops = &clk_ops_branch,
2562 CLK_INIT(mdss_vsync_clk.c),
2563 },
2564};
2565
2566static struct branch_clk mmss_misc_ahb_clk = {
2567 .cbcr_reg = MMSS_MISC_AHB_CBCR,
2568 .has_sibling = 1,
2569 .base = &virt_bases[MMSS_BASE],
2570 .c = {
2571 .dbg_name = "mmss_misc_ahb_clk",
2572 .ops = &clk_ops_branch,
2573 CLK_INIT(mmss_misc_ahb_clk.c),
2574 },
2575};
2576
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2577static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
2578 .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
2579 .has_sibling = 1,
2580 .base = &virt_bases[MMSS_BASE],
2581 .c = {
2582 .dbg_name = "mmss_mmssnoc_bto_ahb_clk",
2583 .ops = &clk_ops_branch,
2584 CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c),
2585 },
2586};
2587
2588static struct branch_clk mmss_mmssnoc_axi_clk = {
2589 .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
2590 .has_sibling = 1,
2591 .base = &virt_bases[MMSS_BASE],
2592 .c = {
2593 .dbg_name = "mmss_mmssnoc_axi_clk",
2594 .parent = &axi_clk_src.c,
2595 .ops = &clk_ops_branch,
2596 CLK_INIT(mmss_mmssnoc_axi_clk.c),
2597 },
2598};
2599
2600static struct branch_clk mmss_s0_axi_clk = {
2601 .cbcr_reg = MMSS_S0_AXI_CBCR,
2602 .has_sibling = 0,
2603 .max_div = 0,
2604 .base = &virt_bases[MMSS_BASE],
2605 .c = {
2606 .dbg_name = "mmss_s0_axi_clk",
2607 .parent = &axi_clk_src.c,
2608 .ops = &clk_ops_branch,
2609 CLK_INIT(mmss_s0_axi_clk.c),
2610 .depends = &mmss_mmssnoc_axi_clk.c,
2611 },
2612};
2613
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2614static struct branch_clk oxili_gfx3d_clk = {
2615 .cbcr_reg = OXILI_GFX3D_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2616 .bcr_reg = OXILICX_BCR,
Patrick Daly295173b2013-03-11 13:35:40 -0700[diff] [blame]2617 .has_sibling = 0,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2618 .max_div = 0,
2619 .base = &virt_bases[MMSS_BASE],
2620 .c = {
2621 .dbg_name = "oxili_gfx3d_clk",
2622 .parent = &gfx3d_clk_src.c,
2623 .ops = &clk_ops_branch,
2624 CLK_INIT(oxili_gfx3d_clk.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2625 },
2626};
2627
2628static struct branch_clk oxilicx_ahb_clk = {
2629 .cbcr_reg = OXILICX_AHB_CBCR,
2630 .has_sibling = 1,
2631 .base = &virt_bases[MMSS_BASE],
2632 .c = {
2633 .dbg_name = "oxilicx_ahb_clk",
2634 .ops = &clk_ops_branch,
2635 CLK_INIT(oxilicx_ahb_clk.c),
2636 },
2637};
2638
2639static struct branch_clk oxilicx_axi_clk = {
2640 .cbcr_reg = OXILICX_AXI_CBCR,
2641 .has_sibling = 1,
2642 .base = &virt_bases[MMSS_BASE],
2643 .c = {
2644 .dbg_name = "oxilicx_axi_clk",
2645 .parent = &axi_clk_src.c,
2646 .ops = &clk_ops_branch,
2647 CLK_INIT(oxilicx_axi_clk.c),
2648 },
2649};
2650
2651static struct branch_clk venus0_ahb_clk = {
2652 .cbcr_reg = VENUS0_AHB_CBCR,
2653 .has_sibling = 1,
2654 .base = &virt_bases[MMSS_BASE],
2655 .c = {
2656 .dbg_name = "venus0_ahb_clk",
2657 .ops = &clk_ops_branch,
2658 CLK_INIT(venus0_ahb_clk.c),
2659 },
2660};
2661
2662static struct branch_clk venus0_axi_clk = {
2663 .cbcr_reg = VENUS0_AXI_CBCR,
2664 .has_sibling = 1,
2665 .base = &virt_bases[MMSS_BASE],
2666 .c = {
2667 .dbg_name = "venus0_axi_clk",
2668 .parent = &axi_clk_src.c,
2669 .ops = &clk_ops_branch,
2670 CLK_INIT(venus0_axi_clk.c),
2671 },
2672};
2673
2674static struct branch_clk venus0_vcodec0_clk = {
2675 .cbcr_reg = VENUS0_VCODEC0_CBCR,
Matt Wagantall57b74562013-07-03 19:24:53 -0700[diff] [blame]2676 .bcr_reg = VENUS0_BCR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2677 .has_sibling = 0,
2678 .base = &virt_bases[MMSS_BASE],
2679 .c = {
2680 .dbg_name = "venus0_vcodec0_clk",
2681 .parent = &vcodec0_clk_src.c,
2682 .ops = &clk_ops_branch,
2683 CLK_INIT(venus0_vcodec0_clk.c),
2684 },
2685};
2686
2687static struct measure_mux_entry measure_mux_MMSS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2688 { &mmss_mmssnoc_bto_ahb_clk.c, MMSS_BASE, 0x0002 },
2689 { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 },
2690 { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 },
2691 { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2692 { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b },
2693 { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c },
2694 { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d },
2695 { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e },
2696 { &venus0_axi_clk.c, MMSS_BASE, 0x000f },
2697 { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 },
2698 { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 },
2699 { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 },
2700 { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 },
2701 { &mdss_vsync_clk.c, MMSS_BASE, 0x001c },
2702 { &mdss_byte0_clk.c, MMSS_BASE, 0x001e },
2703 { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 },
2704 { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 },
2705 { &mdss_axi_clk.c, MMSS_BASE, 0x0024 },
2706 { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 },
2707 { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 },
2708 { &camss_gp0_clk.c, MMSS_BASE, 0x0027 },
2709 { &camss_gp1_clk.c, MMSS_BASE, 0x0028 },
2710 { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 },
2711 { &camss_mclk1_clk.c, MMSS_BASE, 0x002a },
2712 { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d },
2713 { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e },
2714 { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f },
2715 { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 },
2716 { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 },
2717 { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 },
2718 { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 },
2719 { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 },
2720 { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a },
2721 { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b },
2722 { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c },
2723 { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d },
2724 { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f },
2725 { &camss_csi0_clk.c, MMSS_BASE, 0x0041 },
2726 { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 },
2727 { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 },
2728 { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 },
2729 { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 },
2730 { &camss_csi1_clk.c, MMSS_BASE, 0x0046 },
2731 { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 },
2732 { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 },
2733 { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 },
2734 { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a },
2735 { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 },
Patrick Daly2a4ba832013-07-17 12:52:40 -0700[diff] [blame]2736 { &mmssnoc_ahb_clk.c, MMSS_BASE, 0x0001 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2737 {&dummy_clk, N_BASES, 0x0000},
2738};
2739
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2740static struct branch_clk q6ss_ahb_lfabif_clk = {
2741 .cbcr_reg = Q6SS_AHB_LFABIF_CBCR,
2742 .has_sibling = 1,
2743 .base = &virt_bases[LPASS_BASE],
2744 .c = {
2745 .dbg_name = "q6ss_ahb_lfabif_clk",
2746 .ops = &clk_ops_branch,
2747 CLK_INIT(q6ss_ahb_lfabif_clk.c),
2748 },
2749};
2750
2751static struct branch_clk q6ss_ahbm_clk = {
2752 .cbcr_reg = Q6SS_AHBM_CBCR,
2753 .has_sibling = 1,
2754 .base = &virt_bases[LPASS_BASE],
2755 .c = {
2756 .dbg_name = "q6ss_ahbm_clk",
2757 .ops = &clk_ops_branch,
2758 CLK_INIT(q6ss_ahbm_clk.c),
2759 },
2760};
2761
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2762static struct branch_clk q6ss_xo_clk = {
2763 .cbcr_reg = Q6SS_XO_CBCR,
2764 .has_sibling = 1,
2765 .bcr_reg = Q6SS_BCR,
2766 .base = &virt_bases[LPASS_BASE],
2767 .c = {
2768 .dbg_name = "q6ss_xo_clk",
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2769 .ops = &clk_ops_branch,
2770 CLK_INIT(q6ss_xo_clk.c),
2771 },
2772};
2773
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2774static struct measure_mux_entry measure_mux_LPASS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2775 { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d },
2776 { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2777 { &q6ss_xo_clk.c, LPASS_BASE, 0x002b },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2778 {&dummy_clk, N_BASES, 0x0000},
2779};
2780
2781
2782static DEFINE_CLK_MEASURE(apc0_m_clk);
2783static DEFINE_CLK_MEASURE(apc1_m_clk);
2784static DEFINE_CLK_MEASURE(apc2_m_clk);
2785static DEFINE_CLK_MEASURE(apc3_m_clk);
2786static DEFINE_CLK_MEASURE(l2_m_clk);
2787
2788static struct measure_mux_entry measure_mux_APSS[] = {
2789 {&apc0_m_clk, APCS_BASE, 0x00010},
2790 {&apc1_m_clk, APCS_BASE, 0x00114},
2791 {&apc2_m_clk, APCS_BASE, 0x00220},
2792 {&apc3_m_clk, APCS_BASE, 0x00324},
2793 {&l2_m_clk, APCS_BASE, 0x01000},
2794 {&dummy_clk, N_BASES, 0x0000}
2795};
2796
2797#define APCS_SH_PLL_MODE (0x000)
2798#define APCS_SH_PLL_L_VAL (0x004)
2799#define APCS_SH_PLL_M_VAL (0x008)
2800#define APCS_SH_PLL_N_VAL (0x00C)
2801#define APCS_SH_PLL_USER_CTL (0x010)
2802#define APCS_SH_PLL_CONFIG_CTL (0x014)
2803#define APCS_SH_PLL_STATUS (0x01C)
2804
2805enum vdd_sr2_pll_levels {
2806 VDD_SR2_PLL_OFF,
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2807 VDD_SR2_PLL_SVS,
2808 VDD_SR2_PLL_NOM,
2809 VDD_SR2_PLL_TUR,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2810 VDD_SR2_PLL_NUM
2811};
2812
Junjie Wubb5a79e2013-05-15 13:12:39 -0700[diff] [blame]2813static int vdd_sr2_levels[] = {
2814 0, RPM_REGULATOR_CORNER_NONE, /* VDD_SR2_PLL_OFF */
2815 1800000, RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_SR2_PLL_SVS */
2816 1800000, RPM_REGULATOR_CORNER_NORMAL, /* VDD_SR2_PLL_NOM */
2817 1800000, RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_SR2_PLL_TUR */
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]2818};
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2819
Patrick Daly653c0b52013-04-16 17:18:28 -0700[diff] [blame]2820static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
2821 vdd_sr2_levels, NULL);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2822
2823static struct pll_freq_tbl apcs_pll_freq[] = {
Patrick Daly83806032013-03-25 15:18:24 -0700[diff] [blame]2824 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2825 F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0),
2826 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyf363c252013-03-21 12:08:37 -0700[diff] [blame]2827 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2828 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Daly66e32aa2013-05-30 15:11:52 -0700[diff] [blame]2829 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
2830 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
2831 F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Daly5a66c082013-08-02 10:58:56 -0700[diff] [blame^]2832 F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
2833 F_APCS_PLL(1593600000, 83, 0x0, 0x1, 0x0, 0x0, 0x0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2834 PLL_F_END
2835};
2836
2837static struct pll_clk a7sspll = {
2838 .mode_reg = (void __iomem *)APCS_SH_PLL_MODE,
2839 .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL,
2840 .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL,
2841 .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL,
2842 .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL,
2843 .status_reg = (void __iomem *)APCS_SH_PLL_STATUS,
2844 .freq_tbl = apcs_pll_freq,
2845 .masks = {
2846 .vco_mask = BM(29, 28),
2847 .pre_div_mask = BIT(12),
2848 .post_div_mask = BM(9, 8),
2849 .mn_en_mask = BIT(24),
2850 .main_output_mask = BIT(0),
2851 },
2852 .base = &virt_bases[APCS_PLL_BASE],
2853 .c = {
Patrick Daly9bdc8a52013-03-21 19:12:40 -0700[diff] [blame]2854 .parent = &xo_a_clk.c,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2855 .dbg_name = "a7sspll",
2856 .ops = &clk_ops_sr2_pll,
2857 .vdd_class = &vdd_sr2_pll,
2858 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]2859 [VDD_SR2_PLL_SVS] = 1000000000,
2860 [VDD_SR2_PLL_NOM] = 1900000000,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2861 },
2862 .num_fmax = VDD_SR2_PLL_NUM,
2863 CLK_INIT(a7sspll.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2864 },
2865};
2866
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2867static struct clk_freq_tbl ftbl_kpss_ahb_clk[] = {
2868 F_GCC(19200000, xo_a_clk, 0, 0, 0),
2869 F_GCC(37500000, gpll0, 16, 0, 0),
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2870 F_END
2871};
2872
2873static struct rcg_clk kpss_ahb_clk_src = {
2874 .cmd_rcgr_reg = KPSS_AHB_CMD_RCGR,
2875 .set_rate = set_rate_hid,
2876 .freq_tbl = ftbl_kpss_ahb_clk,
2877 .current_freq = &rcg_dummy_freq,
2878 .base = &virt_bases[GCC_BASE],
2879 .c = {
2880 .dbg_name = "kpss_ahb_clk_src",
2881 .ops = &clk_ops_rcg,
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]2882 CLK_INIT(kpss_ahb_clk_src.c),
2883 },
2884};
2885
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2886static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
2887static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
2888static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
2889static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
2890static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
2891static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX);
2892
2893static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
2894static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
2895static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX);
2896static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX);
2897static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX);
2898static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
2899static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
2900
2901static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX);
2902
Patrick Daly4aef16c2013-04-17 15:44:12 -0700[diff] [blame]2903static DEFINE_CLK_VOTER(qseecom_ce1_clk_src, &ce1_clk_src.c, 100000000);
2904static DEFINE_CLK_VOTER(scm_ce1_clk_src, &ce1_clk_src.c, 100000000);
Hariprasad Dhalinarasimhae898bb12013-06-07 14:12:14 -0700[diff] [blame]2905static DEFINE_CLK_VOTER(gud_ce1_clk_src, &ce1_clk_src.c, 100000000);
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]2906
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]2907static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, &xo.c);
2908static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, &xo.c);
2909static DEFINE_CLK_BRANCH_VOTER(cxo_pil_mss_clk, &xo.c);
2910static DEFINE_CLK_BRANCH_VOTER(cxo_wlan_clk, &xo.c);
2911static DEFINE_CLK_BRANCH_VOTER(cxo_pil_pronto_clk, &xo.c);
Vikram Mulukutlaae4ae302013-04-24 12:00:28 -0700[diff] [blame]2912static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, &xo.c);
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]2913
2914
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2915#ifdef CONFIG_DEBUG_FS
2916static int measure_clk_set_parent(struct clk *c, struct clk *parent)
2917{
2918 struct measure_clk *clk = to_measure_clk(c);
2919 unsigned long flags;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2920 u32 regval, clk_sel, found = 0;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2921 int i;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2922 static const struct measure_mux_entry *array[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2923 measure_mux_GCC,
2924 measure_mux_MMSS,
2925 measure_mux_LPASS,
2926 measure_mux_APSS,
2927 NULL
2928 };
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2929 const struct measure_mux_entry *mux = array[0];
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2930
2931 if (!parent)
2932 return -EINVAL;
2933
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2934 for (i = 0; array[i] && !found; i++) {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2935 for (mux = array[i]; mux->c != &dummy_clk; mux++)
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2936 if (mux->c == parent) {
2937 found = 1;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2938 break;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2939 }
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2940 }
2941
2942 if (mux->c == &dummy_clk)
2943 return -EINVAL;
2944
2945 spin_lock_irqsave(&local_clock_reg_lock, flags);
2946 /*
2947 * Program the test vector, measurement period (sample_ticks)
2948 * and scaling multiplier.
2949 */
2950 clk->sample_ticks = 0x10000;
2951 clk->multiplier = 1;
2952
2953 switch (mux->base) {
2954
2955 case GCC_BASE:
2956 writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2957 clk_sel = mux->debug_mux;
2958 break;
2959
2960 case MMSS_BASE:
2961 writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2962 clk_sel = 0x02C;
2963 regval = BVAL(11, 0, mux->debug_mux);
2964 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2965
2966 /* Activate debug clock output */
2967 regval |= BIT(16);
2968 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2969 break;
2970
2971 case LPASS_BASE:
2972 writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2973 clk_sel = 0x161;
2974 regval = BVAL(11, 0, mux->debug_mux);
2975 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2976
2977 /* Activate debug clock output */
2978 regval |= BIT(20);
2979 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2980 break;
2981
2982 case APCS_BASE:
2983 clk->multiplier = 4;
2984 clk_sel = 362;
2985 regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG));
2986 regval &= ~0xC0037335;
2987 /* configure a divider of 4 */
2988 regval = BVAL(31, 30, 0x3) | mux->debug_mux;
2989 writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG));
2990 break;
2991
2992 default:
2993 return -EINVAL;
2994 }
2995
2996 /* Set debug mux clock index */
2997 regval = BVAL(8, 0, clk_sel);
2998 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2999
3000 /* Activate debug clock output */
3001 regval |= BIT(16);
3002 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
3003
3004 /* Make sure test vector is set before starting measurements. */
3005 mb();
3006 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3007
3008 return 0;
3009}
3010
3011/* Sample clock for 'ticks' reference clock ticks. */
3012static u32 run_measurement(unsigned ticks)
3013{
3014 /* Stop counters and set the XO4 counter start value. */
3015 writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
3016
3017 /* Wait for timer to become ready. */
3018 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3019 BIT(25)) != 0)
3020 cpu_relax();
3021
3022 /* Run measurement and wait for completion. */
3023 writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
3024 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3025 BIT(25)) == 0)
3026 cpu_relax();
3027
3028 /* Return measured ticks. */
3029 return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
3030 BM(24, 0);
3031}
3032
3033/*
3034 * Perform a hardware rate measurement for a given clock.
3035 * FOR DEBUG USE ONLY: Measurements take ~15 ms!
3036 */
3037static unsigned long measure_clk_get_rate(struct clk *c)
3038{
3039 unsigned long flags;
3040 u32 gcc_xo4_reg_backup;
3041 u64 raw_count_short, raw_count_full;
3042 struct measure_clk *clk = to_measure_clk(c);
3043 unsigned ret;
3044
3045 ret = clk_prepare_enable(&xo.c);
3046 if (ret) {
3047 pr_warn("CXO clock failed to enable. Can't measure\n");
3048 return 0;
3049 }
3050
3051 spin_lock_irqsave(&local_clock_reg_lock, flags);
3052
3053 /* Enable CXO/4 and RINGOSC branch. */
3054 gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3055 writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3056
3057 /*
3058 * The ring oscillator counter will not reset if the measured clock
3059 * is not running. To detect this, run a short measurement before
3060 * the full measurement. If the raw results of the two are the same
3061 * then the clock must be off.
3062 */
3063
3064 /* Run a short measurement. (~1 ms) */
3065 raw_count_short = run_measurement(0x1000);
3066 /* Run a full measurement. (~14 ms) */
3067 raw_count_full = run_measurement(clk->sample_ticks);
3068
3069 writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
3070
3071 /* Return 0 if the clock is off. */
3072 if (raw_count_full == raw_count_short) {
3073 ret = 0;
3074 } else {
3075 /* Compute rate in Hz. */
3076 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
3077 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
3078 ret = (raw_count_full * clk->multiplier);
3079 }
3080
Patrick Dalye095edb2013-05-23 14:13:09 -0700[diff] [blame]3081 /* Set pin to gcc_debug_clock, enable output mode, disable input mode */
3082 writel_relaxed(0x51200, GCC_REG_BASE(PLLTEST_PAD_CFG));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3083 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3084
3085 clk_disable_unprepare(&xo.c);
3086
3087 return ret;
3088}
3089
3090#else /* !CONFIG_DEBUG_FS */
3091static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
3092{
3093 return -EINVAL;
3094}
3095
3096static unsigned long measure_clk_get_rate(struct clk *clk)
3097{
3098 return 0;
3099}
3100#endif /* CONFIG_DEBUG_FS */
3101
3102static struct clk_ops clk_ops_measure = {
3103 .set_parent = measure_clk_set_parent,
3104 .get_rate = measure_clk_get_rate,
3105};
3106
3107static struct measure_clk measure_clk = {
3108 .c = {
3109 .dbg_name = "measure_clk",
3110 .ops = &clk_ops_measure,
3111 CLK_INIT(measure_clk.c),
3112 },
3113 .multiplier = 1,
3114};
3115
3116static struct clk_lookup msm_clocks_8226[] = {
3117 /* Debug Clocks */
3118 CLK_LOOKUP("measure", measure_clk.c, "debug"),
3119 CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""),
3120 CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""),
3121 CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""),
3122 CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""),
3123 CLK_LOOKUP("l2_m_clk", l2_m_clk, ""),
3124
Vikram Mulukutlaae4ae302013-04-24 12:00:28 -0700[diff] [blame]3125 /* LPM Resources */
3126 CLK_LOOKUP("xo", cxo_lpm_clk.c, "fc4281d0.qcom,mpm"),
3127
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3128 /* PIL-LPASS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3129 CLK_LOOKUP("xo", cxo_pil_lpass_clk.c, "fe200000.qcom,lpass"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3130 CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"),
3131 CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"),
3132 CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"),
3133 CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"),
3134
3135 /* PIL-MODEM */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3136 CLK_LOOKUP("xo", cxo_pil_mss_clk.c, "fc880000.qcom,mss"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3137 CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"),
3138 CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
3139 CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
Madan Mohan Koyyalamudi497b7002013-06-19 17:32:39 -0700[diff] [blame]3140 /* NFC */
3141 CLK_LOOKUP("ref_clk", cxo_d1_a_pin.c, "2-000e"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3142 /* PIL-PRONTO */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3143 CLK_LOOKUP("xo", cxo_pil_pronto_clk.c, "fb21b000.qcom,pronto"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3144
3145 /* PIL-VENUS */
3146 CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"),
3147 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"),
3148 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3149 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"),
3150 CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3151
3152 /* ACPUCLOCK */
3153 CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
3154 CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
3155 CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]3156 CLK_LOOKUP("kpss_ahb", kpss_ahb_clk_src.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3157
3158 /* WCNSS CLOCKS */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3159 CLK_LOOKUP("xo", cxo_wlan_clk.c, "fb000000.qcom,wcnss-wlan"),
Vikram Mulukutla7e5b3112013-04-15 16:32:40 -0700[diff] [blame]3160 CLK_LOOKUP("rf_clk", cxo_a1.c, "fb000000.qcom,wcnss-wlan"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3161
3162 /* BUS DRIVER */
3163 CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"),
3164 CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"),
3165 CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"),
3166 CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"),
3167 CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"),
3168 CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"),
3169 CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"),
3170 CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"),
3171 CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""),
3172 CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"),
3173 CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"),
3174 CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3175 CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3176
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3177 /* CoreSight clocks */
3178 CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"),
3179 CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"),
3180 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"),
3181 CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"),
3182 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"),
3183 CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"),
3184 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"),
3185 CLK_LOOKUP("core_clk", qdss_clk.c, "fc345000.funnel"),
3186 CLK_LOOKUP("core_clk", qdss_clk.c, "fc364000.funnel"),
3187 CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"),
3188 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.etm"),
3189 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.etm"),
3190 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.etm"),
3191 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3192 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.jtagmm"),
3193 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.jtagmm"),
3194 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.jtagmm"),
3195 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3196 CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"),
3197 CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"),
3198 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"),
3199 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"),
3200 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"),
3201 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"),
3202 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"),
3203 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"),
3204 CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"),
3205 CLK_LOOKUP("core_clk", qdss_clk.c, "fc340000.cti"),
3206 CLK_LOOKUP("core_clk", qdss_clk.c, "fc341000.cti"),
3207 CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"),
3208 CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"),
3209 CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"),
Aparna Dasca6aa3a2013-04-02 16:25:27 -0700[diff] [blame]3210 CLK_LOOKUP("core_clk", qdss_clk.c, "fd828018.hwevent"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3211
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3212 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
3213 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
3214 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"),
3215 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"),
3216 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"),
3217 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"),
3218 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"),
3219 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc345000.funnel"),
3220 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc364000.funnel"),
3221 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"),
3222 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.etm"),
3223 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.etm"),
3224 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.etm"),
3225 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.etm"),
Aparna Das664239c2013-05-03 20:13:50 -0700[diff] [blame]3226 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.jtagmm"),
3227 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.jtagmm"),
3228 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.jtagmm"),
3229 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3230 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"),
3231 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"),
3232 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"),
3233 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"),
3234 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"),
3235 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"),
3236 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"),
3237 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"),
3238 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"),
3239 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc340000.cti"),
3240 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc341000.cti"),
3241 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"),
3242 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"),
3243 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"),
Aparna Dasca6aa3a2013-04-02 16:25:27 -0700[diff] [blame]3244 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fd828018.hwevent"),
3245
3246 CLK_LOOKUP("core_mmss_clk", mmss_misc_ahb_clk.c, "fd828018.hwevent"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3247
3248 /* HSUSB-OTG Clocks */
Patrick Dalya5296072013-03-19 12:18:04 -0700[diff] [blame]3249 CLK_LOOKUP("xo", cxo_otg_clk.c, "f9a55000.usb"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3250 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
3251 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
Mayank Ranaf14cb8d2013-07-24 17:09:17 +0530[diff] [blame]3252 CLK_LOOKUP("sleep_clk", gcc_usb2a_phy_sleep_clk.c, "f9a55000.usb"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3253
3254 /* SPS CLOCKS */
3255 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"),
3256 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"),
3257 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
3258 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
3259
3260 /* I2C Clocks */
3261 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"),
3262 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"),
3263
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]3264 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"),
3265 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, "f9927000.i2c"),
3266
Madan Mohan Koyyalamudi497b7002013-06-19 17:32:39 -0700[diff] [blame]3267 /* I2C Clocks nfc */
3268 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9925000.i2c"),
3269 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, "f9925000.i2c"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3270 /* lsuart-v14 Clocks */
3271 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"),
3272 CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),
3273
3274 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"),
3275 CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"),
3276
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]3277 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"),
3278 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3279
3280 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"),
3281 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"),
3282 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3283 CLK_LOOKUP("core_clk_src", qseecom_ce1_clk_src.c, "qseecom"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3284
Hariprasad Dhalinarasimhae898bb12013-06-07 14:12:14 -0700[diff] [blame]3285 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "mcd"),
3286 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "mcd"),
3287 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "mcd"),
3288 CLK_LOOKUP("core_clk_src", gud_ce1_clk_src.c, "mcd"),
3289
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3290 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "scm"),
3291 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "scm"),
3292 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "scm"),
Patrick Dalye07324c2013-03-27 18:02:49 -0700[diff] [blame]3293 CLK_LOOKUP("core_clk_src", scm_ce1_clk_src.c, "scm"),
3294
3295 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, ""),
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3296
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3297 /* SDCC */
3298 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"),
3299 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"),
3300 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
3301 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
3302
3303 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
3304 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
3305 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
3306 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
3307
3308 CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
3309 CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
3310
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3311 CLK_LOOKUP("bus_clk", pnoc_clk.c, ""),
3312 CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""),
3313 CLK_LOOKUP("bus_clk", snoc_clk.c, ""),
3314 CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""),
3315 CLK_LOOKUP("bus_clk", cnoc_clk.c, ""),
3316 CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""),
3317 CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""),
3318 CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""),
3319 CLK_LOOKUP("bus_clk", bimc_clk.c, ""),
3320 CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""),
3321 CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
3322
3323 CLK_LOOKUP("gpll0", gpll0.c, ""),
3324 CLK_LOOKUP("gpll1", gpll1.c, ""),
3325 CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""),
3326 CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3327
3328 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
3329 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
3330 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3331 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
3332 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
3333 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
3334 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
3335 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
3336 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
3337 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
3338 CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
3339 CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""),
3340 CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""),
3341 CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""),
3342 CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
3343 CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
3344 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""),
3345 CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""),
3346 CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
3347 CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
3348
3349 CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"),
3350 CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"),
3351 CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"),
3352 CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"),
3353 CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"),
3354 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"),
3355 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"),
3356 CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"),
3357
3358 /* Multimedia clocks */
3359 CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"),
3360 CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"),
3361 CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
Aravind Venkateswaran6b6d9c42013-05-06 16:10:03 -0700[diff] [blame]3362 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd922800.qcom,mdss_dsi"),
3363 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd922800.qcom,mdss_dsi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3364
Adrian Salido-Morenof840a032013-03-01 23:10:03 -0800[diff] [blame]3365 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"),
3366 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"),
3367 CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"),
3368 CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "fd900000.qcom,mdss_mdp"),
3369 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"),
3370 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3371
3372 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"),
3373 CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"),
3374
Matt Wagantallb8cba292013-04-11 15:45:17 -0700[diff] [blame]3375 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fd8c1024.qcom,gdsc"),
3376 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd8c2304.qcom,gdsc"),
3377 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd8c2304.qcom,gdsc"),
3378 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fd8c35a4.qcom,gdsc"),
3379 CLK_LOOKUP("core_clk", camss_vfe_vfe0_clk.c, "fd8c36a4.qcom,gdsc"),
3380 CLK_LOOKUP("csi_clk", camss_csi_vfe0_clk.c, "fd8c36a4.qcom,gdsc"),
3381 CLK_LOOKUP("cpp_clk", camss_vfe_cpp_clk.c, "fd8c36a4.qcom,gdsc"),
3382 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fd8c4034.qcom,gdsc"),
3383
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3384 /* MM sensor clocks */
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3385 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6f.qcom,camera"),
Ju He0dd84ad2013-06-18 09:59:13 +0800[diff] [blame]3386 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3387 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6d.qcom,camera"),
Liu Su1e4c0ba2013-06-08 23:30:01 +0800[diff] [blame]3388 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6a.qcom,camera"),
feim0aaee482013-06-08 15:26:20 +0800[diff] [blame]3389 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6c.qcom,camera"),
Ju Hebbe039e2013-07-29 04:45:26 -0700[diff] [blame]3390 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "20.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3391 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6f.qcom,camera"),
Ju He0dd84ad2013-06-18 09:59:13 +0800[diff] [blame]3392 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "90.qcom,camera"),
Su Liud1c66ee2013-03-22 15:29:48 -0700[diff] [blame]3393 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6d.qcom,camera"),
Liu Su1e4c0ba2013-06-08 23:30:01 +0800[diff] [blame]3394 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6a.qcom,camera"),
feim0aaee482013-06-08 15:26:20 +0800[diff] [blame]3395 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6c.qcom,camera"),
Ju Hebbe039e2013-07-29 04:45:26 -0700[diff] [blame]3396 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "20.qcom,camera"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3397
Ju Hef80f40b2013-07-18 17:06:32 +0800[diff] [blame]3398 /* eeprom clocks */
3399 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6c.qcom,eeprom"),
3400 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6c.qcom,eeprom"),
Wang Wenbinadb94482013-08-07 14:26:09 +0800[diff] [blame]3401 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "18.qcom,eeprom"),
3402 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "18.qcom,eeprom"),
Su Liu56664932013-08-14 10:20:06 +0800[diff] [blame]3403 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6b.qcom,eeprom"),
3404 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6b.qcom,eeprom"),
Ju Hef80f40b2013-07-18 17:06:32 +0800[diff] [blame]3405
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3406 /* CCI clocks */
3407 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3408 "fda0c000.qcom,cci"),
3409 CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c,
3410 "fda0c000.qcom,cci"),
3411 CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"),
3412 CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"),
3413
3414 /* CSIPHY clocks */
3415 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3416 "fda0ac00.qcom,csiphy"),
3417 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3418 "fda0ac00.qcom,csiphy"),
3419 CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c,
3420 "fda0ac00.qcom,csiphy"),
3421 CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c,
3422 "fda0ac00.qcom,csiphy"),
3423 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3424 "fda0b000.qcom,csiphy"),
3425 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3426 "fda0b000.qcom,csiphy"),
3427 CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c,
3428 "fda0b000.qcom,csiphy"),
3429 CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c,
3430 "fda0b000.qcom,csiphy"),
3431
3432 /* CSID clocks */
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3433 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3434 "fda08000.qcom,csid"),
3435 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3436 "fda08000.qcom,csid"),
3437 CLK_LOOKUP("csi_ahb_clk", camss_csi0_ahb_clk.c,
3438 "fda08000.qcom,csid"),
3439 CLK_LOOKUP("csi_src_clk", csi0_clk_src.c,
3440 "fda08000.qcom,csid"),
3441 CLK_LOOKUP("csi_phy_clk", camss_csi0phy_clk.c,
3442 "fda08000.qcom,csid"),
3443 CLK_LOOKUP("csi_clk", camss_csi0_clk.c,
3444 "fda08000.qcom,csid"),
3445 CLK_LOOKUP("csi_pix_clk", camss_csi0pix_clk.c,
3446 "fda08000.qcom,csid"),
3447 CLK_LOOKUP("csi_rdi_clk", camss_csi0rdi_clk.c,
3448 "fda08000.qcom,csid"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3449
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3450
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3451 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
Su Liu2d73d772013-04-24 23:55:32 -0700[diff] [blame]3452 "fda08400.qcom,csid"),
3453 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3454 "fda08400.qcom,csid"),
3455 CLK_LOOKUP("csi_ahb_clk", camss_csi1_ahb_clk.c,
3456 "fda08400.qcom,csid"),
3457 CLK_LOOKUP("csi_src_clk", csi1_clk_src.c,
3458 "fda08400.qcom,csid"),
3459 CLK_LOOKUP("csi_phy_clk", camss_csi1phy_clk.c,
3460 "fda08400.qcom,csid"),
3461 CLK_LOOKUP("csi_clk", camss_csi1_clk.c,
3462 "fda08400.qcom,csid"),
3463 CLK_LOOKUP("csi_pix_clk", camss_csi1pix_clk.c,
3464 "fda08400.qcom,csid"),
3465 CLK_LOOKUP("csi_rdi_clk", camss_csi1rdi_clk.c,
3466 "fda08400.qcom,csid"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3467
3468 /* ISPIF clocks */
Sreesudhan Ramakrish Ramkumarecdcfce2013-04-17 12:58:26 -0700[diff] [blame]3469 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3470 "fda0a000.qcom,ispif"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3471 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3472 "fda0a000.qcom,ispif"),
3473 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3474 "fda0a000.qcom,ispif"),
3475
3476 /* VFE clocks */
3477 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3478 "fda10000.qcom,vfe"),
3479 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"),
3480 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3481 "fda10000.qcom,vfe"),
3482 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3483 "fda10000.qcom,vfe"),
3484 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"),
3485 CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"),
3486
3487 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c,
3488 "fda44000.qcom,iommu"),
3489 CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"),
3490 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"),
3491
3492 /* Jpeg Clocks */
3493 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"),
3494 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3495 "fda1c000.qcom,jpeg"),
3496 CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c,
3497 "fda1c000.qcom,jpeg"),
3498 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3499 "fda1c000.qcom,jpeg"),
3500
3501 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"),
3502 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3503 "fda64000.qcom,iommu"),
3504 CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c,
3505 "fda64000.qcom,iommu"),
3506
Su Liudb7b2062013-03-14 20:57:15 -0700[diff] [blame]3507 CLK_LOOKUP("micro_iface_clk", camss_micro_ahb_clk.c,
3508 "fda04000.qcom,cpp"),
3509 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3510 "fda04000.qcom,cpp"),
3511 CLK_LOOKUP("cpp_iface_clk", camss_vfe_cpp_ahb_clk.c,
3512 "fda04000.qcom,cpp"),
3513 CLK_LOOKUP("cpp_core_clk", camss_vfe_cpp_clk.c, "fda04000.qcom,cpp"),
3514 CLK_LOOKUP("cpp_bus_clk", camss_vfe_vfe_axi_clk.c, "fda04000.qcom,cpp"),
3515 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda04000.qcom,cpp"),
3516 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3517 "fda04000.qcom,cpp"),
3518 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda04000.qcom,cpp"),
3519
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3520 /* KGSL Clocks */
3521 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"),
3522 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"),
liu zhongc45eb8b2013-02-21 11:50:24 -0800[diff] [blame]3523 CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c,
3524 "fdb00000.qcom,kgsl-3d0"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3525
3526 CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"),
3527 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"),
3528 CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"),
3529
3530 CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3531
3532 /* Venus Clocks */
3533 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"),
3534 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"),
3535 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"),
3536
3537 CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c,
3538 "fdc84000.qcom,iommu"),
3539 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"),
3540 CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"),
Hariprasad Dhalinarasimha92a13222013-03-12 11:59:28 -0700[diff] [blame]3541 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3542 CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""),
3543 CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""),
3544 CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""),
3545
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3546 CLK_LOOKUP("", mmss_mmssnoc_bto_ahb_clk.c, ""),
3547 CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""),
3548 CLK_LOOKUP("", mmss_s0_axi_clk.c, ""),
Bhalchandra Gajared5a4ba72013-03-11 16:15:13 -0700[diff] [blame]3549
3550 /* Audio clocks */
3551 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.224"),
3552 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.4106"),
3553 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16384"),
3554 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16386"),
3555 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16390"),
3556 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16391"),
3557
Hariprasad Dhalinarasimha1fa54392013-03-21 15:57:51 -0700[diff] [blame]3558 /* Add QCEDEV clocks */
3559 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd400000.qcom,qcedev"),
3560 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd400000.qcom,qcedev"),
3561 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd400000.qcom,qcedev"),
3562 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd400000.qcom,qcedev"),
3563
3564 /* Add QCRYPTO clocks */
3565 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd404000.qcom,qcrypto"),
3566 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd404000.qcom,qcrypto"),
3567 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd404000.qcom,qcrypto"),
3568 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd404000.qcom,qcrypto"),
3569
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]3570 /* DSI PLL clocks */
3571 CLK_LOOKUP("", dsi_vco_clk_8226.c, ""),
3572 CLK_LOOKUP("", analog_postdiv_clk_8226.c, ""),
3573 CLK_LOOKUP("", indirect_path_div2_clk_8226.c, ""),
3574 CLK_LOOKUP("", pixel_clk_src_8226.c, ""),
3575 CLK_LOOKUP("", byte_mux_8226.c, ""),
3576 CLK_LOOKUP("", byte_clk_src_8226.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3577};
3578
3579static struct clk_lookup msm_clocks_8226_rumi[] = {
3580 CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3581 CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3582 CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
3583 CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
3584 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
3585 CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
3586 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
3587 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
3588 CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
3589 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
3590};
3591
3592struct clock_init_data msm8226_rumi_clock_init_data __initdata = {
3593 .table = msm_clocks_8226_rumi,
3594 .size = ARRAY_SIZE(msm_clocks_8226_rumi),
3595};
3596
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3597static void __init reg_init(void)
3598{
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3599 u32 regval;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3600
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3601 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
3602 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3603 regval |= BIT(0);
3604 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3605
3606 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3607 * No clocks need to be enabled during sleep.
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3608 */
3609 writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3610}
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3611
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3612static void __init msm8226_clock_post_init(void)
3613{
Vikram Mulukutla441db7a2013-03-15 13:56:33 -0700[diff] [blame]3614 /*
3615 * Hold an active set vote for CXO; this is because CXO is expected
3616 * to remain on whenever CPUs aren't power collapsed.
3617 */
3618 clk_prepare_enable(&xo_a_clk.c);
3619
Patrick Daly856c2fe2013-07-18 12:59:40 -0700[diff] [blame]3620 /*
3621 * Handoff will override the prepare enable count as well as the rate
3622 * Set them again.
3623 */
3624 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
3625 clk_prepare_enable(&mmssnoc_ahb_a_clk.c);
3626
Patrick Dalyfd3df102013-05-28 18:08:22 -0700[diff] [blame]3627 /* Set an initial rate (fmax at nominal) on the MMSSNOC AXI clock */
3628 clk_set_rate(&axi_clk_src.c, 200000000);
3629
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3630 /* Set rates for single-rate clocks. */
3631 clk_set_rate(&usb_hs_system_clk_src.c,
3632 usb_hs_system_clk_src.freq_tbl[0].freq_hz);
3633 clk_set_rate(&usb_hsic_clk_src.c,
3634 usb_hsic_clk_src.freq_tbl[0].freq_hz);
3635 clk_set_rate(&usb_hsic_io_cal_clk_src.c,
3636 usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz);
3637 clk_set_rate(&usb_hsic_system_clk_src.c,
3638 usb_hsic_system_clk_src.freq_tbl[0].freq_hz);
3639 clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz);
3640 clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz);
3641 clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz);
3642 clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz);
3643 clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz);
3644 clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz);
Patrick Daly01d4c1d2013-05-22 19:10:55 -0700[diff] [blame]3645
3646 clk_set_rate(&kpss_ahb_clk_src.c, 19200000);
3647 clk_prepare_enable(&kpss_ahb_clk_src.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3648}
3649
3650#define GCC_CC_PHYS 0xFC400000
3651#define GCC_CC_SIZE SZ_16K
3652
3653#define MMSS_CC_PHYS 0xFD8C0000
3654#define MMSS_CC_SIZE SZ_256K
3655
3656#define LPASS_CC_PHYS 0xFE000000
3657#define LPASS_CC_SIZE SZ_256K
3658
3659#define APCS_KPSS_SH_PLL_PHYS 0xF9016000
3660#define APCS_KPSS_SH_PLL_SIZE SZ_64
3661
3662#define APCS_KPSS_GLB_PHYS 0xF9011000
3663#define APCS_KPSS_GLB_SIZE SZ_4K
3664
3665
3666static void __init msm8226_clock_pre_init(void)
3667{
3668 virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE);
3669 if (!virt_bases[GCC_BASE])
3670 panic("clock-8226: Unable to ioremap GCC memory!");
3671
3672 virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE);
3673 if (!virt_bases[MMSS_BASE])
3674 panic("clock-8226: Unable to ioremap MMSS_CC memory!");
3675
3676 virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE);
3677 if (!virt_bases[LPASS_BASE])
3678 panic("clock-8226: Unable to ioremap LPASS_CC memory!");
3679
3680 virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS,
3681 APCS_KPSS_GLB_SIZE);
3682 if (!virt_bases[APCS_BASE])
3683 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3684
3685 virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS,
3686 APCS_KPSS_SH_PLL_SIZE);
3687 if (!virt_bases[APCS_PLL_BASE])
3688 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3689
3690 clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
3691
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3692 vdd_dig.regulator[0] = regulator_get(NULL, "vdd_dig");
3693 if (IS_ERR(vdd_dig.regulator[0]))
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3694 panic("clock-8226: Unable to get the vdd_dig regulator!");
3695
Patrick Dalyebc26bc2013-02-05 11:49:07 -0800[diff] [blame]3696 vdd_sr2_pll.regulator[0] = regulator_get(NULL, "vdd_sr2_pll");
3697 if (IS_ERR(vdd_sr2_pll.regulator[0]))
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3698 panic("clock-8226: Unable to get the sr2_pll regulator!");
3699
Patrick Daly6fb589a2013-03-29 17:55:55 -0700[diff] [blame]3700 vdd_sr2_pll.regulator[1] = regulator_get(NULL, "vdd_sr2_dig");
3701 if (IS_ERR(vdd_sr2_pll.regulator[1]))
3702 panic("clock-8226: Unable to get the vdd_sr2_dig regulator!");
3703
Patrick Daly856c2fe2013-07-18 12:59:40 -0700[diff] [blame]3704
3705 enable_rpm_scaling();
3706
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3707 /*
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3708 * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB
3709 * source. Sleep set vote is 0.
3710 * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to
3711 * access mmss clock controller registers.
3712 */
3713 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
Patrick Daly856c2fe2013-07-18 12:59:40 -0700[diff] [blame]3714 clk_prepare_enable(&mmssnoc_ahb_a_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3715
3716 reg_init();
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3717
Patrick Dalyd3fd03f2013-03-08 19:01:18 -0800[diff] [blame]3718 /* v2 specific changes */
3719 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
3720 cpp_clk_src.c.fmax = camss_vfe_cpp_fmax_v2;
3721 vfe0_clk_src.c.fmax = camss_vfe_vfe0_fmax_v2;
3722 }
3723
Aravind Venkateswaran78b73252013-05-08 18:25:21 -0700[diff] [blame]3724 clk_ops_pixel_clock = clk_ops_pixel;
3725 clk_ops_pixel_clock.set_rate = set_rate_pixel;
3726 clk_ops_pixel_clock.round_rate = round_rate_pixel;
3727
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3728 /*
3729 * MDSS needs the ahb clock and needs to init before we register the
3730 * lookup table.
3731 */
3732 mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3733}
3734
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3735struct clock_init_data msm8226_clock_init_data __initdata = {
3736 .table = msm_clocks_8226,
3737 .size = ARRAY_SIZE(msm_clocks_8226),
3738 .pre_init = msm8226_clock_pre_init,
3739 .post_init = msm8226_clock_post_init,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3740};