blob: 504f19b2af458d7e4da5ada45e71c72a99416222 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090012#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070013
14#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15#define CARDBUS_RESERVE_BUSNR 3
16#define PCI_CFG_SPACE_SIZE 256
17#define PCI_CFG_SPACE_EXP_SIZE 4096
18
19/* Ugh. Need to stop exporting this to modules. */
20LIST_HEAD(pci_root_buses);
21EXPORT_SYMBOL(pci_root_buses);
22
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080023
24static int find_anything(struct device *dev, void *data)
25{
26 return 1;
27}
28
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070029/*
30 * Some device drivers need know if pci is initiated.
31 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080032 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070033 */
34int no_pci_devices(void)
35{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080036 struct device *dev;
37 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070038
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080039 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
40 no_devices = (dev == NULL);
41 put_device(dev);
42 return no_devices;
43}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070044EXPORT_SYMBOL(no_pci_devices);
45
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#ifdef HAVE_PCI_LEGACY
47/**
48 * pci_create_legacy_files - create legacy I/O port and memory files
49 * @b: bus to create files under
50 *
51 * Some platforms allow access to legacy I/O port and ISA memory space on
52 * a per-bus basis. This routine creates the files and ties them into
53 * their associated read, write and mmap files from pci-sysfs.c
54 */
55static void pci_create_legacy_files(struct pci_bus *b)
56{
Eric Sesterhennf5afe802006-02-28 15:34:49 +010057 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 GFP_ATOMIC);
59 if (b->legacy_io) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070060 b->legacy_io->attr.name = "legacy_io";
61 b->legacy_io->size = 0xffff;
62 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 b->legacy_io->read = pci_read_legacy_io;
64 b->legacy_io->write = pci_write_legacy_io;
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040065 device_create_bin_file(&b->dev, b->legacy_io);
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
67 /* Allocated above after the legacy_io struct */
68 b->legacy_mem = b->legacy_io + 1;
69 b->legacy_mem->attr.name = "legacy_mem";
70 b->legacy_mem->size = 1024*1024;
71 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 b->legacy_mem->mmap = pci_mmap_legacy_mem;
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040073 device_create_bin_file(&b->dev, b->legacy_mem);
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 }
75}
76
77void pci_remove_legacy_files(struct pci_bus *b)
78{
79 if (b->legacy_io) {
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040080 device_remove_bin_file(&b->dev, b->legacy_io);
81 device_remove_bin_file(&b->dev, b->legacy_mem);
Linus Torvalds1da177e2005-04-16 15:20:36 -070082 kfree(b->legacy_io); /* both are allocated here */
83 }
84}
85#else /* !HAVE_PCI_LEGACY */
86static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
87void pci_remove_legacy_files(struct pci_bus *bus) { return; }
88#endif /* HAVE_PCI_LEGACY */
89
90/*
91 * PCI Bus Class Devices
92 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040093static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
94 struct device_attribute *attr,
Alan Cox4327edf2005-09-10 00:25:49 -070095 char *buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070096{
Linus Torvalds1da177e2005-04-16 15:20:36 -070097 int ret;
Alan Cox4327edf2005-09-10 00:25:49 -070098 cpumask_t cpumask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400100 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
102 if (ret < PAGE_SIZE)
103 buf[ret++] = '\n';
104 return ret;
105}
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400106DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
108/*
109 * PCI Bus Class
110 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400111static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400113 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115 if (pci_bus->bridge)
116 put_device(pci_bus->bridge);
117 kfree(pci_bus);
118}
119
120static struct class pcibus_class = {
121 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400122 .dev_release = &release_pcibus_dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123};
124
125static int __init pcibus_class_init(void)
126{
127 return class_register(&pcibus_class);
128}
129postcore_initcall(pcibus_class_init);
130
131/*
132 * Translate the low bits of the PCI base
133 * to the resource type
134 */
135static inline unsigned int pci_calc_resource_flags(unsigned int flags)
136{
137 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
138 return IORESOURCE_IO;
139
140 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
141 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
142
143 return IORESOURCE_MEM;
144}
145
146/*
147 * Find the extent of a PCI decode..
148 */
Olof Johanssonf797f9c2005-06-13 15:52:27 -0700149static u32 pci_size(u32 base, u32 maxbase, u32 mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150{
151 u32 size = mask & maxbase; /* Find the significant bits */
152 if (!size)
153 return 0;
154
155 /* Get the lowest of them to find the decode size, and
156 from that the extent. */
157 size = (size & ~(size-1)) - 1;
158
159 /* base == maxbase can be valid only if the BAR has
160 already been programmed with all 1s. */
161 if (base == maxbase && ((base | size) & mask) != mask)
162 return 0;
163
164 return size;
165}
166
Yinghai Lu07eddf32006-11-29 13:53:10 -0800167static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
168{
169 u64 size = mask & maxbase; /* Find the significant bits */
170 if (!size)
171 return 0;
172
173 /* Get the lowest of them to find the decode size, and
174 from that the extent. */
175 size = (size & ~(size-1)) - 1;
176
177 /* base == maxbase can be valid only if the BAR has
178 already been programmed with all 1s. */
179 if (base == maxbase && ((base | size) & mask) != mask)
180 return 0;
181
182 return size;
183}
184
185static inline int is_64bit_memory(u32 mask)
186{
187 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
188 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
189 return 1;
190 return 0;
191}
192
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
194{
195 unsigned int pos, reg, next;
196 u32 l, sz;
197 struct resource *res;
198
199 for(pos=0; pos<howmany; pos = next) {
Yinghai Lu07eddf32006-11-29 13:53:10 -0800200 u64 l64;
201 u64 sz64;
202 u32 raw_sz;
203
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 next = pos+1;
205 res = &dev->resource[pos];
206 res->name = pci_name(dev);
207 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
208 pci_read_config_dword(dev, reg, &l);
209 pci_write_config_dword(dev, reg, ~0);
210 pci_read_config_dword(dev, reg, &sz);
211 pci_write_config_dword(dev, reg, l);
212 if (!sz || sz == 0xffffffff)
213 continue;
214 if (l == 0xffffffff)
215 l = 0;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800216 raw_sz = sz;
217 if ((l & PCI_BASE_ADDRESS_SPACE) ==
218 PCI_BASE_ADDRESS_SPACE_MEMORY) {
Amos Waterland3c6de922005-09-22 00:48:19 -0700219 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
Yinghai Lu07eddf32006-11-29 13:53:10 -0800220 /*
221 * For 64bit prefetchable memory sz could be 0, if the
222 * real size is bigger than 4G, so we need to check
223 * szhi for that.
224 */
225 if (!is_64bit_memory(l) && !sz)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 continue;
227 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
228 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
229 } else {
230 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
231 if (!sz)
232 continue;
233 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
234 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
235 }
236 res->end = res->start + (unsigned long) sz;
237 res->flags |= pci_calc_resource_flags(l);
Yinghai Lu07eddf32006-11-29 13:53:10 -0800238 if (is_64bit_memory(l)) {
H. Peter Anvin17d6dc82006-04-18 17:19:52 -0700239 u32 szhi, lhi;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800240
H. Peter Anvin17d6dc82006-04-18 17:19:52 -0700241 pci_read_config_dword(dev, reg+4, &lhi);
242 pci_write_config_dword(dev, reg+4, ~0);
243 pci_read_config_dword(dev, reg+4, &szhi);
244 pci_write_config_dword(dev, reg+4, lhi);
Yinghai Lu07eddf32006-11-29 13:53:10 -0800245 sz64 = ((u64)szhi << 32) | raw_sz;
246 l64 = ((u64)lhi << 32) | l;
247 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 next++;
249#if BITS_PER_LONG == 64
Yinghai Lu07eddf32006-11-29 13:53:10 -0800250 if (!sz64) {
251 res->start = 0;
252 res->end = 0;
253 res->flags = 0;
254 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 }
Yinghai Lu07eddf32006-11-29 13:53:10 -0800256 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
257 res->end = res->start + sz64;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258#else
Yinghai Lu07eddf32006-11-29 13:53:10 -0800259 if (sz64 > 0x100000000ULL) {
260 printk(KERN_ERR "PCI: Unable to handle 64-bit "
261 "BAR for device %s\n", pci_name(dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 res->start = 0;
263 res->flags = 0;
Bjorn Helgaasea285022006-06-09 11:28:29 -0700264 } else if (lhi) {
H. Peter Anvin17d6dc82006-04-18 17:19:52 -0700265 /* 64-bit wide address, treat as disabled */
Yinghai Lu07eddf32006-11-29 13:53:10 -0800266 pci_write_config_dword(dev, reg,
267 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
H. Peter Anvin17d6dc82006-04-18 17:19:52 -0700268 pci_write_config_dword(dev, reg+4, 0);
269 res->start = 0;
270 res->end = sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 }
272#endif
273 }
274 }
275 if (rom) {
276 dev->rom_base_reg = rom;
277 res = &dev->resource[PCI_ROM_RESOURCE];
278 res->name = pci_name(dev);
279 pci_read_config_dword(dev, rom, &l);
280 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
281 pci_read_config_dword(dev, rom, &sz);
282 pci_write_config_dword(dev, rom, l);
283 if (l == 0xffffffff)
284 l = 0;
285 if (sz && sz != 0xffffffff) {
Amos Waterland3c6de922005-09-22 00:48:19 -0700286 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287 if (sz) {
288 res->flags = (l & IORESOURCE_ROM_ENABLE) |
Gary Hadebb446092007-12-11 17:09:13 -0800289 IORESOURCE_MEM | IORESOURCE_PREFETCH |
290 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 res->start = l & PCI_ROM_ADDRESS_MASK;
292 res->end = res->start + (unsigned long) sz;
293 }
294 }
295 }
296}
297
Sam Ravnborg0ab2b572008-02-17 10:45:28 +0100298void __devinit pci_read_bridge_bases(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299{
300 struct pci_dev *dev = child->self;
301 u8 io_base_lo, io_limit_lo;
302 u16 mem_base_lo, mem_limit_lo;
303 unsigned long base, limit;
304 struct resource *res;
305 int i;
306
307 if (!dev) /* It's a host bus, nothing to read */
308 return;
309
310 if (dev->transparent) {
311 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
Ivan Kokshaysky90b54922005-06-07 04:07:02 +0400312 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
313 child->resource[i] = child->parent->resource[i - 3];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314 }
315
316 for(i=0; i<3; i++)
317 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
318
319 res = child->resource[0];
320 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
321 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
322 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
323 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
324
325 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
326 u16 io_base_hi, io_limit_hi;
327 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
328 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
329 base |= (io_base_hi << 16);
330 limit |= (io_limit_hi << 16);
331 }
332
333 if (base <= limit) {
334 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Daniel Yeisley9d265122005-12-05 07:06:43 -0500335 if (!res->start)
336 res->start = base;
337 if (!res->end)
338 res->end = limit + 0xfff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339 }
340
341 res = child->resource[1];
342 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
343 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
344 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
345 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
346 if (base <= limit) {
347 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
348 res->start = base;
349 res->end = limit + 0xfffff;
350 }
351
352 res = child->resource[2];
353 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
354 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
355 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
356 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
357
358 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
359 u32 mem_base_hi, mem_limit_hi;
360 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
361 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
362
363 /*
364 * Some bridges set the base > limit by default, and some
365 * (broken) BIOSes do not initialize them. If we find
366 * this, just assume they are not being used.
367 */
368 if (mem_base_hi <= mem_limit_hi) {
369#if BITS_PER_LONG == 64
370 base |= ((long) mem_base_hi) << 32;
371 limit |= ((long) mem_limit_hi) << 32;
372#else
373 if (mem_base_hi || mem_limit_hi) {
374 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
375 return;
376 }
377#endif
378 }
379 }
380 if (base <= limit) {
381 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
382 res->start = base;
383 res->end = limit + 0xfffff;
384 }
385}
386
Sam Ravnborg96bde062007-03-26 21:53:30 -0800387static struct pci_bus * pci_alloc_bus(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388{
389 struct pci_bus *b;
390
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100391 b = kzalloc(sizeof(*b), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 if (b) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393 INIT_LIST_HEAD(&b->node);
394 INIT_LIST_HEAD(&b->children);
395 INIT_LIST_HEAD(&b->devices);
396 }
397 return b;
398}
399
400static struct pci_bus * __devinit
401pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
402{
403 struct pci_bus *child;
404 int i;
405
406 /*
407 * Allocate a new bus, and inherit stuff from the parent..
408 */
409 child = pci_alloc_bus();
410 if (!child)
411 return NULL;
412
413 child->self = bridge;
414 child->parent = parent;
415 child->ops = parent->ops;
416 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200417 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418 child->bridge = get_device(&bridge->dev);
419
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400420 /* initialize some portions of the bus device, but don't register it
421 * now as the parent is not properly set up yet. This device will get
422 * registered later in pci_bus_add_devices()
423 */
424 child->dev.class = &pcibus_class;
425 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426
427 /*
428 * Set up the primary, secondary and subordinate
429 * bus numbers.
430 */
431 child->number = child->secondary = busnr;
432 child->primary = parent->secondary;
433 child->subordinate = 0xff;
434
435 /* Set up default resource pointers and names.. */
436 for (i = 0; i < 4; i++) {
437 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
438 child->resource[i]->name = child->name;
439 }
440 bridge->subordinate = child;
441
442 return child;
443}
444
Sam Ravnborg451124a2008-02-02 22:33:43 +0100445struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446{
447 struct pci_bus *child;
448
449 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700450 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800451 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800453 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700454 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 return child;
456}
457
Sam Ravnborg96bde062007-03-26 21:53:30 -0800458static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700459{
460 struct pci_bus *parent = child->parent;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700461
462 /* Attempts to fix that up are really dangerous unless
463 we're going to re-assign all bus numbers. */
464 if (!pcibios_assign_all_busses())
465 return;
466
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700467 while (parent->parent && parent->subordinate < max) {
468 parent->subordinate = max;
469 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
470 parent = parent->parent;
471 }
472}
473
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474/*
475 * If it's a bridge, configure it and scan the bus behind it.
476 * For CardBus bridges, we don't scan behind as the devices will
477 * be handled by the bridge driver itself.
478 *
479 * We need to process bridges in two passes -- first we scan those
480 * already configured by the BIOS and after we are done with all of
481 * them, we proceed to assigning numbers to the remaining buses in
482 * order to avoid overlaps between old and new bus numbers.
483 */
Sam Ravnborg0ab2b572008-02-17 10:45:28 +0100484int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485{
486 struct pci_bus *child;
487 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100488 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 u16 bctl;
490
491 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
492
493 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
494 pci_name(dev), buses & 0xffffff, pass);
495
496 /* Disable MasterAbortMode during probing to avoid reporting
497 of bus errors (in some architectures) */
498 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
499 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
500 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
501
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
503 unsigned int cmax, busnr;
504 /*
505 * Bus already configured by firmware, process it in the first
506 * pass and just note the configuration.
507 */
508 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000509 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510 busnr = (buses >> 8) & 0xFF;
511
512 /*
513 * If we already got to this bus through a different bridge,
514 * ignore it. This can happen with the i450NX chipset.
515 */
516 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
517 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
518 pci_domain_nr(bus), busnr);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000519 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520 }
521
Rajesh Shah6ef6f0e2005-04-28 00:25:49 -0700522 child = pci_add_new_bus(bus, dev, busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 if (!child)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000524 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 child->primary = buses & 0xFF;
526 child->subordinate = (buses >> 16) & 0xFF;
Gary Hade11949252007-10-08 16:24:16 -0700527 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528
529 cmax = pci_scan_child_bus(child);
530 if (cmax > max)
531 max = cmax;
532 if (child->subordinate > max)
533 max = child->subordinate;
534 } else {
535 /*
536 * We need to assign a number to this bus which we always
537 * do in the second pass.
538 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700539 if (!pass) {
540 if (pcibios_assign_all_busses())
541 /* Temporarily disable forwarding of the
542 configuration cycles on all bridges in
543 this bus segment to avoid possible
544 conflicts in the second pass between two
545 bridges programmed with overlapping
546 bus ranges. */
547 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
548 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000549 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700550 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551
552 /* Clear errors */
553 pci_write_config_word(dev, PCI_STATUS, 0xffff);
554
Rajesh Shahcc574502005-04-28 00:25:47 -0700555 /* Prevent assigning a bus number that already exists.
556 * This can happen when a bridge is hot-plugged */
557 if (pci_find_bus(pci_domain_nr(bus), max+1))
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000558 goto out;
Rajesh Shah6ef6f0e2005-04-28 00:25:49 -0700559 child = pci_add_new_bus(bus, dev, ++max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 buses = (buses & 0xff000000)
561 | ((unsigned int)(child->primary) << 0)
562 | ((unsigned int)(child->secondary) << 8)
563 | ((unsigned int)(child->subordinate) << 16);
564
565 /*
566 * yenta.c forces a secondary latency timer of 176.
567 * Copy that behaviour here.
568 */
569 if (is_cardbus) {
570 buses &= ~0xff000000;
571 buses |= CARDBUS_LATENCY_TIMER << 24;
572 }
573
574 /*
575 * We need to blast all three values with a single write.
576 */
577 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
578
579 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -0700580 child->bridge_ctl = bctl;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700581 /*
582 * Adjust subordinate busnr in parent buses.
583 * We do this before scanning for children because
584 * some devices may not be detected if the bios
585 * was lazy.
586 */
587 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 /* Now we can scan all subordinate buses... */
589 max = pci_scan_child_bus(child);
Kristen Accardie3ac86d2006-01-17 16:57:01 -0800590 /*
591 * now fix it up again since we have found
592 * the real value of max.
593 */
594 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595 } else {
596 /*
597 * For CardBus bridges, we leave 4 bus numbers
598 * as cards with a PCI-to-PCI bridge can be
599 * inserted later.
600 */
Dominik Brodowski49887942005-12-08 16:53:12 +0100601 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
602 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700603 if (pci_find_bus(pci_domain_nr(bus),
604 max+i+1))
605 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100606 while (parent->parent) {
607 if ((!pcibios_assign_all_busses()) &&
608 (parent->subordinate > max) &&
609 (parent->subordinate <= max+i)) {
610 j = 1;
611 }
612 parent = parent->parent;
613 }
614 if (j) {
615 /*
616 * Often, there are two cardbus bridges
617 * -- try to leave one valid bus number
618 * for each one.
619 */
620 i /= 2;
621 break;
622 }
623 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700624 max += i;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700625 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626 }
627 /*
628 * Set the subordinate bus number to its real value.
629 */
630 child->subordinate = max;
631 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
632 }
633
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
635
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200636 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +0100637 while (bus->parent) {
638 if ((child->subordinate > bus->subordinate) ||
639 (child->number > bus->subordinate) ||
640 (child->number < bus->number) ||
641 (child->subordinate < bus->number)) {
Joe Perchesa6f29a92007-11-19 17:48:29 -0800642 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200643 "hidden behind%s bridge #%02x (-#%02x)\n",
644 child->number, child->subordinate,
645 (bus->number > child->subordinate &&
646 bus->subordinate < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -0800647 "wholly" : "partially",
648 bus->self->transparent ? " transparent" : "",
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200649 bus->number, bus->subordinate);
Dominik Brodowski49887942005-12-08 16:53:12 +0100650 }
651 bus = bus->parent;
652 }
653
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000654out:
655 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
656
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 return max;
658}
659
660/*
661 * Read interrupt line and base address registers.
662 * The architecture-dependent code can tweak these, of course.
663 */
664static void pci_read_irq(struct pci_dev *dev)
665{
666 unsigned char irq;
667
668 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -0800669 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 if (irq)
671 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
672 dev->irq = irq;
673}
674
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +0200675#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -0800676
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677/**
678 * pci_setup_device - fill in class and map information of a device
679 * @dev: the device structure to fill
680 *
681 * Initialize the device structure with information about the device's
682 * vendor,class,memory and IO-space addresses,IRQ lines etc.
683 * Called at initialisation of the PCI subsystem and by CardBus services.
684 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
685 * or CardBus).
686 */
687static int pci_setup_device(struct pci_dev * dev)
688{
689 u32 class;
690
691 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
692 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
693
694 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -0700695 dev->revision = class & 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696 class >>= 8; /* upper 3 bytes */
697 dev->class = class;
698 class >>= 8;
699
700 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
701 dev->vendor, dev->device, class, dev->hdr_type);
702
703 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700704 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705
706 /* Early fixups, before probing the BARs */
707 pci_fixup_device(pci_fixup_early, dev);
708 class = dev->class >> 8;
709
710 switch (dev->hdr_type) { /* header type */
711 case PCI_HEADER_TYPE_NORMAL: /* standard header */
712 if (class == PCI_CLASS_BRIDGE_PCI)
713 goto bad;
714 pci_read_irq(dev);
715 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
716 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
717 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +0100718
719 /*
720 * Do the ugly legacy mode stuff here rather than broken chip
721 * quirk code. Legacy mode ATA controllers have fixed
722 * addresses. These are not always echoed in BAR0-3, and
723 * BAR0-3 in a few cases contain junk!
724 */
725 if (class == PCI_CLASS_STORAGE_IDE) {
726 u8 progif;
727 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
728 if ((progif & 1) == 0) {
Linus Torvaldsaf1bff42007-12-10 07:40:54 -0800729 dev->resource[0].start = 0x1F0;
730 dev->resource[0].end = 0x1F7;
731 dev->resource[0].flags = LEGACY_IO_RESOURCE;
732 dev->resource[1].start = 0x3F6;
733 dev->resource[1].end = 0x3F6;
734 dev->resource[1].flags = LEGACY_IO_RESOURCE;
Alan Cox368c73d2006-10-04 00:41:26 +0100735 }
736 if ((progif & 4) == 0) {
Linus Torvaldsaf1bff42007-12-10 07:40:54 -0800737 dev->resource[2].start = 0x170;
738 dev->resource[2].end = 0x177;
739 dev->resource[2].flags = LEGACY_IO_RESOURCE;
740 dev->resource[3].start = 0x376;
741 dev->resource[3].end = 0x376;
742 dev->resource[3].flags = LEGACY_IO_RESOURCE;
Alan Cox368c73d2006-10-04 00:41:26 +0100743 }
744 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 break;
746
747 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
748 if (class != PCI_CLASS_BRIDGE_PCI)
749 goto bad;
750 /* The PCI-to-PCI bridge spec requires that subtractive
751 decoding (i.e. transparent) bridge must have programming
752 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -0800753 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754 dev->transparent = ((dev->class & 0xff) == 1);
755 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
756 break;
757
758 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
759 if (class != PCI_CLASS_BRIDGE_CARDBUS)
760 goto bad;
761 pci_read_irq(dev);
762 pci_read_bases(dev, 1, 0);
763 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
764 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
765 break;
766
767 default: /* unknown header */
768 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
769 pci_name(dev), dev->hdr_type);
770 return -1;
771
772 bad:
773 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
774 pci_name(dev), class, dev->hdr_type);
775 dev->class = PCI_CLASS_NOT_DEFINED;
776 }
777
778 /* We found a fine healthy device, go go go... */
779 return 0;
780}
781
782/**
783 * pci_release_dev - free a pci device structure when all users of it are finished.
784 * @dev: device that's been disconnected
785 *
786 * Will be called only by the device core when all users of this pci device are
787 * done.
788 */
789static void pci_release_dev(struct device *dev)
790{
791 struct pci_dev *pci_dev;
792
793 pci_dev = to_pci_dev(dev);
794 kfree(pci_dev);
795}
796
Keshavamurthy, Anil S994a65e2007-10-21 16:41:46 -0700797static void set_pcie_port_type(struct pci_dev *pdev)
798{
799 int pos;
800 u16 reg16;
801
802 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
803 if (!pos)
804 return;
805 pdev->is_pcie = 1;
806 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
807 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
808}
809
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810/**
811 * pci_cfg_space_size - get the configuration space size of the PCI device.
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700812 * @dev: PCI device
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813 *
814 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
815 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
816 * access it. Maybe we don't have a way to generate extended config space
817 * accesses, or the device is behind a reverse Express bridge. So we try
818 * reading the dword at 0x100 which must either be 0 or a valid extended
819 * capability header.
820 */
Benjamin Herrenschmidtac7dc652005-12-13 18:09:16 +1100821int pci_cfg_space_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822{
823 int pos;
824 u32 status;
825
826 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
827 if (!pos) {
828 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
829 if (!pos)
830 goto fail;
831
832 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
833 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
834 goto fail;
835 }
836
837 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
838 goto fail;
839 if (status == 0xffffffff)
840 goto fail;
841
842 return PCI_CFG_SPACE_EXP_SIZE;
843
844 fail:
845 return PCI_CFG_SPACE_SIZE;
846}
847
848static void pci_release_bus_bridge_dev(struct device *dev)
849{
850 kfree(dev);
851}
852
Michael Ellerman65891212007-04-05 17:19:08 +1000853struct pci_dev *alloc_pci_dev(void)
854{
855 struct pci_dev *dev;
856
857 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
858 if (!dev)
859 return NULL;
860
Michael Ellerman65891212007-04-05 17:19:08 +1000861 INIT_LIST_HEAD(&dev->bus_list);
862
Michael Ellerman4aa9bc92007-04-05 17:19:10 +1000863 pci_msi_init_pci_dev(dev);
864
Michael Ellerman65891212007-04-05 17:19:08 +1000865 return dev;
866}
867EXPORT_SYMBOL(alloc_pci_dev);
868
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869/*
870 * Read the config data for a PCI device, sanity-check it
871 * and fill in the dev structure...
872 */
873static struct pci_dev * __devinit
874pci_scan_device(struct pci_bus *bus, int devfn)
875{
876 struct pci_dev *dev;
877 u32 l;
878 u8 hdr_type;
879 int delay = 1;
880
881 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
882 return NULL;
883
884 /* some broken boards return 0 or ~0 if a slot is empty: */
885 if (l == 0xffffffff || l == 0x00000000 ||
886 l == 0x0000ffff || l == 0xffff0000)
887 return NULL;
888
889 /* Configuration request Retry Status */
890 while (l == 0xffff0001) {
891 msleep(delay);
892 delay *= 2;
893 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
894 return NULL;
895 /* Card hasn't responded in 60 seconds? Must be stuck. */
896 if (delay > 60 * 1000) {
897 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
898 "responding\n", pci_domain_nr(bus),
899 bus->number, PCI_SLOT(devfn),
900 PCI_FUNC(devfn));
901 return NULL;
902 }
903 }
904
905 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
906 return NULL;
907
Michael Ellermanbab41e92007-04-05 17:19:09 +1000908 dev = alloc_pci_dev();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909 if (!dev)
910 return NULL;
911
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912 dev->bus = bus;
913 dev->sysdata = bus->sysdata;
914 dev->dev.parent = bus->bridge;
915 dev->dev.bus = &pci_bus_type;
916 dev->devfn = devfn;
917 dev->hdr_type = hdr_type & 0x7f;
918 dev->multifunction = !!(hdr_type & 0x80);
919 dev->vendor = l & 0xffff;
920 dev->device = (l >> 16) & 0xffff;
921 dev->cfg_size = pci_cfg_space_size(dev);
Linas Vepstas82081792006-07-10 04:44:46 -0700922 dev->error_state = pci_channel_io_normal;
Keshavamurthy, Anil S994a65e2007-10-21 16:41:46 -0700923 set_pcie_port_type(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924
925 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
926 set this higher, assuming the system even supports it. */
927 dev->dma_mask = 0xffffffff;
928 if (pci_setup_device(dev) < 0) {
929 kfree(dev);
930 return NULL;
931 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +1000932
933 return dev;
934}
935
Sam Ravnborg96bde062007-03-26 21:53:30 -0800936void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +1000937{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 device_initialize(&dev->dev);
939 dev->dev.release = pci_release_dev;
940 pci_dev_get(dev);
941
Christoph Hellwig87348132006-12-06 20:32:33 -0800942 set_dev_node(&dev->dev, pcibus_to_node(bus));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -0800944 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945 dev->dev.coherent_dma_mask = 0xffffffffull;
946
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -0800947 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -0800948 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -0800949
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950 /* Fix up broken headers */
951 pci_fixup_device(pci_fixup_header, dev);
952
953 /*
954 * Add the device to our list of discovered devices
955 * and the bus list for fixup functions, etc.
956 */
Zhang Yanmind71374d2006-06-02 12:35:43 +0800957 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800959 up_write(&pci_bus_sem);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +1000960}
961
Sam Ravnborg451124a2008-02-02 22:33:43 +0100962struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +1000963{
964 struct pci_dev *dev;
965
966 dev = pci_scan_device(bus, devfn);
967 if (!dev)
968 return NULL;
969
970 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971
972 return dev;
973}
Adrian Bunkb73e9682007-11-21 15:07:11 -0800974EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975
976/**
977 * pci_scan_slot - scan a PCI slot on a bus for devices.
978 * @bus: PCI bus to scan
979 * @devfn: slot number to scan (must have zero function.)
980 *
981 * Scan a PCI slot on the specified PCI bus for devices, adding
982 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -0800983 * will not have is_added set.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984 */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800985int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986{
987 int func, nr = 0;
988 int scan_all_fns;
989
990 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
991
992 for (func = 0; func < 8; func++, devfn++) {
993 struct pci_dev *dev;
994
995 dev = pci_scan_single_device(bus, devfn);
996 if (dev) {
997 nr++;
998
999 /*
1000 * If this is a single function device,
1001 * don't scan past the first function.
1002 */
1003 if (!dev->multifunction) {
1004 if (func > 0) {
1005 dev->multifunction = 1;
1006 } else {
1007 break;
1008 }
1009 }
1010 } else {
1011 if (func == 0 && !scan_all_fns)
1012 break;
1013 }
1014 }
1015 return nr;
1016}
1017
Sam Ravnborg0ab2b572008-02-17 10:45:28 +01001018unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019{
1020 unsigned int devfn, pass, max = bus->secondary;
1021 struct pci_dev *dev;
1022
1023 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1024
1025 /* Go find them, Rover! */
1026 for (devfn = 0; devfn < 0x100; devfn += 8)
1027 pci_scan_slot(bus, devfn);
1028
1029 /*
1030 * After performing arch-dependent fixup of the bus, look behind
1031 * all PCI-to-PCI bridges on this bus.
1032 */
1033 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1034 pcibios_fixup_bus(bus);
1035 for (pass=0; pass < 2; pass++)
1036 list_for_each_entry(dev, &bus->devices, bus_list) {
1037 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1038 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1039 max = pci_scan_bridge(bus, dev, max, pass);
1040 }
1041
1042 /*
1043 * We've scanned the bus and so we know all about what's on
1044 * the other side of any bridges that may be on this bus plus
1045 * any devices.
1046 *
1047 * Return how far we've got finding sub-buses.
1048 */
1049 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1050 pci_domain_nr(bus), bus->number, max);
1051 return max;
1052}
1053
Sam Ravnborg96bde062007-03-26 21:53:30 -08001054struct pci_bus * pci_create_bus(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001055 int bus, struct pci_ops *ops, void *sysdata)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056{
1057 int error;
1058 struct pci_bus *b;
1059 struct device *dev;
1060
1061 b = pci_alloc_bus();
1062 if (!b)
1063 return NULL;
1064
1065 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1066 if (!dev){
1067 kfree(b);
1068 return NULL;
1069 }
1070
1071 b->sysdata = sysdata;
1072 b->ops = ops;
1073
1074 if (pci_find_bus(pci_domain_nr(b), bus)) {
1075 /* If we already got to this bus through a different bridge, ignore it */
1076 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1077 goto err_out;
1078 }
Zhang Yanmind71374d2006-06-02 12:35:43 +08001079
1080 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081 list_add_tail(&b->node, &pci_root_buses);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001082 up_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083
1084 memset(dev, 0, sizeof(*dev));
1085 dev->parent = parent;
1086 dev->release = pci_release_bus_bridge_dev;
1087 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1088 error = device_register(dev);
1089 if (error)
1090 goto dev_reg_err;
1091 b->bridge = get_device(dev);
1092
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001093 b->dev.class = &pcibus_class;
1094 b->dev.parent = b->bridge;
1095 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1096 error = device_register(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097 if (error)
1098 goto class_dev_reg_err;
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001099 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 if (error)
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001101 goto dev_create_file_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102
1103 /* Create legacy_io and legacy_mem files for this bus */
1104 pci_create_legacy_files(b);
1105
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106 b->number = b->secondary = bus;
1107 b->resource[0] = &ioport_resource;
1108 b->resource[1] = &iomem_resource;
1109
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110 return b;
1111
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001112dev_create_file_err:
1113 device_unregister(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114class_dev_reg_err:
1115 device_unregister(dev);
1116dev_reg_err:
Zhang Yanmind71374d2006-06-02 12:35:43 +08001117 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 list_del(&b->node);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001119 up_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120err_out:
1121 kfree(dev);
1122 kfree(b);
1123 return NULL;
1124}
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001125
Sam Ravnborg0ab2b572008-02-17 10:45:28 +01001126struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001127 int bus, struct pci_ops *ops, void *sysdata)
1128{
1129 struct pci_bus *b;
1130
1131 b = pci_create_bus(parent, bus, ops, sysdata);
1132 if (b)
1133 b->subordinate = pci_scan_child_bus(b);
1134 return b;
1135}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001136EXPORT_SYMBOL(pci_scan_bus_parented);
1137
1138#ifdef CONFIG_HOTPLUG
1139EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140EXPORT_SYMBOL(pci_scan_slot);
1141EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1143#endif
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001144
1145static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1146{
1147 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1148 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1149
1150 if (a->bus->number < b->bus->number) return -1;
1151 else if (a->bus->number > b->bus->number) return 1;
1152
1153 if (a->devfn < b->devfn) return -1;
1154 else if (a->devfn > b->devfn) return 1;
1155
1156 return 0;
1157}
1158
1159/*
1160 * Yes, this forcably breaks the klist abstraction temporarily. It
1161 * just wants to sort the klist, not change reference counts and
1162 * take/drop locks rapidly in the process. It does all this while
1163 * holding the lock for the list, so objects can't otherwise be
1164 * added/removed while we're swizzling.
1165 */
1166static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1167{
1168 struct list_head *pos;
1169 struct klist_node *n;
1170 struct device *dev;
1171 struct pci_dev *b;
1172
1173 list_for_each(pos, list) {
1174 n = container_of(pos, struct klist_node, n_node);
1175 dev = container_of(n, struct device, knode_bus);
1176 b = to_pci_dev(dev);
1177 if (pci_sort_bf_cmp(a, b) <= 0) {
1178 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1179 return;
1180 }
1181 }
1182 list_move_tail(&a->dev.knode_bus.n_node, list);
1183}
1184
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08001185void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001186{
1187 LIST_HEAD(sorted_devices);
1188 struct list_head *pos, *tmp;
1189 struct klist_node *n;
1190 struct device *dev;
1191 struct pci_dev *pdev;
Greg Kroah-Hartmanb2490722007-11-01 19:41:16 -07001192 struct klist *device_klist;
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001193
Greg Kroah-Hartmanb2490722007-11-01 19:41:16 -07001194 device_klist = bus_get_device_klist(&pci_bus_type);
1195
1196 spin_lock(&device_klist->k_lock);
1197 list_for_each_safe(pos, tmp, &device_klist->k_list) {
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001198 n = container_of(pos, struct klist_node, n_node);
1199 dev = container_of(n, struct device, knode_bus);
1200 pdev = to_pci_dev(dev);
1201 pci_insertion_sort_klist(pdev, &sorted_devices);
1202 }
Greg Kroah-Hartmanb2490722007-11-01 19:41:16 -07001203 list_splice(&sorted_devices, &device_klist->k_list);
1204 spin_unlock(&device_klist->k_lock);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001205}